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Also, the system clock is used by the internal ADC to digitize the response signal and requires 16 clock periods to perform a single conversion. Therefore, with a maximum system clock frequency of 16.776MHz, the ADC can sample the response signal with a frequency of 1.0485MHz (i.e. a throughput rate of ≈1.04 MSPS). The ADC will convert 1024 samples and pass the digital results to the AD5933 MAC core where it performs a 1024 point DFT to determine the peak of the response signal at the ADC input.
PTM Published on: 2007-09-17
Australia