Built on a power-optimized 60 nm process, Intel Cyclone 10 LP FPGAs extend the low-power leadership of the previous generation Cyclone V FPGAs. The latest generation devices reduce core static power by up to 50 percent compared to the previous generations. All Intel Cyclone 10 LP FPGAs require only two core power supplies for operation, simplifying the power distribution network and saving board costs, board space, and design time. The flexibility of the Intel Cyclone 10 LP FPGA enables the user to design in a smaller, lower cost device, lowering total system costs.
The logic and routing core fabric sea of gates is surrounded on each side by I/O elements with a phase-locked loop (PLLs) in each corner. Embedded memory blocks (M9K) and 18 bit x 18 bit multipliers blocks are arranged in vertical columns. The architecture also includes highly efficient interconnect and low-skew clock networks, providing connectivity between logic structures for clock and data signals.
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- 1.0 V and 1.2 V core voltage options
- Logic elements (LEs): four-input look-up table (LUT) and register
- Abundant routing/metal interconnect between all LEs
- M9K: 9 Kb of embedded SRAM memory blocks, cascadable
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- One 18 × 18 or two 9 × 9 multiplier modes, cascadable
- Up to 15 dedicated clock pins that can drive up to 20 global clocks
- Up to four general purpose PLLs
- True LVDS and emulated LVDS transmitters and receivers
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Development Kit
| Image | Manufacturer Part Number | Description | Available Quantity | View Details |
|  | EK-10CL025U256 | CYCLONE 10 EVALUATION KIT | 194 - Immediate
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Published: 2017-09-19