Thermally Aware High-Power Inverter Board for Battery-Powered Applications
Nowadays, battery-powered motor-driven solutions may commonly deliver hundreds of watts power using very low operating voltages. In such applications, a correct management of currents flowing through the motor driving electronics is deemed necessary to ensure overall system efficiency and reliability. Indeed, motor currents may exceed tens of amperes, leading to increased power dissipation inside the inverter. More power to the inverter components results in higher temperatures, performance degradation end even sudden breaks if going above maximum allowed ratings. The optimization of thermal performance, in combination with a compact form factor, is a key aspect of the inverter design phase that might hide pitfalls if not properly addressed. An approach to this problem has been the production of prototypes successively refined using on-field validation. However, electrical and thermal evaluations were totally separated, and electrical-thermal coupling effects were never addressed during design. This usually resulted in several iterations and a long time to market. A more effective alternative method is currently available to optimize the electro-thermal performance of motor control systems by taking advantage of modern simulation technologies. Cadence® Celsius™ Thermal Solver, industry-leading electrical-thermal co-simulation software for system analysis, provides in just a few minutes a global and accurate assessment of design performance from both an electrical and thermal perspective. STMicroelectronics, a leading manufacturer of industrial motor control integrated circuits, fine-tuned its EVALSTDRIVE101 evaluation board using Celsius™. The result is an inverter for three-phase brushless motors capable of driving up to 15 Arms current that can be referenced by the final application designers. In this article, we take the opportunity to describe the workflow that allowed STMicroelectronics to put in production the EVALSTDRIVE101, reducing the effort needed for thermal optimization.
The EVALSTDRIVE101 is based on the STDRIVE101, a 75 V triple half-bridge gate driver with protections provided in a quad flat no-lead (QFN) 4x4 mm package, a perfect fit for battery-powered solutions and six STL110N10F7 power MOSFETs arranged into three half-bridges. Celsius™ dramatically simplified the EVALSTDRIVE101 optimization process achieving a compact and reliable design in a short timeframe. Simulation results, as discussed later, were used to iteratively adjust component placements, refine shapes of planes and traces, modify layer thickness, and add or remove vias to obtain the production-ready version of the inverter. The EVALSTDRIVE101 optimized layout consists of four layers with 2 oz copper, width of 11.4 cm and height of 9 cm that can deliver up to 15 Arms current to the load using a battery voltage of 36 V. From a thermal perspective, the most critical part of the EVALSTDRIVE101 is the power stage area that mainly includes power MOSFETs, shunt resistors, ceramic bypass capacitors, electrolytic bulk capacitors and connectors. The layout of this part was deeply shrunk to cover only half of the overall board size, i.e. 50 cm2. On this regard, special care was paid in the placement and routing of MOSFETs since these components are responsible for most of power losses during inverter operations. The copper area of all MOSFET drain terminals was maximized on the top layer and replicated and enlarged where possible for other layers to improve heat transmission toward the bottom of the board surface. In this way, both top and bottom surfaces of the board effectively contribute to heat dissipation by natural convection and radiation. Electrical and thermal connection among different layers was provided by vias of 0.5 mm diameter that facilitate air flow and improve cooling. A grid of vias are located right below the MOSFETs exposed pads, but their diameter was reduced to 0.3 mm to prevent solder paste reflows in the holes.
Estimate of power losses
Figure 1: Simulated top layer current density. (Image source: STMicroelectronics)
Figure 2: Simulated top layer steady state temperatures. (Image source: STMicroelectronics)
Thermal optimization of the EVALSTDRIVE101 started from an estimate of the power dissipated by the inverter during its operation being one input of the thermal simulator. The inverter losses can be split in two contributions: those due to Joule effect within board traces and those due to electronic components. While Celsius™ can precisely determine current densities and board losses directly by importing layout data, the losses due to electronic components must be computed. Although a circuit simulator could provide very accurate results, it was decided to use simplified formulae to obtain a reasonable estimate of the power losses, though with approximations. Indeed, electrical models of components might be unavailable from manufacturers and difficult, or not feasible to implement by scratch due to lack of modeling data while provided formulae require only basic information from datasheets. Leaving out secondary phenomena, power dissipation of the inverter is dominated by losses inside shunt resistors Psh and the MOSFETs. These losses are by conduction Pcond, switching Psw, and diode drop Pdt:
Estimated power dissipation was 1.303 W for each MOSFET and 0.281 W for each shunt resistor.
Celsius™ allows designers to perform simulations that include an electrical analysis of the system showing current densities in traces and vias, as well as voltage drops. These simulations require designers to define current loops of interest using a circuit model for the system. The model adopted for each half-bridge of EVALSTDRIVE101 is shown in Figure 3. It consists of two constant current generators placed between the output and power supply connectors and three short circuits bypassing the MOSFETs and shunt resistor. The two current loops provide a good fitting with real case average currents throughout the supply rail and ground plane while the output path current is slightly oversized, a convenient operating condition for evaluating design robustness. Figure 4 and Figure 1 show the voltage drops and current density of the EVALSTDRIVE101 with a current of 15 Arms. Voltage drops with respect to ground reference highlight a particularly optimized layout with an absence of bottlenecks and well-balanced outputs at 28mV, 25mV, and 23mV for U, V, and W. Output U shows the highest voltage drop while output W, the lowest of the three because of the shorter path length from the power connector. The currents are well distributed in the various paths and have an average density below 15 A/mm2, which is the recommended value for power trace sizing. Some red areas are highlighted in proximity of the MOSFETs, shunt resistors and connectors. These represent a higher current density due to the components’ terminals being smaller than the underlying power traces. However, the maximum current density is far below the limit of 50 A/mm2, which could realistically lead to reliability issues.
Figure 3: Current loop modeling. (Image source: STMicroelectronics)
The simulator enables designers to set up and run steady-state or transient simulations. The former provides a single 2D temperature map for layers and components, while the latter provides maps for each simulated time instant and warmup curves at a cost of longer simulation time. Settings needed for steady-state simulation can be applied to a transient simulation, but this additionally requires the definition of power dissipation functions for the components. Transient simulations are suitable when defining different operating states for the system with power sources not simultaneously active and to assess the time needed to reach steady-state temperature.
Figure 4: Simulated inner layer voltage drops. (Image source: STMicroelectronics)
EVALSTDRIVE101 simulations were done at an ambient temperature of 28 °C with the heat transfer coefficient as boundary conditions and the two-resistor’s thermal models for the devices. These models were used instead of detailed thermal models like Delphi since they are directly available in components’ datasheets, although this slightly sacrifices the simulation accuracy. Steady state results for the EVALSTDRIVE101 are provided in Figure 4 and transient simulation results in Figure 5. Step power functions were used in the transient simulation to enable all MOSEFTs and shunt resistors at time zero. Simulations identified the U half-bridge area as the hottest of the board. The Q1 MOSFET (high-side) was at 94.06 °C followed by Q4 MOSFET (low-side), R24 and R23 shunt resistors with temperatures of 93.99 °C, 85.34 °C, and 85.58 °C, respectively.
Figure 5: Simulated U half-bridge components warm up. (Image source: STMicroelectronics)
Thermal characterization setup
An experimental characterization of EVALSTDRIVE101 thermal performance was done after production. Rather than using a motor connected to a braking bench, an equivalent testbench was considered for ease of implementation as shown in Figure 6. The EVALSTDRIVE101 was connected to a control board to generate the necessary driving signals and placed inside a plexiglass box to obtain system cooling by convection without accidental air flow. Above the box was placed one thermal imaging camera (model TVS-200 by Nippon Avionics), which framed the board through a hole in the cover of the box. A three-phase load was connected to the board outputs, and the system was supplied at 36 V. The load consists of three coils wired in a star configuration to emulate the motor. Each coil has a saturation current of 30 A, 300 µH inductance and only a 25 mΩ parasitic resistance. The low parasitic resistance considerably reduced the Joule heating effect inside the coils in favor of a lossless power transfer between the board and the load. Three sinusoidal currents were generated inside the coils at 15 Arms by applying proper sinusoidal voltages via the control board. With this method, the power stage worked in an operating condition very close to the final motor driving application with the advantage of not requiring a control loop.
Figure 6: Thermal characterization setup. (Image source: STMicroelectronics)
Power loss measurement
One factor affecting the quality of the simulation results is certainly the data accuracy of the power dissipated by each device on the power stage. This data was obtained using simplified formulae for both the MOSFETs and shunt resistors, thus approximations were introduced. Measurement was made on the board to evaluate the error in quantifying the dissipated power. The power loss Ploss of the board was measured as the difference between the input power Pin and the power delivered to the load at the three outputs PUout, PVout, and PWout. The measurement was made using an oscilloscope (model HDO6104-MS by Teledyne LeCroy) and applying the proper math functions to the waveforms: first, the point-by-point product of the voltage and current was computed, then the power was averaged over an integer number of sinusoid cycles. The following table shows the measurement results at ambient temperature and in a hot state when the power stage reached steady state condition. The overall value of power dissipated by the board previously estimated by formulae is also provided.
The results show a very good matching between measurements and estimates which is in line with introduced approximations. An overestimation of the measurement at room temperature of 1.5% is made by the formulae, which provides roughly a 3.9% underestimate compared with hot condition data. This result is in line with the variability associated with the on-resistance of the MOSFETs and shunt resistors since nominal values were used in the computations. As expected, all power values were higher at hot than at room temperature due to the increase of the resistances of the coils and MOSFETs with temperature. The data also shows a difference among the measured powers for the three outputs. This effect is due to the unbalancing of the three-phase load, because of slightly different values of L and R from coil to coil. This effect, however, plays a marginal role since the observed misalignment is lower than the one between the measurements and the estimate.
The generation of sinusoidal currents in the load and the acquisition of thermal images by the thermal imaging camera were simultaneously activated. The thermal imaging camera was previously configured to collect thermal images every 15 seconds and to include in every capture three temperature markers for components Q1, Q4, and R23. The system remained active until the steady-state condition was reached after about 25 minutes. The ambient temperature detected inside the box at the end of the test was roughly 28°C. Figure 7 shows the heating transient of the board that was derived from temperature markers and Figure 8 shows the final temperatures on the board. The measurement showed that the Q1 MOSFET was the hottest component on the entire board with a temperature of 93.8°C, while the Q4 MOSFET and R23 resistor reached 91.7°C and 82.6°C, respectively. As previously discussed, Celsius™ simulated the Q1 MOSFET temperature at 94.06°C, the Q4 MOSFET temperature at 93.99°C, and the R23 temperature at 85.58°C giving a very good matching with measurements. The same agreement can be also found in the time constant of heating transient as can be easily seen from direct comparison of Figure 5 with Figure 7.
Figure 7: Measured U half-bridge components warm up. (Image source: STMicroelectronics)
Figure 8: Measured top layer steady state temperatures. (Image source: STMicroelectronics)
STMicroelectronics recently released the EVALSTDRIVE101 evaluation board which was designed by taking advantage of the Cadence® Celsius™ Thermal Solver. The board targets high power and low voltage three-phase brushless motor control as needed by battery-powered applications. It includes a compact power stage of 50 cm2 which can deliver over 15 Arms current to the motor without a heatsink or additional cooling. Using different simulation features embedded in thermal simulator, it was possible not only to foresee the temperature profile of the board and its hot spots on the power stage components, but also to have a detailed description of voltage drops and current density along power traces which could be tricky or not feasible at all to obtain by experimental measurements. Simulation outputs enabled a fast optimization of board layout, adjusting placement and correcting layout weakness from early in the design to signoff. A thermal characterization with an infrared camera showed the good agreement between simulated and measured steady-state temperatures as well as the transient temperature profile, proving outstanding performance of the board and the effectiveness of the thermal simulator in helping designers to reduce design margin and achieve a quick time to market.
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