LTC6903,LTC6904 Datasheet by Analog Devices Inc.

View All Related Products | Download PDF Datasheet
LTLII‘IW TECHNOLOGY -I —II I||_|_||_|| «H F .”_T_| . HI L7HEWEAR 1
LTC6903/LTC6904
1
69034fe
Typical applicaTion
FeaTures
applicaTions
DescripTion
1kHz to 68MHz Serial
Port Programmable Oscillator
The LTC
®
6903/LTC6904 are low power self contained digital
frequency sources providing a precision frequency from
1kHz to 68MHz, set through a serial port. The LTC6903/
LTC6904 require no external components other than a
power supply bypass capacitor, and they operate over a
single wide supply range of 2.7V to 5.5V.
The LTC6903/LTC6904 feature a proprietary feedback loop
that linearizes the relationship between digital control set-
ting and frequency, resulting in a very simple frequency
setting equation:
fHz
DACkHzf MHz
OCT
=
<<22078
21024
16
8()
;
where OCT is a 4-bit digital code and DAC is a 10-bit
digital code.
The LTC6903 is controlled by a convenient SPI compatible
serial interface. The LTC6904 uses an industry standard
I2C compatible interface.
A Microcontroller Controlling Its Clock
n Precision Digitally Controlled Oscillator
n Power Management
n Direct Digital Frequency Synthesis (DDS)
Replacement
n Replacement for DAC and VCO
n Switched Capacitor Filter Clock
n 1kHz to 68MHz Square Wave Output
n 0.5% (Typ) Initial Frequency Accuracy
n Frequency Error <1.1% Over All Settings
n 10ppm/°C Typical Frequency Drift Over
Temperature
n 0.1% Resolution
n 1.7mA Typical Supply Current (f < 1MHz, VS = 2.7V)
n 2.7V to 5.5V Single- Supply Operation
n Jitter <0.4% Typical 1kHz to 8MHz
n Easy to Use SPI (LTC6903) or I2C (LTC6904) Serial
Interface
n Output Enable Pin
n –55°C to 125°C Operation
n MS8 Package
PIC16F73
MICROCONTROLLER
VDD
VSS
RC2/CCP1
VSS
RC5/SDO
RC3/SCK/SCL
LTC6903
0.01µF
GND
SDI
SCK
SEN
POWER-UP CLOCK
FREQUENCY IS 1039Hz
V+
5V
10Ω
10k
5V
OE
CLK
69034 TA01
CLK
OSC2/CLKOUT
OSC1/CLKIN
MCLR/VP–P
1µF
0.1µF
FREQUENCY ERROR (%)
–1.0
UNITS
40
30
20
10
0
–0.5
69034 TA01b
0 0.5 1.0
VS = 3V
TA = 25°C
f = 1039Hz
443
UNITS
TESTED
LTC6903 Frequency Error
Distribution
L, LT, LTC , LT M , Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 6342817 and 6614313.
LTC 6903 / LTC6904 TOP wEw mmmm uuuu L7LJCUEN2
LTC6903/LTC6904
2
69034fe
absoluTe MaxiMuM raTings
Total Supply Voltage (V+ to GND) ................................ 6V
Maximum Voltage
on any Pin ............. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Output Short-Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3)
LTC6903CMS8/LTC6904CMS8 ............40°C to 8C
LTC6903IMS8/LTC6904IMS8 .............. 40°C to 85°C
LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C
LTC6904MPMS8 ............................... 5C to 125°C
Specified Temperature Range (Note 4)
LTC6903CMS8/LTC6904CMS8 ................ C to 70°C
LTC6903IMS8/LTC6904IMS8 .............. 40°C to 85°C
LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C
LTC6904MPMS8 ............................... 5C to 125°C
Storage Temperature Range .................. 6C to 150°C
Lead Temperature (Soldering, 10 sec) ...................30C
(Note 1)
1
2
3
4
GND
SDI
SCK
SEN/ADR*
8
7
6
5
V+
OE
CLK
CLK
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 200°C/W
*SEN (LTC6903)
ADR (LTC6904)
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6903CMS8#PBF LTC6903CMS8#TRPBF LTABN 8-Lead Plastic MSOP 0°C to 70°C
LTC6903IMS8#PBF LTC6903IMS8#TRPBF LTABN 8-Lead Plastic MSOP –40°C to 85°C
LTC6903HMS8#PBF LTC6903HMS8#TRPBF LTABN 8-Lead Plastic MSOP –40°C to 125°C
LTC6904CMS8#PBF LTC6904CMS8#TRPBF LTAES 8-Lead Plastic MSOP 0°C to 70°C
LTC6904IMS8#PBF LTC6904IMS8#TRPBF LTAES 8-Lead Plastic MSOP –40°C to 85°C
LTC6904HMS8#PBF LTC6904HMS8#TRPBF LTAES 8-Lead Plastic MSOP –40°C to 125°C
LTC6904MPMS8#PBF LTC6904MPMS8#TRPBF LTFDX 8-Lead Plastic MSOP –55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
pin conFiguraTion
LTCéQOS/LTCéQOA L7 LJUW 3
LTC6903/LTC6904
3
69034fe
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSSupply Voltage Applied Between V+ and GND l2.7 5.5 V
IS, SHDN V+ Supply Current, Shutdown VS = 2.7V
VS = 5.5V
l
l
0.25
0.6
0.6
2.2
mA
mA
IS, DC V+ Supply Current, Single Output
Enabled
f = 68MHz, 5pF Load, V+ = 2.7V
f < 1MHz, V+ = 2.7V
f = 68MHz, 5pF Load, V+ = 5.5V
f < 1MHz, V+ = 5.5V
l
l
l
l
3.6
1.7
7
1.9
7
3.1
15
4.5
mA
mA
mA
mA
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆fi Initial Frequency Accuracy f = 1.039kHz, V+ = 3V, CLOAD = 5pF ±0.75 %
∆f Total Frequency Accuracy (Note 7) Single Output Active:
Over All Settings, V+ = 2.7V, CLOAD = 5pF
Over All Settings, V+ = 5.5V, CLOAD = 5pF
0.5
0.5
1.1
1.6
%
%
LTC6903CMS8, LTC6904CMS8:
Over All Settings, V+ = 2.7V, CLOAD = 5pF
Over All Settings, V+ = 5.5V, CLOAD = 5pF
l
l
0.5
0.5
1.65
2
%
%
LTC6903HMS8, LTC6903IMS8,
LTC6904HMS8, LTC6904IMS8,
LTC6904MPMS8:
Over All Settings, V+ = 2.7V, CLOAD = 5pF
Over All Settings, V+ = 5.5V, CLOAD = 5pF
l
l
0.5
0.5
1.9
2.2
%
%
fMAX Maximum Operating Frequency 68 MHz
fMIN Minimum Operating Frequency 1.039 kHz
∆f/∆T Frequency Drift Over Temperature 10 ppm/°C
∆f/∆V Frequency Drift Over Supply 0.05 %/V
Long-Term Frequency Stability 300 ppm/√kHr
Timing Jitter (See Graph) 1.039kHz to 8.5MHz
1.039kHz to 68MHz
0.4
1
%
%
Duty Cycle 1.039kHz to 1MHz
1.039kHz to 68MHz
l49 50
50
51 %
%
ROUT Output Resistance CLK, CLK Pins, V+ = 2.7V 45 Ω
VOH High Level Output Voltage V+ = 5.5V, 4mA Load
V+ = 2.7V, 4mA Load
l
l
4.8
2
5.3
2.3
V
V
V+ = 5.5V, 1mA Load
V+ = 2.7V, 1mA Load
l
l
5.2
2.3
5.45
2.55
V
V
VOL Low Level Output Voltage V+ = 5.5V, 4mA Load
V+ = 2.7V, 4mA Load
l
l
0.15
0.25
0.3
0.45
V
V
V+ = 5.5V, 1mA Load
V+ = 2.7V, 1mA Load
l
l
0.05
0.05
0.15
0.2
V
V
trOutput Rise Time (10% - 90%) V+ = 5.5V, RLOAD = ∞, CLOAD = 5pF
V+ = 2.7V, RLOAD = ∞, CLOAD = 5pF
1
1
ns
ns
tfOutput Fall Time (10% - 90%) V+ = 5.5V, RLOAD = ∞, CLOAD = 5pF
V+ = 2.7V, RLOAD = ∞, CLOAD = 5pF
1
1
ns
ns
LTC 6903 / LTC6904
LTC6903/LTC6904
4
69034fe
SYMBOL PARAMETER MIN TYP MAX UNITS
LTC6903 (Notes 5, 6)
fSCK Serial Port Clock Frequency l20 MHz
tCKHI Min Clock HIGH Time l25 ns
tCKLO Min Clock LOW Time l25 ns
tSU Min Setup Time – SDI to SCK l10 ns
tHLD Min Hold Time – SCK to SDI l10 ns
tLCH Min Latch Time – SEN to SEN l400 ns
tFCK Min First Clock – SEN to SCK l20 ns
LTC6904 (Notes 5, 6)
fSMB SMBus Operating Frequency l10 100 kHz
tBUF Bus Free Time Between STOP and START Condition l4.7 µs
tHD,STA Hold Time After (Repeated) START Condition l4.0 µs
tSU,STA Repeated START Condition Setup Time l4.7 µs
tSU,STO STOP Condition Setup Time l4.0 µs
LTC6904 (Notes 5, 6)
tHD,DAT Data Hold Time l300 ns
tSU,DAT Data Setup Time l250 ns
tLOW Clock LOW Period l4.7 µs
tHIGH Clock HIGH Period l4.0 50 µs
tfClock, Data Fall Time l300 ns
trClock, Data Rise Time l1000 ns
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum when the output is shorted indefinitely.
Note 3: The LTC6903CMS8, LTC6904CMS8, LTC6903IMS8 and
LTC6904IMS8 are guaranteed functional over the operating temperature
range of –40°C to 85°C.
Note 4: The LTC6903CMS8 and LTC6904CMS8 are guaranteed to meet
the specified performance limits over the 0°C to 70°C temperature range
and are designed, characterized and expected to meet the specified
performance from –40°C to 85°C but are not tested or QA sampled
at these temperatures. The LTC6903IMS8 and LTC6904IMS8 are
guaranteed to meet the specified performance limits over the –40°C to
85°C temperature range. The LTC6903HMS8 and LTC6904HMS8 are
guaranteed to meet the specified performance limits over the –40°C to
125°C temperature range. The LTC6904MPMS8 is guaranteed to meet the
specified performance limits over the –55°C to 125°C temperature range.
Note 5: All values are referenced to VIH and VIL levels.
Note 6: Guaranteed by design and not subject to test.
Note 7: Parts with tighter frequency accuracy are available. Consult LTC
Marketing for details.
serial porT elecTrical characTerisTics
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH Min High Level Input Voltage
SEN, SCK, SDI Pins
l0.67 V+V
VIL Max Low Level Input Voltage
SEN, SCK, SDI Pins
l0.33 V+V
IIN Digital Input Leakage
SEN, SCK, SDI Pins
l10 µA
LTCéQOS/LTCéQOA UM W1 L7 LJUW 5
LTC6903/LTC6904
5
69034fe
Typical perForMance characTerisTics
Integral Nonlinearity
DAC SETTING
0 200 400 600 800 1000
INTEGRAL NONLINEARITY (LSB)
69034 G01
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DAC SETTING
0 200 400 600 800 1000
DIFFERENTIAL NONLINEARITY (LSB)
69034 G01
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
TEMPERATURE (°C)
–40 –20 0 20 40 60 80 120100
FREQUENCY (%)
69034 G03
0.10
0.06
0.02
0.08
0.04
0
–0.02
–0.04
–0.06
–0.08
–0.10
Differential Nonlinearity Frequency vs Temperature
Peak-to-Peak Jitter vs Frequency
Supply Current vs Output
Frequency
Output Resistance vs Supply
Voltage
Output Spectrum at 20MHz Output Waveform at 68MHz Output Waveform at 20MHz
FREQUENCY (MHz)
0.1 1 10 100
PEAK-TO-PEAK JITTER (%)
69034 G04
10
1
0.1
0.01
V+ = 3V
FREQUENCY (MHz)
0.001 0.01 0.1 1 10 100
SUPPLY CURRENT (mA)
69034 G05
10
8
9
7
5
3
6
4
2
1
0
V+ = 3V
V+ = 5V
SUPPLY VOLTAGE (V)
3.5 4.52.5 3.0 4.0 5.0 5.5
OUTPUT RESISTANCE (Ω)
69034 G06
60
50
40
30
20
10
0
15MHz 25MHz
10dB/DIV
69034 G07
20
0
–80
20MHz
0.5/DIV
5ns/DIV 69034 G08CL = 10pF
V+ = 3V
0.5/DIV
10ns/DIV 69034 G08CL = 10pF
V+ = 3V
LTC 6903 / LTC6904 9 L fl L 0% > T :4 msn —1 6 L7LJ1‘JW
LTC6903/LTC6904
6
69034fe
pin FuncTions
GND (Pin 1): Negative Power Supply (Ground). Should
be tied directly to a ground plane for best performance.
SDI (Pin 2): Serial Data Input. Data for serial transfer is
presented on this pin.
SCK (Pin 3): Serial Port Clock. Input, positive edge trig-
gered. Clocks serial data in on rising edge.
SEN (Pin 4): Serial Port Enable (LTC6903 Only). Input,
active LOW. Initiates serial transaction when brought LOW,
finalizes transaction when brought HIGH after 16 clocks.
ADR (Pin 4): Serial Port Address (LTC6904 Only). Sets
the I2C serial port address.
CLK (Pin 5): Auxiliary Clock Output. Frequency set by
serial port.
CLK (Pin 6): Main Clock Output. Frequency set by serial port.
OE (Pin 7): Asynchronous Output Enable. CLK and CLK
are set LOW when this pin is LOW.
V+ (Pin 8): Positive Power Supply. This supply must be
kept free from noise and ripple. It should be bypassed
directly to a ground plane with a quality 0.1µF capacitor.
Additional bypass may be necessary for operation at high
frequency or under larger loads.
block DiagraM
21 3 4
67 5
8
+
MASTER
OSCILLATOR
fMO = 68MHz • kΩ ISET
V+ – VSET
PROGRAMMABLE
DIVIDER
+
ISET
VSET
A1
SERIAL PORT
V+OE
GND
DAC OCT
SDI SCK SEN (LTC6903)
ADR (LTC6904)
CLK CLK
69034 BD
LTCéQOS/LTCéQOA XXXXXXXXXXXXXXXXX j: in H H \\\\\\\\\\\\\\\\\\\\\\\\\\\ _L_JI_J L_l |_l |__I1_J— L7 LJUW 7
LTC6903/LTC6904
7
69034fe
TiMing DiagraMs
LTC6904 Timing Diagram
LTC6904 Typical Input Waveform—
Programming Frequency to 68MHz (ADR Pin Set LOW)
LTC6903 Timing Diagram
SEN
SDI
SCK
D15 D14 D13 D12 D11 D10 D8D9 D7 D6 D5 D4 D3 D2 D1 D0
69034 TD01
tSU, DAT
tHD, STA
tHD, DAT
SDA
SCL
tSU, STA
tHD, STA tSU, STO
69034 TD02
tBUF
tLOW
tHIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
trtf
ACK
123
ADDRESS
4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
69034 TD03
00101110
001011ADR WR
11111111
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
11111100
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0
ACK
STOPSTART
SDA
SCL
ACK
LTC 6903 / LTC6904 6.596(Hz)
LTC6903/LTC6904
8
69034fe
Theory oF operaTion
applicaTions inForMaTion
The LTC6903/LTC6904 contain an internal feedback loop
which controls a high frequency square wave VCO oper-
ating between 34MHz and 68MHz. The internal feedback
loop frequency is set over an octave by a 10-bit resistor
DAC. The VCO tracks the internal feedback loop frequency
and the output frequency of the VCO is divided by one of
sixteen possible powers of two.
Higher VCO frequencies and lower output divider settings
can result in higher output jitter. Random jitter at the
lower frequency ranges is very low because of the high
output divisor.
The higher frequency settings will display some deter-
ministic jitter from coupling between the control loop
and the output. This shows up in the frequency spectrum
as spurs separated from the fundamental frequency by
1MHz to 2MHz.
Frequency Setting Information
The frequency output of the LTC6903/LTC6904 is deter-
mined by the following equation:
fHz
DAC
OCT
=
22078
21024
()
where DAC is the integer value from 0-1023 represented
by the serial port register bits DAC[9:0] and OCT is the
integer value from 0-15 represented by the serial port
register bits OCT [3:0].
Use the following two steps to choose binary numbers
“OCT” and “DAC” in order to set frequency “f”:
1) Use Table 1 to ChooseOCT” or use the following
formula, rounding down to the integer value less than or
equal to the result.
OCT f
=
3 322 1039
. log
2) ChooseDAC” by the following formula, rounding DAC
to the nearest integer:
DAC =2048 2078(Hz)2(10+OCT)
f
For example, to set a frequency of 6.5MHz, first look
at Table 1 to find an OCT value. 6.5MHz falls between
4.25MHz and 8.5MHz yielding an OCT value of 12 or
1100. Substituting the OCT value of 12 and the desired
frequency of 6.5MHz into the previous equation results in:
DAC =2048 2078(Hz)2(10+12)
6.5e6(Hz)
=707.113
Rounding 707.113 to the nearest integer yields a DAC
value of 707 (or a 10-bit digital word of 1011000011.)
Table 1. Output Frequency Range vs OCT Settling
(Frequency Resolution 0.001 • f)
f ≥ f < OCT
34.05MHz 68.03MHz 15
17.02MHz 34.01MHz 14
8.511MHz 17.01MHz 13
4.256MHz 8.503MHz 12
2.128MHz 4.252MHz 11
1.064MHz 2.126MHz 10
532kHz 1063kHz 9
266kHz 531.4kHz 8
133kHz 265.7kHz 7
66.5kHz 132.9kHz 6
33.25kHz 66.43kHz 5
16.62kHz 33.22kHz 4
8.312kHz 16.61kHz 3
4.156kHz 8.304kHz 2
2.078kHz 4.152kHz 1
1.039kHz 2.076kHz 0
LTCéQOS/LTCéQOA L7 LJUW 9
LTC6903/LTC6904
9
69034fe
applicaTions inForMaTion
Power-Up State
When power is first applied to the LTC6903/LTC6904,
all register values are automatically reset to 0. This results
in an output frequency of 1.039kHz with both outputs active.
Output Spectrum
In most frequency ranges, the output of the LTC6903/
LTC6904 is generated as a division of the higher internal
clock frequency. This helps to minimize jitter and sub-
harmonics at the output of the device. In the highest
frequency ranges, the division ratio is reduced, which
will result in greater cycle-to-cycle jitter as well as spurs
at the internal sampling frequency. Because the internal
control loop runs at 1MHz to 2MHz without regard to the
output frequency, output spurs separated from the set
frequency by 1MHz to 2MHz may be observed. These
spurs are characteristically more than 30dB below the
level of the set frequency.
Frequency Settling
When frequency settings change, the settling time and
shape differ depending on which bits are changed. Changing
only the OCT bits will result in an instantaneous change
in frequency for OCT values below 10. Values of 10 and
above may take up to 100µs to settle due to the action of
internal power conservation circuitry.
Changing the DAC bits will result in a smooth transition
between the frequencies, occupying at most 100µs, with
little overshoot.
Changing both the OCT and DAC bits simultaneously may
result in considerable excursion beyond the frequencies
requested before settling.
It should be noted that changing the DAC bits at the lower
frequency ranges will result in a seemingly instantaneous
frequency change because the settling time depends on
the internal loop frequency rather than the set frequency.
Power Supply Bypass
In order to obtain the accuracies represented in this data
sheet, it is necessary to provide excellent bypass on the
power supply. Adequate bypass is aF capacitor in
parallel with a 0.01µF capacitor connected within a few
millimeters of the power supply leads.
Monotonicity and Linearity
The DAC in the LTC6903/LTC6904 is guaranteed to be
10-bit monotonic. Nonlinearity of the DAC is less than 1%.
Additionally, the LTC6903/LTC6904 is guaranteed to be
monotonic when switching between octaves with the
OCT setting bits. For example, the frequency output with
a DAC setting of “1111111111” and an OCT setting of
“1100” will always be lower than the frequency output
with a DAC setting of “0000000000” and an OCT setting
of “1101”. Linearity at these transition points is typically
around 3 LSBs.
Output Loading and Accuracy
Improper loading of the outputs of the LTC6903/LTC6904,
especially with poor power supply bypassing, will result in
accuracy problems. At low frequencies, capacitive loading
of the output is not a concern. At frequencies above 1MHz,
attention should be paid to minimize the capacitive load
on the CLK and CLK pins.
The LTC6903/LTC6904 is designed to drive up to 5pF
on each output with no degradation in accuracy. 5pF is
equivalent to one to two HC series logic inputs. A standard
10x oscilloscope probe usually presents between 10pF
and 15pF of capacitive load.
It is strongly suggested that a high speed buffer is used
when driving more than one or two logic inputs, when
driving a line more than 5 centimeters in length, or a
capacitive load greater than 5pF.
LTC 6903 / LTC6904 ‘IO
LTC6903/LTC6904
10
69034fe
applicaTions inForMaTion
Output Control
The CLK and CLK outputs of the LTC6903/LTC6904 are
individually controllable through the serial port as de-
scribed in Table 2 below. The low power mode may also
be accessed through these control bits. It is preferred
that unused outputs be disabled in order to reduce power
dissipation and improve accuracy.
Disabling an unused output will improve accuracy of
operation at frequencies above 1MHz. An unused output
running with no load typically degrades frequency ac-
curacy up to 0.2% at 68MHz. An unused output running
into a 5pF load typically degrades frequency accuracy up
to 0.5% at 68MHz.
Table 2. Output Configuration
CNF1 CNF0 CLK CLK
0 0 ON CLK + 180°
0 1 OFF ON
1 0 ON OFF
1 1 Powered-Down*
*Powered-Down: When in this mode, the chip is in a low power state
and will require approximately 100µs to recover. This is not the same
effect as the OE pin, which is fast, but uses more power supply current.
Serial Port Bitmap (LTC6903/LTC6904)
(All serial port register bits default LOW at power up)
Table 3
D15 D14 D13 D12 D11 D10 D9 D8
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
D7 D6 D5 D4 D3 D2 D1 D0
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0
Serial Port Register Description
OCT[3:0] – Frequency Divider Setting. (See Frequency
Setting Information Section)
DAC[9:0] – Master Oscillator Frequency Setting. (See
Frequency Setting Information Section)
CNF[1:0] – Output Configuration. This controls outputs
CLK and CLK according to Table 2.
LTC6903 SPI Compatible Interface
A serial data transfer is composed of sixteen (16) bits of
data labeled D15 through D0. D15 is the first bit of data
presented in each transaction. All serial port register bits
are set LOW on power-up.
Writing Data (LTC6903 Only)
When the SEN line is brought LOW, serial data presented
on the SDI input is clocked in on the rising edges of SCK
until SEN is brought HIGH. On every eighth rising edge
of SCK, the preceding 8-bits of data are clocked into the
internal register. It is therefore possible to clock in only
the 8 {D15 - D8} most significant bits of data rather than
completing an entire transfer.
The serial data transfer starts with the most significant
bit and ends with the least significant bit of the data, as
shown in the Timing Diagrams section.
LTCéQOS/LTCéQOA L7 LJUW 1 1
LTC6903/LTC6904
11
69034fe
applicaTions inForMaTion
LTC6904 I2C Interface
The LTC6904 communicates with a host (master) using the
standard I2C 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be HIGH when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required on
these lines. If the I2C interface is not driven with a standard
I2C compatible device, care must be taken to ensure that
the SDA line is released during the ACK cycle to prevent
bus contention.
The LTC6904 is a receive-only (slave) device. The master
can communicate with the LTC6904 using the write word
protocols as explained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
HIGH. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from LOW to HIGH while
SCL is HIGH. The bus is then free for communication with
another SMBus device.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The acknowledge related
clock pulse is generated by the master. The master releases
the SDA line (HIGH) during the acknowledge clock pulse.
The slave-receiver must pull down the SDA line during the
acknowledge clock pulse so that it remains a stable LOW
during the HIGH period of this clock pulse.
Write Word Protocol
The master initiates communication with the LTC6904
with a START condition and a 7-bit address followed by
the write bit (Wr) = 0. The LTC6904 acknowledges and
the master delivers the most significant data byte. Again
the LTC6904 acknowledges and the data is latched into
the most significant data byte input register. The master
then delivers the least significant data byte. The LTC6904
acknowledges once more and latches the data into the
least significant data byte input register. Lastly, the master
terminates the communication with a STOP condition.
Slave Address
The LTC6904 can respond to one of two 7-bit addresses.
The first 6 bits (MSBs) have been factory programmed
to 001011. The address pin, ADR (Pin 4) is programmed
by the user and determines the LSB of the slave address,
as shown in the table below:
ADR (Pin 4) LTC6904 Address
0 0010111
1 0010110
Write Word Protocol Used by the LTC6904
Slave Address AWr MS Data Byte A LS Data Byte A PS
7 11 8 1 8
69034 F01
1 11
S = START Condition, Wr = Write Bit = 0, A = Acknowledge, P = STOP Condition
LTC 6903 / LTC6904 may: 0127 (M51005) T EDEN] ‘ 532 320i 345 (‘25 135) 3 (205 u 42 1 u can 4 + n 55 (0‘65: 00‘5] ‘ P (0255) 12 L7LJCUEN2
LTC6903/LTC6904
12
69034fe
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
MSOP (MS8) 0307 REV F
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTCéQOS/LTCéQOA L7HEJWEGR 1 3
LTC6903/LTC6904
13
69034fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
D 12/11 Corrected LTC6903 Timing Diagram.
Corrected references to Frequency Setting Information section within Serial Port Register Description section.
7
10
E 3/12 Updated Absolute Maximum Ratings and Order Information.
Revised Notes 3 and 4 in Timing Characteristics.
2
4
(Revision history begins at Rev D)
LTCéQOS/LTC6904
LTC6903/LTC6904
14
69034fe
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
LT 0312 REV E • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC1799 1kHz to 30MHz ThinSOT Oscillator Single Output, Higher Frequency Operation
LTC6900 1kHz to 20MHz ThinSOT Oscillator Single Output, Lower Power
LTC6902 Mulitphase Oscillator with Spread Spectrum Modulation 1, 3 or 4-Phase Outputs
MUX INPUTS
S2 S1 S0 n
Output
Pulse Width
0
1
0
0
0
1
0
0
0
4
5
6
16/fCLK
32/fCLK
64/fCLK
1
0
1
0
1
0
0
1
0
1
1
1
7
8
9
10
128/fCLK
256/fCLK
512/fCLK
1024/fCLK
1 1 1 11 2048/fCLK
Wide Range Time Interval Generator (1.97 Seconds to 4 Microseconds)
U6
LTC6903
GND
SDI
SCK
SEN
1
2
3
4
TRIG
< TRIGGER PULSE WIDTH < OUTPUT PULSE WIDTH
fCLK
SDI
SCK
SEN
8
7
6
5
V+
OE
CLK
69034 TA02
CLK
74HC4040
PHILIPS
SEMICONDUCTOR
MUX SELECT ADDRESS LINES
7
5
2
13
Q8
910
11
52
8
8
16
16
6
3
4
14
1
Q12
12
15
Q1
MR
CLK
63
1
4
Q
Q
R
PS
CLK
D
Q2
Q3
Q4
Q5
Q6
Q7
Q9
Q10
Q11
74HC251
PHILIPS
SEMICONDUCTOR
74HC74-B
PHILIPS
SEMICONDUCTOR
3
1
14
12
S0
4
2
15
13
10
7
11
9
D1
Y
Y
D2
D0
D3
D4
D5
D6
D7
S1
S2
OE
C3
0.1µF
V
+
VOUT
fCLK
2n
VOUT
QOUT
C1, 0.1µF
C2
0.1µF
912
811
6
5
74HC74-A
PHILIPS SEMICONDUCTOR
13
10
Q
R
PS
CLK
D
Q
1
OUTPUT
PULSE
WIDTH
=
U4
U5
U1
f
CLK
S1
S0
S2
V
+
V
+
+
V
V
+

Products related to this Datasheet

IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8MSOP
IC OSC SILICON PROG 8MSOP
BD DEMO FOR LTC6903 REQ. DC2026
BD DEMO FOR LTC6904 REQ. DC2026
IC OSC SILICON PROG 8-MSOP
IC OSC SILICON PROG 8-MSOP