CAT25320 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2015
June, 2018 Rev. 12
1Publication Order Number:
CAT25320/D
CAT25320
EEPROM Serial 32-Kb SPI
Description
The CAT25320 is a EEPROM Serial 32Kb SPI device internally
organized as 4096x8 bits. This features a 32byte page write buffer
and supports the Serial Peripheral Interface (SPI) protocol. The device
is enabled through a Chip Select (CS) input. In addition, the required
bus signals are clock input (SCK), data input (SI) and data output (SO)
lines. The HOLD input may be used to pause any serial
communication with the CAT25320 device. The device features
software and hardware write protection, including partial as well as
full array protection.
Features
10 MHz SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
32byte Page Write Buffer
Selftimed Write Cycle
Hardware and Software Protection
Block Write Protection
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC, TSSOP 8lead Packages
This Device is PbFree, Halogen Free/BFR Free, and RoHS
Compliant
SI
SO
CAT25320
SCK
VSS
VCC
CS
WP
HOLD
Figure 1. Functional Symbol
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PIN CONFIGURATION
SI
HOLD
VCC
VSS
WP
SO
CS 1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SCK
SOIC (V), TSSOP (Y)
Chip SelectCS
Serial Data OutputSO
Write ProtectWP
GroundVSS
Serial Data InputSI
Serial ClockSCK
FunctionPin Name
PIN FUNCTION
Hold Transmission InputHOLD
Power SupplyVCC
SOIC8
V SUFFIX
CASE 751BD
TSSOP8
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CASE 948AL
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CAT25320
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2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Operating Temperature 45 to +130 °C
Storage Temperature 65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than 0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than 1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = 40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Supply Current
(Read Mode)
Read, VCC = 5.5 V,
SO open
10 MHz / 40°C to 85°C 2 mA
5 MHz / 40°C to 125°C 2 mA
ICCW Supply Current
(Write Mode)
Write, VCC = 5.5 V,
SO open
10 MHz / 40°C to 85°C 2 mA
5 MHz / 40°C to 125°C 3 mA
ISB1 Standby Current VIN = GND or VCC, CS = VCC,
WP = VCC, VCC = 5.5 V
TA = 40°C to +85°C 1 mA
TA = 40°C to +125°C 2 mA
ISB2 Standby Current VIN = GND or VCC, CS = VCC,
WP = GND, VCC = 5.5 V
TA = 40°C to +85°C 3 mA
TA = 40°C to +125°C 5 mA
ILInput Leakage Current VIN = GND or VCC 2 2 mA
ILO Output Leakage
Current
CS = VCC,
VOUT = GND or VCC
TA = 40°C to +85°C1 1 mA
TA = 40°C to +125°C1 2 mA
VIL Input Low Voltage 0.5 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC + 0.5 V
VOL1 Output Low Voltage VCC 2.5 V, IOL = 3.0 mA 0.4 V
VOH1 Output High Voltage VCC 2.5 V, IOH = 1.6 mA VCC 0.8 V V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 150 mA0.2 V
VOH2 Output High Voltage VCC < 2.5 V, IOH = 100 mAVCC 0.2 V V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN CAPACITANCE (Note 2) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol Test Conditions Min Typ Max Units
COUT Output Capacitance (SO) VOUT = 0 V 8 pF
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF
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CAT25320
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Table 5. A.C. CHARACTERISTICS
(TA = 40°C to +85°C (Industrial) and TA = 40°C to +125°C (Extended).) (Notes 4, 7)
Symbol Parameter
VCC = 1.8 V 5.5 V / 405C to +855C
VCC = 2.5 V 5.5 V / 405C to +1255C
VCC = 2.5 V 5.5 V
405C to +855C
Units
Min Max Min Max
fSCK Clock Frequency DC 5 DC 10 MHz
tSU Data Setup Time 40 20 ns
tHData Hold Time 40 20 ns
tWH SCK High Time 75 40 ns
tWL SCK Low Time 75 40 ns
tLZ HOLD to Output Low Z 50 25 ns
tRI (Note 5) Input Rise Time 2 2 ms
tFI (Note 5) Input Fall Time 2 2 ms
tHD HOLD Setup Time 0 0 ns
tCD HOLD Hold Time 10 10 ns
tVOutput Valid from Clock Low 75 40 ns
tHO Output Hold Time 0 0 ns
tDIS Output Disable Time 50 20 ns
tHZ HOLD to Output High Z 100 25 ns
tCS CS High Time 50 20 ns
tCSS CS Setup Time 20 15 ns
tCSH CS Hold Time 30 20 ns
tCNS CS Inactive Setup Time 50 15 ns
tCNH CS Inactive Hold Time 50 15 ns
tWPS WP Setup Time 10 10 ns
tWPH WP Hold Time 100 60 ns
tWC (Note 6) Write Cycle Time 5 5 ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the tCSH is defined relative to the negative clock edge.
Table 6. POWERUP TIMING (Notes 5, 8)
Symbol Parameter Max Units
tPUR Powerup to Read Operation 1 ms
tPUW Powerup to Write Operation 1 ms
8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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CAT25320
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4
Pin Description
SI: The serial data input pin accepts opcodes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25320.
CS: The chip select input pin is used to enable/disable the
CAT25320. When CS is high, the SO output is tristated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress). Every communication
session between host and CAT25320 must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25320, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, the HOLD input should be tied to VCC, either
directly or through a resistor.
Functional Description
The CAT25320 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8bit instruction register. The instruction
set and associated opcodes are listed in Table 7.
Reading data stored in the CAT25320 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25320, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25320 will accept any one of the six instruction
opcodes listed in Table 7 and will ignore all other possible
8bit combinations. The communication protocol follows
the timing from Figure 2.
Table 7. INSTRUCTION SET
Instruction Opcode Operation
WREN 0000 0110 Enable Write Operations
WRDI 0000 0100 Disable Write Operations
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 0011 Read Data from Memory
WRITE 0000 0010 Write Data to Memory
Figure 2. Synchronous Data Timing
CS
SCK
SI
SO
tCNH
tCSS tWH tWL
tSU
tH
HIZ
VALID
IN
VALID
OUT
tCSH
tRI
tFI
tVtV
tHO
tCNS
tCS
HIZ
tDIS
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CAT25320
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5
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are nonvolatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become readonly.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the nonblock protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
Table 8. STATUS REGISTER
7 6 5 4 3 2 1 0
WPEN 0 0 0 BP1 BP0 WEL RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
Array Address Protected Protection
BP1 BP0
0 0 None No Protection
0 1 0C000FFF Quarter Array Protection
1 0 08000FFF Half Array Protection
1 1 00000FFF Full Array Protection
Table 10. WRITE PROTECT CONDITIONS
WPEN WP WEL Protected Blocks Unprotected Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
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CAT25320
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6
WRITE OPERATIONS
The CAT25320 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25320. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
Figure 3. WREN Timing
SCK
SI
SO
00000 110
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
Figure 4. WRDI Timing
SCK
SI
SO
00000 100
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
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CAT25320
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Byte Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16bit address
and data as shown in Figure 5. Only 12 significant address
bits are used by the CAT25320. The rest are don’t care bits,
as shown in Table 11. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
Page Write
After sending the first data byte to the CAT25320, the host
may continue sending data, up to a total of 32 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25320 is
automatically returned to the write disable state.
Table 11. BYTE ADDRESS
Device Address Significant Bits Address Don’t Care Bits # Address Clock Pulses
CAT25320 A11 A0 A15 A12 16
Figure 5. Byte WRITE Timing
SCK
SI
SO
0000 01 0 D7 D6 D5 D4 D3 D2 D1 D0
012345678
OPCODE DATA IN
HIGH IMPEDANCE
BYTE ADDRESS*
21 22 23 24 25 26 27 28 29 30 31
Dashed Line = mode (1, 1)
CS
A0
AN
0
* Please check the Byte Address Table (Table 11)
Figure 6. Page WRITE Timing
SCK
SI
SO
0000 0 10
BYTE ADDRESS*
Data
Byte 1
012345678 212223
2431 3239
Data Byte N
OPCODE
7..1 0
24+(N1)x81 .. 24+(N1)x8
24+Nx81
DATA IN
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
CS
ANA0
Data
Byte 3
Data
Byte 2
0
* Please check the Byte Address Table (Table 11)
CAT25320
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8
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3 and 7 can be written using the WRSR command.
Write Protection
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
Figure 7. WRSR Timing
0123 45678 10911121314
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
7 6 5 4 3 2 10
0000000 1
OPCODE
Dashed Line = mode (1, 1)
CS
Figure 8. WP Timing
SCK
WP
Dashed Line = mode (1, 1)
WP
CS
tWPH
tWPS
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CAT25320
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9
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16bit address (see Table 11 for the number
of significant address bits).
After receiving the last address bit, the CAT25320 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25320 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at any
time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the full content of the status register (New product,
Rev. F) or the RDY (Ready) bit only (i.e., data out = FFh) for
previous product revision C (Mature product). For easy
detection of the internal write cycle completion, both during
writing to the memory array and to the status register, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
Figure 9. READ Timing
SCK
SI
SO
BYTE ADDRESS*
0123456789
76 5 4 3 2 1 0
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
2120 22 23 24 25 26 27 28 29 30
00 00 0 11
Dashed Line = mode (1, 1)
A0
AN
CS
* Please check the Byte Address Table (Table 11)
0
10
Figure 10. RDSR Timing
012345678 10911121314
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO 7 6 54 3 2 1 0
00000 1 01
Dashed Line = mode (1, 1)
CS
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CAT25320
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10
Hold Operation
The HOLD input can be used to pause communication
between host and CAT25320. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tristated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
The CAT25320 device incorporates PowerOn Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after VCC exceeds the POR trigger level
and will power down into Reset mode when VCC drops
below the POR trigger level. This bidirectional POR
behavior protects the device against ‘brownout’ failure
following a temporary loss of power.
The CAT25320 device powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
opcode will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Figure 11. HOLD Timing
SCK
SO HIGH IMPEDANCE
Dashed Line = mode (1, 1)
tLZ
CS
HOLD
tCD
tHD
tHD
tCD
tHZ
ORDERING INFORMATION
Order Number
Device Specific
Marking (Note
NO TAG) Package Type Temperature Range
Lead
Finish Shipping
CAT25320VIGT3 *4C
25320VI
SOIC8I = Industrial
(40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT25320YEGT3 S32 TSSOP8E = Extended
(40°C to +125°C
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT25320YIGT3 S32 TSSOP8I = Industrial
(40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
9. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
SOIC 8, 150 mils
CASE 751BD01
ISSUE O
DATE 19 DEC 2008
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34272E
ON SEMICONDUCTOR STANDARD
SOIC 8, 150 MILS
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
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DOCUMENT NUMBER:
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SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 01O
Case Outline Number:
751BD
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El 9‘5
TSSOP8, 4.4x3
CASE 948AL01
ISSUE O
DATE 19 DEC 2008
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34428E
ON SEMICONDUCTOR STANDARD
TSSOP8, 4.4X3
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
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