CAT24C64 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2018
April, 2018 − Rev. 27 1Publication Order Number:
CAT24C64/D
CAT24C64
64 Kb I2C CMOS Serial
EEPROM
Description
The CAT24C64 is a 64 Kb CMOS Serial EEPROM device,
internally organized as 8192 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C64 devices on the same bus.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC, TSSOP, UDFN 8−pad and Ultra−thin WLCSP 4−bump
Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
Figure 1. Functional Symbol
SDA
SCL
WP
CAT24C64
VCC
VSS
A2, A1, A0
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PIN CONFIGURATIONS (Top Views)
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
SOIC−8
W SUFFIX
CASE 751BD
SOIC (W), TSSOP (Y),
UDFN (HU4)
TSSOP−8
Y SUFFIX
CASE 948AL
Device AddressA0, A1, A2Serial DataSDA
Serial ClockSCL
Write ProtectWP
Power SupplyVCC GroundVSS
FunctionPin Name
PIN FUNCTION
For the location of Pin 1, please consult the
corresponding package drawing.
UDFN−8
HU4 SUFFIX
CASE 517AZ
WLCSP−4
C4C SUFFIX
CASE 567JY
SDA
WP
VCC
VSS
A2
A1
A01
SCL
WLCSP
A1 A2
B1 B2 SD
A
VSS
SCL
VCC
1
X = Specific Device Code
= (see ordering information)
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
W = Production Week Code
X
YW
MARKING
DIAGRAMS
(WLCSP−4)
WLCSP−4
C4U SUFFIX
CASE 567PB
X
YM
(C4C) (C4U)
For serial EEPROM in a US8 package, please
consult the N24C64 datasheet.
CAT24C64
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2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature –65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program/Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 2 mA
ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C
VCC 3.3 V 1mA
TA = −40°C to +85°C
VCC > 3.3 V 3
TA = −40°C to +125°C 5
ILI/O Pin Leakage Pin at GND or VCC 2mA
VIL Input Low Voltage −0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA
VIN < VIH, VCC = 3.3 V 120
VIN < VIH, VCC = 1.8 V 80
VIN > VIH 2
IA (Note 5) Address Input Current
(A0, A1, A2)
Product Rev F
VIN < VIH, VCC = 5.5 V 50 mA
VIN < VIH, VCC = 3.3 V 35
VIN < VIH, VCC = 1.8 V 25
VIN > VIH 2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
CAT24C64
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3
Table 5. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 6)
Symbol Parameter
Standard
VCC = 1.7 V − 5.5 V Fast
VCC = 1.7 V − 5.5 V
Fast−Plus
VCC = 1.7 V − 5.5 V
TA = −405C to +855C
Units
Min Max Min Max Min Max
FSCL Clock Frequency 100 400 1,000 kHz
tHD:STA START Condition Hold Time 4 0.6 0.25 ms
tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms
tHIGH High Period of SCL Clock 4 0.6 0.40 ms
tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms
tHD:DAT Data In Hold Time 000ms
tSU:DAT Data In Setup Time 250 100 50 ns
tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns
tF (Note 7) SDA and SCL Fall Time 300 300 100 ns
tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms
tBUF Bus Free Time Between
STOP and START 4.7 1.3 0.5 ms
tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms
tDH Data Out Hold Time 100 100 50 ns
Ti (Note 7) Noise Pulse Filtered at SCL
and SDA Inputs 100 100 100 ns
tSU:WP WP Setup Time 000ms
tHD:WP WP Hold Time 2.5 2.5 1 ms
tWR Write Cycle Time 5 5 5 ms
tPU (Notes 7, 8) Power−up to Ready Mode 1 1 0.1 1 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
E E
CAT24C64
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4
Power−On Reset (POR)
Each CAT24C64 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard−wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally. The Address inputs are not available for use with
WLCSP 4−bumps.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally. The WP input is not available for the
WLCSP 4−bumps, therefore all write operations are allowed
for the device in this package.
Functional Description
The CAT24C64 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C64
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
I2C Bus Protocol
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAT24C64, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A2, A1 and A0, must match
the logic state of the similarly named input pins. The devices
in WLCSP 4−bumps respond only to the Slave Address with
A2 A1 A0 = 000 (CAT24C64C4xTR). The R/W bit tells the
Slave whether the Master intends to read (1) or write (0) data
(Figure 3).
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
START
CONDITION STOP
CONDITION
SDA
SCL
Figure 2. Start/Stop Timing
Figure 3. Slave Address Bits
1010
DEVICE ADDRESS*
A2A1A0R/W
* The devices in WLCSP 4−bumps respond only to the Slave Address with: A2 A1 A0 = 000, CAT24C64C4xTR
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CAT24C64
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5
Figure 4. Acknowledge Timing
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP ( tSU:DAT)
ACK DELAY ( tAA)
Figure 5. Bus Timing
SCL
SDA IN
SDA OUT
tBUF
tSU:STO
tSU:DAT
tR
tAA tDH
tLOW
tHIGH
tLOW
tSU:STA tHD:STA
tHD:DAT
tF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24C64 is shipped erased, i.e., all bytes are FFh.
J \_:E_3J U M \_3§E§§-'_/ \_ |:|_|_|_||ll\‘|llllll x x33333x X: _I_ IX www.cns
CAT24C64
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6
SLAVE
ADDRESS
S
A
***
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
BYTE DATA
BYTE
Figure 6. Byte Write Sequence
*a15 − a13 are don’t care bits.
a15 − a8a7 − a0d7 − d0
Figure 7. Write Cycle Timing
STOP
CONDITION START
CONDITION ADDRESS
ACK8th Bit
Byte n
SCL
SDA
tWR
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
P
A
C
K
BUS
ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
Figure 8. Page Write Sequence
Figure 9. WP Timing
189
18
ADDRESS
BYTE DATA
BYTE
SCL
SDA
WP
tSU:WP
tHD:WP
a7a0d7d0
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CAT24C64
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7
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
Figure 10. Immediate Read Sequence and Timing
SCL
SDA 8th Bit
STOP
NO ACKDATA OUT
89
SLAVE
ADDRESS
S
A
C
KDATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 11. Selective Read Sequence
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
A
R
T
SLAVE
S
A
C
K
S
T
A
R
T
P
S
T
O
P
ADDRESS
BYTE ADDRESS
BYTE ADDRESS
N
O
A
C
K
DATA
BYTE
BUS ACTIVITY:
MASTER
SLAVE
Figure 12. Sequential Read Sequence
S
T
O
P
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
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CAT24C64
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking Package Type Temperature Range Lead Finish Shipping
CAT24C64WI−GT3 24C64F SOIC−8, JEDEC I = Industrial
(−40°C to +85°C) NiPdAu Tape & Reel,
3,000 Units / Reel
CAT24C64YI−GT3 C64F TSSOP−8 I = Industrial
(−40°C to +85°C) NiPdAu Tape & Reel,
3,000 Units / Reel
CAT24C64HU4I−GT3 C6U UDFN−8 I = Industrial
(−40°C to +85°C) NiPdAu Tape & Reel,
3,000 Units / Reel
CAT24C64C4CTR AWLCSP−4
with Die Coat Industrial
(−40°C to +85°C) N/A Tape & Reel,
5,000 Units / Reel
CAT24C64C4UTR AWLCSP−4
with Die Coat Industrial
(−40°C to +85°C) N/A Tape & Reel,
5,000 Units / Reel
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10.The standard lead finish is NiPdAu.
11. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
12.Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultra violet light. When exposed to ultra violet light
the EEPROM cells lose their stored data.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
www.onsemi.com
8
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
DATE 23 MAR 2015
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.08 A1 SEATING
PLANE
NOTE 3
b
8X
0.10 C
0.05 C
AB
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
b0.20 0.30
D2.00 BSC
D2 1.35 1.45
E3.00 BSC
E2 1.25 1.35
e0.50 BSC
L0.25 0.35
14
8
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.45 3.40
1
DIMENSIONS: MILLIMETERS
1
NOTE 4
0.30
8X
DETAIL A
A3 0.13 REF
A3
A
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
L1 −−− 0.15
e
RECOMMENDED
5
1.56
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
XXXXX
AWLYWG
1
M
M
0.68
C0.10
8X
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
UDFN8, 2X3 EXTENDED PAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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WLCSP4, 0.77x0.77
CASE 567JY
ISSUE C
DATE 07 MAR 2017
SEATING
PLANE
E
D
AB
PIN A1
REFERENCE
e
A0.05 BC
0.03 C
0.05 C
4X b
12
B
A
0.05 C
A
A1
A2
C
SCALE 4:1
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 4
e
PITCH 0.16
4X
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.40
0.40
RECOMMENDED
1PACKAGE
OUTLINE
PITCH
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF
THE SOLDER BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM
CONTACT BALL DIAMETER PARALLEL TO DATUM C.
6. BACKSIDE COATING IS OPTIONAL.
DIM
A
MIN NOM
−−−
MILLIMETERS
A1
D
E
b0.15 0.155
e0.40 BSC
−−−
0.04 0.06
A2 0.23 REF
A3 0.025 REF
0.75 0.77
0.75 0.77
MAX
0.16
0.35
0.08
0.79
0.79
A2
DETAIL A
NOTE 6
DIE COAT
(OPTIONAL)
A3
X = Specific Device Code
Y = Year
W = Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
X
YW
NOTE 5
NOTE 3
A
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON85186F
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
WLCSP4, 0.77X0.77
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" -A.1 PLANE o BOTTOM VIEW L ‘ 63*"69 ,,+ +,, L‘jw ON Semxcunduclar vesewes we th| to make changes wuhum Yunhev name to any pruduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy ansmg mac xna apphcahan m use no any pmduclnv mum and saaamcauy dwsc‘axms any and au Mammy mc‘udmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Semxmnduclar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
WLCSP4, 0.77x0.77
CASE 567PB
ISSUE A
DATE 09 NOV 2016
SEATING
PLANE
E
D
AB
PIN A1
REFERENCE
e
A0.05 BC
0.03 C
0.05 C
4X b
12
B
A
0.05 C
A
A1
A2
C
SCALE 4:1
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 4
e
PITCH 0.16
4X
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.40
0.40
RECOMMENDED
1PACKAGE
OUTLINE
PITCH
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DATUM C, THE SEATING PLANE, IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
4. COPLANARITY APPLIES TO SPHERICAL CROWNS OF
THE SOLDER BALLS.
5. DIMENSION b IS MEASURED AT THE MAXIMUM
CONTACT BALL DIAMETER PARALLEL TO DATUM C.
6. BACKSIDE COATING IS OPTIONAL.
DIM
A
MIN NOM
−−−
MILLIMETERS
A1
D
E
b0.15 0.155
e0.40 BSC
−−−
0.04 0.055
A2 0.19 REF
A3 0.025 REF
0.75 0.77
0.75 0.77
MAX
0.16
0.30
0.07
0.79
0.79
A2
DETAIL A
NOTE 6
DIE COAT
(OPTIONAL)
A3
X = Specific Device Code
Y = Year
W = Work Week
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
X
YW
NOTE 5
NOTE 3
A
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON12765G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
WLCSP4, 0.77X0.77
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" ON Semxcunduchv and are Mademavk: av Semmanduclur Campunenls Inuwnaa LLC dba ON Samanauaxar Dr H: suaamanas m xna Umled sxaxaa andJm mhev comma: ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
SOIC 8, 150 mils
CASE 751BD01
ISSUE O
DATE 19 DEC 2008
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON34272E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SOIC 8, 150 MILS
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" :Fa | i? :L ON Semxcunduchv and are Mademavk: av Semmanduclur Campunenls Inuwnaa LLC dba ON Samanauaxar Dr H: suaamanas m xna Umled sxaxaa andJm mhev comma: ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
TSSOP8, 4.4x3
CASE 948AL01
ISSUE O
DATE 19 DEC 2008
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON34428E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP8, 4.4X3
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
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