ATF16V8B,BQ,BQL Datasheet by Microchip Technology

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Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
Features
Industry-standard Architecture
̶Emulates Many 20-pin PALs®
̶Low-cost Easy-to-use Software Tools
High-speed Electrically-erasable Programmable Logic Devices
̶10ns Maximum Pin-to-pin Delay
Automatic 5mA Standby for ATF16V8BQL
CMOS and TTL Compatible Inputs and Outputs
̶Input and I/O Pull-up Resistors
Advanced Flash Technology
̶Reprogrammable
̶100% Tested
High-reliability CMOS Process
̶20 Year Data Retention
̶100 Erase/Write Cycles
̶2,000V ESD Protection
̶200mA Latchup Immunity
Industrial Temperature Range
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-compliant
Green Package Options (Pb/Halide-free/RoHS Compliant)
Description
The Atmel® ATF16V8B(QL) is a high-performance CMOS Electrically-Erasable
Programmable Logic Device (EE PLD) that utilizes the Atmel proven
electrically-erasable Flash memory technology. All speed ranges are specified
over the full 5.0V 10% range for industrial temperature range.
The ATF16V8BQL provides edge-sensing low-power PLD solution with low
standby power consumption (5mA typical). The ATF16V8BQL powers down
automatically to the low-power mode through the Input Transition Detection (ITD)
circuitry when the device is idle.
The ATF16V8B(QL) incorporate a super set of the generic architectures, which
allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs.
Eight outputs are each allocated eight product terms. Three different modes of
operation, configured automatically with software, allow highly complex logic
functions to be realized.
ATF16V8B, ATF16V8BQ*, and ATF16V8BQL
High-performance EE PLD
DATASHEET
*The ATF16V8BQ is
Replaced by ATF16V8B
and ATF16V8BQL
IEEIIIIIII IIEIIIIIII
ATF196V8B(Q)(QL) [DATASHEET]
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1. Pin Configurations and Pinouts
Table 1-1. Pin Configurations
Figure 1-1. Pinouts
Pin Name Function
CLK Clock
GND Ground
I Logic Inputs
I/O Bi-directional Buffers
OE Output Enable
VCC +5V Power Supply
20-lead SOIC
(Top View)
1
2
3
4
5
6
7
8
9
10
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
20
19
18
17
16
15
14
13
12
11
20-lead TSSOP
(Top View)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
20-lead PDIP
(Top View)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
20-lead PLCC
(Top View)
I3
I4
I5
I6
I7
4
5
6
7
8
18
17
16
15
14
I8
GND
I9/OE
I/O
I/O
I2
I1
I/CLK
VCC
I/O
3
2
1
20
19
9
10
11
12
13
I/O
I/O
I/O
I/O
I/O
Note: Drawings are not to scale.
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2. Block Diagram
Figure 2-1. Block Diagram
10 Input Pins
Programmable
Interconnect
and
Combinatorial
Logic Array
Logic
Option
Up to
8 Flip-Flops
8 I/O Pins
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3. Electrical Characteristics
3.1 Absolute Maximum Ratings*
Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output
pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20ns.
3.2 Pin Capacitance
Table 3-1. Pin Capacitance (f = 1MHz, T = 25°C(1))
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
3.3 DC and AC Operating Conditions
Table 3-2. DC and AC Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1)
Voltage on Input Pins with Respect to
Ground During Programming . . . . . . . . . . . . . -2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
*Notice: Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is
a stress rating only and functional
operation of the device at these or any
other conditions beyond those indicated
in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device
reliability.
Typ Max Units Conditions
CIN 5 8 pF VIN = 0V
COUT 6 8 pF VOUT = 0V
Industrial
Operating Temperature (Ambient) -40oC to +85oC
VCC Power Supply 5.0V 10%
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3.4 DC Characteristics
Table 3-3. DC Characteristics
Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30s.
Symbol Parameter Condition Min Typ Max Units
IIL
Input or I/O Low
Leakage Current 0 VIN VIL(Max) -35 -100 μA
IIH
Input or I/O High
Leakage Current 3.5 VIN VCC 10 μA
ICC
Power Supply
Current, Standby
VCC = Max
VIN = Max, Outputs Open
B-10 55 95
mAB-15 50 80
BQL-15 5 15
ICC2
Clocked Power
Supply Current
VCC = Max, Outputs Open
f = 15MHz
B-10 60 100
mAB-15 55 95
BQL-15 20 40
IOS(1) Output Short
Circuit Current VOUT = 0.5 V -130 mA
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 VCC + 0.75 V
VOL Output High Voltage VIN = VIH or VIL
VCC = Min IOL = 24mA 0.5 V
VOH Output High Voltage VIN = VIH or VIL
VCC = Min IOH = -4.0 mA 2.4 V
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3.5 AC Characteristics
Table 3-4. AC Characteristics(1)
Note: 1. See ordering information for valid part numbers and speed grades.
Figure 3-1. AC Waveforms(3.6)
Symbol Parameter
-10 -15
UnitsMin Max Min Max
tPD
Input or Feedback to
Non-Registered Output 8 outputs switching 3 10 3 15 ns
tCF Clock to Feedback 6 8 ns
tCO Clock to Output 2 7 2 10 ns
tSInput or Feedback Setup Time 7.5 12 ns
tHHold Time 0 0 ns
tPClock Period 12 16 ns
tWClock Width 6 8 ns
fMAX
External Feedback 1/(tS + tCO) 68 45
MHzInternal Feedback 1/(tS + tCF) 74 50
No Feedback 1/(tP) 83 62
tEA Input to Output Enable — Product Term 3 10 3 15 ns
tER Input to Output Disable — Product Term 2 10 2 15 ns
tPZX OE pin to Output Enable 2 10 2 15 ns
tPXZ OE pin to Output Disable 1.5 10 1.5 15 ns
Inputs, I/O
Reg. Feedback
CLK
Registered
Outputs
Combinatorial
Outputs
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
tStH
tW
tW
tP
tCO
tPD
tER, tPXZ tEA, tPZX
tER, tPXZ
HIGH Z
HIGH Z
tEA, tPZX
Note 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.
<>C 5.0V R1 = 200 OUTPUT PIN R2=390 $CL=50pF AtmeL
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3.6 Input Test Waveforms
3.6.1 Input Test Waveforms and Measurement Levels
Figure 3-2. Input Test Waveforms and Measurement Levels
3.6.2 Output Test Loads (Commercial)
Figure 3-3. Output Test Loads
CL includes Test fixture and Probe capacitance
3.7 Power-up Reset
The registers in the ATF16V8B(QL) are designed to reset during power-up. At a point delayed slightly from VCC
crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be
high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and
3. The clock must remain stable during tPR.
Figure 3-4. Power-up Reset Waveforms
AC
Driving
Levels
AC
Measurement
Level
3.0V
0.0V
1.5V
tR, tF < 5ns (10% to 90%)
Power
Registered
Outputs
Clock
VRST
tPR
tS
tW
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Table 3-5. Power-up Reset Parameters
3.8 Preload of Registered Outputs
The ATF16V8B(QL) device registers are provided with circuitry to allow loading of each register with either a
high or a low. This feature will simplify testing since any state can be forced into the registers to control test
sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once
downloaded, the JEDEC file preload sequence will be done automatically by most of the approved
programmers after the programming.
4. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8B(QL) fuse patterns. Once
programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
5. Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
6. Programming/Erasing
Programming/erasing is performed using standard PLD programmers.
7. Input and I/O Pull-ups
All ATF16V8B(QL) family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or
I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known
states. These are relatively weak active pull-ups that can easily be over driven by TTL-compatible drivers (see
input and I/O diagrams below).
Figure 7-1. Input Diagram
Parameter Description Typ Max Units
tPR Power-up Reset Time 600 1,000 ns
VRST Power-up Reset Voltage 3.8 4.5 V
Input
ESD
Protection
Circuit
V
CC
V
CC
R > 50KΩ
AAAAA
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Figure 7-2. I/O Diagram
8. Functional Logic Diagram Description
The logic option and functional diagrams describe the ATF16V8B(QL) architecture. Eight configurable
macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.
The ATF16V8B(QL) can be configured in one of three different modes. Each mode makes the ATF16V8B(QL)
look like a different device. Most PLD compilers can choose the right mode automatically. The user can also
force the selection by supplying the compiler with a mode selection. The determining factors would be the usage
of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF16V8B(QL) universal architecture can be programmed to emulate many 20-pin PAL devices. These
architectural subsets can be found in each of the configuration modes described in the following pages. The
user can download the listed subset device JEDEC programming file to the PLD programmer, and the
ATF16V8B(QL) can be configured to act like the chosen device. Check with your programmer manufacturer for
this capability.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the content of the ATF16V8B(QL). Eight bytes (64 fuses) of User Signature
are accessible to the user for purposes such as storing project name, part number, revision, or date. The User
Signature is accessible regardless of the state of the security fuse.
9. Software Support
Atmel WinCUPL is a free tool, available on Atmel’s web site and can be used to design in all members of the
ATF16V8B(QL) family of SPLDs. The below table lists the Atmel WinCUPL device mnemonics for the different
macrocell configuration modes.
Table 9-1. Compiler Mode Selection
OE
Data
VCC VCC
I/O
Feedback
R > 50KΩ
Registered Complex Simple Auto Select
CUPL, Atmel WinCUPL G16V8MS G16V8MA G16V8AS G16V8
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10. Macrocell Configuration
Software compilers support the three different OMC modes as different device types. Most compilers have the
ability to automatically select the device type, generally based on the register usage and Output Enable (OE)
usage. Register usage on the device forces the software to choose the registered mode. All combinatorial
outputs with OE controlled by the product term will force the software to choose the complex mode. The
software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The
different device types can be used to override the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user must pay special attention to the following
restrictions in each mode:
Registered Mode
Pin 1 and pin 11 are permanently configured as clock and output enable respectively. These pins cannot
be configured as dedicated inputs in the registered mode.
Complex Mode
Pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively.
Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode.
Simple Mode
All feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins
(pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated
combinatorial output.
10.1 ATF16V8B(QL) Registered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more registers are required.
Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a
registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight
product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by
a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an
input, the output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices can be emulated
using this mode:
16R8
16R6
16R4
16RP8
16RP6
16RP4
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Figure 10-1. Registered Configuration for Registered Mode(1)(2)
Notes: 1. Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the registered
outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage
automatically.
Figure 10-2. Combinatorial Configuration for Registered Mode(1)(2)
Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage
automatically.
CLK
OE
XOR
DQ
Q
XOR
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Figure 10-3. Registered Mode Logic Diagram
CLK
Input Lines
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
0 4 8 1216202428
1
2
3
4
5
6
7
8
9
18
19
17
16
15
14
13
12
11
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10.2 ATF16V8B(QL) Complex Mode
PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O functions are
possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the
AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term
and one product term enabling the output.
Combinatorial applications with an OE requirement will make the compiler select this mode. The following
devices can be emulated using this mode:
Figure 10-4. Complex Mode Option
16L8
16H8
16P8
0
1
7
XOR
Pins 12 and 19 do not have this feedback path.
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Figure 10-5. Complex Mode Logic Diagram
Input Lines
0 4 8 12 16 20 24 28
1
2
3
4
5
6
7
8
9
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
18
19
17
16
15
14
13
12
11
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10.3 ATF16V8B(QL) Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term.
Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can
be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple
PALs can be emulated using this mode:
Figure 10-6. Simple Mode Option
10L8
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
0
1
0
7
XOR
Pins 15 and 16 do not have this feedback path.
* Pins 15 and 16 are always enabled.
VCC
S1*
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Figure 10-7. Simple Mode Logic Diagram
Input Lines
0 4 8 12 16 20 24 28
1
2
3
4
5
6
7
8
9
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
Output
Logic
18
19
17
16
15
14
13
12
11
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11. Test Characterization Data
Supply Current vs Input Frequency
0
25
50
75
I
CC
(mA)
0 25 50 75 100
Frequency (MHz)
ATF16V8B
ATF16V8BQ
ATF16V8B/BQ (V
CC
= 5V, T
A
= 25°C)
Supply Current vs Input Frequency
I
CC
(mA)
Frequency (MHz)
ATF16V8BL/BQL (V
CC
= 5V, T
A
= 25°C)
0
25
50
75
0 20406080100
ATF16V8B
ATF16V8BQL
25
35
45
55
65
4.50 4.75 5.00 5.25 5.50
ATF16V8B
ATF16V8BQ
Supply Current vs Supply Voltage
I
CC
(mA)
Supply Voltage (V)
ATF16V8B/BQ (T
A
= 25°C)
4.0
4.5
5.0
5.5
6.0
4.50 4.75 5.00 5.25 5.50
Supply Current vs Supply Voltage
I
CC
(mA)
Supply Voltage (V)
ATF16V8BL/BQL (T
A
= 25°C)
30
40
50
60
70
-55 -10 35 80 125
Supply Current vs Ambient Temperature
I
CC
(mA)
Ambient Temperature (C)
ATF16V8B/BQ (V
CC
= 5.0V)
ATF16V8B
ATF16V8BQ
4.0
4.4
4.8
5.2
5.6
-55 -10 35 80 125
Supply Current vs Ambient Temperature
I
CC
(mA)
Ambient Temperature (C)
ATF16V8BL/BQL (V
CC
= 5.0V)
-24
-22
-20
-18
-16
-14
-12
-10
4.5 4.7 4.9 5.1 5.3 5.5
Output Source Current vs Supply Current
I
OH
(mA)
Supply Voltage (V)
T
A
= 25°C
Output Sink Current vs Supply Current
I
OL
(mA)
Supply Voltage (V)
T
A
= 25°C
34.5
34.0
33.5
33.0
32.5
32.0
4.50 4.75 5.00 5.25 5.50
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Output Source Current vs Outpute Voltage
I
OH
(mA)
Output Voltage (V)
(V
CC
= 5.0V, T
A
= 25°C)
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
3.5 3.8 4.1 4.4 4.7 5.0
Output Sink Current vs Output Voltage
I
OL
(mA)
Output Voltage (V)
(V
CC
= 5.0V, T
A
= 25°C)
70
60
50
40
30
20
10
0
0.0 0.2 0.4 0.6 0.8 1.0
Output Source Current vs Output Voltage
I
OH
(mA)
Output Voltage (V)
(V
CC
= 5.0V, T
A
= 25°C)
0
-10
-20
-30
-40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Sink Current vs Output Voltage
I
OL
(mA)
Output Voltage (V)
(V
CC
= 5.0V, T
A
= 25°C)
140
120
100
80
60
40
20
0
0 1 2 3 4 5
Normalized TPD vs Supply Voltage
Supply Voltage (V)
(T
A
= 25°C)
1.30
1.15
1.00
0.85
0.70
4.50 4.75 5.00 5.25 5.50
ATF16VB/BQ
ATF16VB/BQL
Normalized TPD
Normalized TPD vs Ambient Temperature
Normalized TPD
Ambient Temperature (C)
(V
CC
= 5.0V)
1.30
1.15
1.00
0.85
0.70
-55 -25 5 35 65 95 125
Normalized TCO vs Supply Voltage
Normalized TCO
Supply Voltage (V)
(T
A
= 25°C)
1.30
1.15
1.00
0.85
0.70
4.50 4.75 5.00 5.25 5.50
ATF16V8B/BQ
ATF16V8B/BQL
Normalized TCO vs Ambient Temperature
Normalized TCO
Ambient Temperature (C)
(V
CC
= 5.0V)
1.30
1.15
1.00
0.85
0.70
-55 -10 35 80 125
AtmeL
19
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
Normalized TS vs Supply Voltage
Normalized TS
Supply Voltage (V)
(T
A
= 25°C)
1.30
1.15
1.00
0.85
0.70
-55 -10 35 80 125
Normalized TS vs Ambient Temperature
Normalized TS
Ambient Temperature (C)
(V
CC
= 5.0V)
1.30
1.15
1.00
0.85
0.70
-55 -10 35 80 125
Delta TPD vs Output Loading
Delta TPD (ns)
Output Loading (pF)
(V
CC
= 5.0V, T
A
= 25°C)
6
4
2
0
-2
0 50 100 150 200 250 300
Delta TCO vs Output Loading
Delta TCO (ns)
Output Loading (pF)
(V
CC
= 5V, T
A
= 25°C)
6
4
2
0
-2
0 50 100 150 200 250 300
Delta TPD vs # Output Switching
Delta TPD (ns)
# of Output Switching
(V
CC
= 5.0V, T
A
= 25°C)
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
1 2 3 4 5 6 7 8
Delta TCO vs # Output Switching
Delta TCO (ns)
# of Output Switching
(V
CC
= 5.0V, T
A
= 25°C)
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
1 2 3 4 5 6 7 8
Input Current vs Input Voltage
Input Current μA
Input Voltage (V)
(V
CC
= 5.0V, T
A
= 25°C)
40
20
0
-20
-40
1 2 3 4 5 6 7 8
Input Clamp Current vs Input Voltage
Input Current mA
Input Voltage (V)
(V
CC
= 5.0V, T
A
= 25°C)
20
0
-20
-40
-60
-80
-1.0 -0.8 -0.6 -0.4 -0.2 0.0
AtmeL
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
20
12. Ordering Information
tPD
(ns)
tS
(ns)
tCO
(ns) Ordering Code Package Operation Range
10 7.5 7 ATF16V8B-10JU 20J
Industrial
(Pb/Halide-free/RoHS Compliant)
(-40C to +85C)
15 12 10
ATF16V8B-15SU 20S2
ATF16V8B-15XU 20X
ATF16V8B-15PU 20P3
ATF16V8B-15JU 20J
15 12 10
ATF16V8BQL-15SU 20S2
Industrial
(Pb/Halide-free/RoHS Compliant)
(-40C to +85C)
ATF16V8BQL-15XU 20X
ATF16V8BQL-15PU 20P3
ATF16V8BQL-15JU 20J
Package Type
20S2 20-lead, 0.300" wide, Plastic Gull-wing Small Outline (SOIC)
20X 20-lead, 4.4mm wide, Plastic Thin Shrink Small Outline (TSSOP)
20P3 20-lead, 0.300" wide, Plastic Dual Inline Package (PDIP)
20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)
HHHHHHHHH= TOP V‘EW SIDE VIEW END VIEW SYMBOL MIN NOM MAX E AtmeL AtmeL
21
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
13. Packaging Information
13.1 20S2 — 20-lead SOIC
DRAWING NO. REV. TITLE GPC
20S2, 20-lead, 0.300” Wide Body, Plastic
Gull Wing Small Outline Package (SOIC) 20S2 E
7/1/14
SRJ
Package Drawing Contact:
packagedrawings@atmel.com
1. This drawing is for general information only. Refer to JEDEC Drawing
MS-013, Variation AC, for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold flash, protrusions or gate burrs. Mold
flash, protrustions or gate burrs shall not exceed 0.15 mm per end.
Diminsion E1 does not include interlead flash or protursion. Interlead flash
or protrusion shall not exceed 0.25 mm per side.
3. The package top may be smaller than the package bottom. Dimensions D
and E1 are determinded at the outermost extremes of the plastic body
exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. The dimensions apply to the flat section of the lead between 0.10 to
0.25 mm from the lead tip.
5. Dimension ‘b’ does not include the dambar protrusion. Allowable dambar
protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum
material condition. The dambar may not be located on the lower radius of
the foot.
6. ‘A1’ is defined as the vertical distance from the seating plane to the lowest
point on the package body excluding the lid or thermal enhancement on the
cavity down package configuration.
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 12.80 BSC 2,3
E1 7.50 BSC 2,3
E 10.30 BSC
A - - 2.65
A1 0.10 - 0.30 6
A2 2.05 - -
e 1.27 BSC
b 0.31 - 0.51 4,5
L 0.40 - 1.27
C 0.20 - 0.33 4
D
A
e
1
20
b
E1 E
END VIEW
TOP VIEW
SIDE VIEW
E1
A1
A2
C
11
10
L
AtmeL AtmeL
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
22
13.2 20X — 20-lead TSSOP
DRAWING NO. REV. TITLE GPC
20X D
TLN
Package Drawing Contact:
packagedrawings@atmel.com
09/26/11
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 6.40 6.50 6.60 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A1.20
A2 0.80 1.00 1.05
b 0.19 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional
information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
L1
A
L
DA2
EE1
e
b
Top Vi ew
Side View
End View
0º~ 8º
20X, 20-lead 4.4 x 6.5 mm Body, 0.65 mm
Lead Pitch, Thin Shrink Small Outline Package
(TSSOP)
Lead Detail AtmeL AtmeL
23
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
13.3 20P3 — 20-lead PDIP
DRAWING NO. REV.
GPC
TITLE
20P3 F
1/6/12
PQD
20P3, 20-lead, 0.300”/7.62 mm Wide Plastic Dual
Inline Package (PDIP)
COMMON DIMENSIONS
(UNIT OF MEASURE=MM)
Symbol Min. Nom. Max. Note
A - - 5.334
A1 0.381 - -
A2 2.921 3.302 4.953
b 0.356 0.457 0.588
b2 1.143 1.524 1.778
c 0.203 0.254 0.356
D 24.892 26.162 26.924 Note 2
E 7.620 7.874 8.255
E1 6.096 6.350 7.112 Note 2
L 2.921 3.302 3.810
e 2.54 BSC
eA 7.62 BSC
eB - - 10.922
eC 0.000 - 1.524
Notes:
1. This package conforms to JEDEC reference MS-001,
Variation AD.
2. Dimensions D and E1 do not include mold Flash or
Protrusion. Mold Flash or Protrusion shall not exceed
0.25 mm (0.010").
BASE PLANE
SEATING PLANE
A1
A
L
b
b2
DE
c
A2
e
110
20
-C-
eB
eA
See
Lead Detail
eC
GAGE
PLANE
.015
ZZ
Lead Detail
L
C
E1
j
0.10
m
C
11
Package Drawing Contact:
packagedrawings@atmel.com
AtmeL
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
24
13.4 20J — 20-lead PLCC
TITLE DRAWING NO. REV.
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102mm) maximum
A 4.191 4.572
A1 2.286 3.048
A2 0.508
D 9.779 10.033
D1 8.890 9.042 Note 2
E 9.779 10.033
E1 8.890 9.042 Note 2
D2/E2 7.366 8.382
B 0.660 0.813
B1 0.330 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1
D2/E2
B
e
E1 E
D1
D
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B
20J
10/04/01
Package Drawing Contact:
packagedrawings@atmel.com
AtmeL
25
ATF196V8B(Q)(QL) [DATASHEET]
Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014
14. Revision History
Doc. Rev. Date Comments
0364K 07/2014
Removed ATF16V8BQ device and commercial options due to becoming obsolete.
Updated package drawings to most current versions and the 20S to 20S2 package
drawing.
Updated template, Atmel logos, disclaimer page.
0364J 07/2005 Green Package options added in 2005.
1999 ATF16V8B-25 JC/PC/SC/XC/JI/PI/SI/XI and ATF16V8BQL-25 JC/PC/SC/XC/JI/PI/SI/XI
were obsoleted in August 1999 and removed from the datasheet.
Atmet ‘ Enablmg Unlimited Possibilities" ”amfiw
X
XXX
XX
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© 2014 Atmel Corporation. / Rev.: Atmel-0364K-PLD-ATF16V8B-8BQ-8BQL-Datasheet_072014.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. Other terms and product names may be trademarks of others.
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is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
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BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
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