ESD8011 Datasheet by ON Semiconductor

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ESD801 1 5/20 us @ TA = 2560 Slorage Temperature Range Ts.g ,55 to +150 6:: Lead Solder Tempelalure , TL 260 6:: Maximum 11 in Seconds) IEC 610007472 Conlaei (ESD) ESD :20 kV IEC 610007472 All (ESDl ESD :20 kV Maximum Peak Pulse Cunem lpp 3.5 A 5/20 us @ TA = 2560 Maximum Peak Pulse Power Ppk 34 w Slresses exceeding lhose lisled in lhe Maximum Ralings lable may damage lhe device. ll any ol lhese limils aie exceeded deyiee lunclionalily snould nol be assumed damage may occul and reliability may be alleeled. See Applicalion Note AND8308/D for further description of survivability specs. m semaanuusiai Campunenls inausines. LLC am May, 2015 — Rev. 4 www.0nsemi.com Pu 0N Semiconductorg [C
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 4 1Publication Order Number:
ESD8011/D
ESD8011
ESD Protection Diodes
Ultra Low Capacitance ESD Protection
Diode for High Speed Data Line
The ESD8011 ESD protection diodes are designed to protect high
speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
Features
Ultra Low Capacitance (0.10 pF Typ, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
USB 3.x
MHL 2.0
SATA/SAS
PCI Express
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ55 to +125 °C
Storage Temperature Range Tstg 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds) TL260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD) ESD
ESD
±20
±20 kV
kV
Maximum Peak Pulse Current
8/20 ms @ TA = 25°CIpp 3.6 A
Maximum Peak Pulse Power
8/20 ms @ TA = 25°CPpk 34 W
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
X3DFN2
CASE 152AF
PIN CONFIGURATION
AND SCHEMATIC
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R = Specific Device Code
(Rotated 90° clockwise)
M = Date Code
=
12
PIN 1
M
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
R
ESD8011
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2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
VRWM Working Peak Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
VHOLD Holding Reverse Voltage
IHOLD Holding Reverse Current
RDYN Dynamic Resistance
IPP Maximum Peak Pulse Current
VCClamping Voltage @ IPP
VC = VHOLD + (IPP * RDYN)
I
V
VCVRWMVHOLD
VBR
RDYN
VC
IR
IT
IHOLD
−IPP
RDYN
IPP
VC = VHOLD + (IPP * RDYN)
VRWM
VHOLD
IR
IT
IHOLD
VBR
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND 5.5 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 6.5 7.3 V
Reverse Leakage Current IRVRWM = 5.5 V, I/O Pin to GND 1.0 mA
Reverse Holding Voltage VHOLD I/O Pin to GND 2.05 V
Holding Reverse Current IHOLD I/O Pin to GND 17 mA
Clamping Voltage
TLP (Note 2) VCIPP = 8 A IEC61000−4−2 Level 2 Equivalent
(±4 kV Contact, ±8 kV Air) 11.0 V
IPP = 16 A IEC61000−4−2 Level 2 Equivalent
(±8 kV Contact, ±16 kV Air)
19.0
Dynamic Resistance RDYN Pin1 to Pin2
Pin2 to Pin1 1.0
1.0 W
Junction Capacitance CJVR = 0 V, f = 1 MHz 0.10 0.20 pF
Series Inductance LSVR = 0 V 0.3 nH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figure 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
ESD8011
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TYPICAL CHARACTERISTICS
FREQUENCY (Hz)
1E101E91E81E7
−14
−12
−10
−8
−4
−2
0
2
(dB)
−6
3E10
m1 m2
Interface
Data Rate
(Gb/s) Fundamental Frequency
(GHz) 3rd Harmonic Frequency
(GHz) ESD8011 Insertion Loss (dB)
USB 3.0 52.5 (m1) 7.5 (m2) m1 = 0.087
m2 = 0.256
Figure 1. ESD8011 Insertion Loss
ESD8011
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4
TYPICAL CHARACTERISTICS
Figure 2. Positive TLP I−V Curve Figure 3. Negative TLP I−V Curve
VC, VOLTAGE (V)
201814128420
0
2
6
8
10
14
18
20
TLP CURRENT (A)
4
12
16
610 16 2224
0
2
10
4
6
8
VIEC, EQUIVALENT (kV)
VC, VOLTAGE (V)
201814128420
0
−2
−6
−8
−10
−14
−18
−20
TLP CURRENT (A)
−4
−12
−16
610 16 2224
0
2
10
4
6
8
VIEC, EQUIVALENT (kV)
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ESD8011
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5
Latch−Up Considerations
ON Semiconductors 8000 series of ESD protection
devices utilize a snap−back, SCR type structure. By using
this technology, the potential for a latch−up condition was
taken into account by performing load line analyses of
common high speed serial interfaces. Example load lines for
latch−up free applications and applications with the
potential for latch−up are shown below with a generic IV
characteristic of a snapback, SCR type structured device
overlaid on each. In the latch−up free load line case, the IV
characteristic of the snapback protection device intersects
the load−line in one unique point (VOP, IOP). This is the only
stable operating point of the circuit and the system is
therefore latch−up free. In the non−latch up free load line
case, the IV characteristic of the snapback protection device
intersects the load−line in two points (VOPA, IOPA) and
(VOPB, IOPB). Therefore in this case, the potential for
latch−up exists if the system settles at (VOPB, IOPB) after a
transient. Because of this, ESD8011 should not be used for
HDMI applications − ESD8104 or ESD8040 have been
designed to be acceptable for HDMI applications without
latch−up. Please refer to Application Note AND9116/D for
a more in−depth explanation of latch−up considerations
using ESD8000 series devices.
I
I
VV
ESD8011 Latch−up free:
USB 2.0 LS/FS, USB 2.0 HS, USB 3.0 SS,
DisplayPort
VOP VDD
ISSMAX
IOP
ESD8011 Potential Latch−up:
HDMI 1.4/1.3a TMDS
VOPB VOPA VDD
ISSMAX
IOPB
IOPA
Figure 4. Example Load Lines for Latch−up Free Applications and Applications with the Potential for Latch−up
Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH−UP FREE APPLICATIONS
Application
VBR (min) IH (min) VH (min) ON Semiconductor ESD8000 Series
(V) (mA) (V) Recommended PN
HDMI 1.4/1.3a TMDS 3.465 54.78 1.0 ESD8104, ESD8040
USB 2.0 LS/FS 3.301 1.76 1.0 ESD8004, ESD8011
USB 2.0 HS 0.482 N/A 1.0 ESD8004, ESD8011
USB 3.0 SS 2.800 N/A 1.0 ESD8004, ESD8006, ESD8011
DisplayPort 3.600 25.00 1.0 ESD8004, ESD8006, ESD8011
from a 100 ns long reclangular pulse from a charged ‘ ion line. A simplified schemallc of a typical TLP . .hown in Figure 6. TLP I—V curves of ESD proleclion devices acc alely demol le lhe product's ESD capabilily becau. Ihe [Os ofamps un'em levels and under 100 us time 5 1e match lhose oi an ESD evenl. This illustraled in Figure 7 where an 8 kV [EC 61000—4—2 currenl waveform is compared wilh TLP currem pi i 8 A and 16A. A TLP I—V curve shows lhe voltage at which Ihe device lurns on as well as how well lhe device clamps voltage over a range of currem levels. 35 30 25 20 15 Currem (A) 10 A20 0 20 Au l<— ——l="" mmsli="" vc="" i="" figure="" 6.="" simplified="" sche="" sysi="" ii="" iecs="" w="" itlpsa="" —tlp="" 16a="" 60="" so="" 100="" 110="" time="" (n5)="" www.0nsemi.com="" 6="" l”—="">
ESD8011
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6
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A) Current at
30 ns (A) Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 6. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 7 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 6. Simplified Schematic of a Typical TLP
System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
Figure 7. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESD8011
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7
ORDERING INFORMATION
Device Package Shipping
ESD8011MUT5G X3DFN2
(Pb−Free) 10000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SIDE VIE E 2Xb 1 2 :xLza‘E + 63 0 IE" BO'I'IOM VIEW owns the thls tn a num
ESD8011
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8
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A B
E
D
BOTTOM VIEW
b
e2X
L22X
TOP VIEW
2X
A
A1
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A0.25 0.33
A1 −−− 0.05
b0.22 0.28
e0.355 BSC
L2 0.17 0.23
MOUNTING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.74
1
0.30
0.31
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
2
1
See Application Note AND8398/D for more mounting details
A
M
0.05 BC
A
M
0.05 BC
2X
2X
RECOMMENDED
PIN 1
INDICATOR
(OPTIONAL)
D0.58 0.66
E0.28 0.36
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P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ESD8011/D
HDMI is a registered trademark of HDMI Licensing, LLC.
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