NCV7342 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 4 1Publication Order Number:
NCV7342/D
NCV7342
High Speed Low Power CAN
Transceiver
Description
The NCV7342 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
The NCV7342 is an addition to the CAN high−speed transceiver
family complementing NCV734x CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
Due to the wide common−mode voltage range of the receiver inputs
and other design features, the NCV7342 is able to reach outstanding
levels of electromagnetic susceptibility (EMS). Similarly, extremely
low electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
Features
Compatible with the ISO 11898−2, ISO 11898−5 Standards
High Speed (up to 1 Mbps)
VIO Pin on NCV7342−3 Version Allowing Direct Interfacing with
3 V to 5 V Microcontrollers
VSPLIT Pin on NCV7342−0 Version for Bus Common Mode
Stabilization
Very Low Current Consumption in Standby Mode with Wake−up via
the Bus
Excellent Electromagnetic Susceptibility (EMS) Level Over Full
Frequency Range. Very Low Electromagnetic Emissions (EME) Low
EME Also Without Common Mode (CM) Choke
Bus Pins Protected Against >15 kV System ESD Pulses
Transmit Data (TxD) Dominant Time−out Function
Bus Dominant Time−out function in Standby Mode
Under All Supply Condition the Chip Behaves Predictably
No Disturbance of the Bus Lines with an Unpowered Node
Thermal Protection
Bus Pins Protected Against Transients in an Automotive
Environment
Bus Pins Short Circuit Proof to Supply Voltage and Ground
These are Pb−Free Devices
Quality
Wettable Flank Package for Enhanced Optical Inspection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Typical Applications
Automotive
Industrial Networks
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5
6
7
8
1
2
3
4
TxD
RxD
STB
GND
CANL
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
ORDERING INFORMATION
VCC
VSPLIT (−0)
VIO (−3)
CANH
PIN ASSIGNMENTS
MARKING DIAGRAMS
1
8
SOIC−8
D SUFFIX
CASE 751AZ
NV7342−x= Specific Device Code
x = 0 or 3
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
NV7342−x
ALYW G
G
1
8
NV7342−x
ALYWG
G
(Note: Microdot may be in either location)
NV7342−x
ALYWG
G
1
DFN8
MW SUFFIX
CASE 506DG
1
STB
CANL
VIO
CANH
TxD
RxD
GND
VCC
1
2
3
45
6
7
8
EP Flag
NCV7342
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Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol Parameter Conditions Min Typ Max Unit
VCC Power supply voltage 4.5 5.5 V
VUVVcc Undervoltage detection voltage
on pin VCC (NCV7342−3 only) 3.5 4.5 V
ICC Supply current Dominant; VTxD = 0 V
Recessive; VTxD = VIO
75
10 mA
ICCS Supply current in standby mode
including VIO current TJ v 100°C, (Note 1) 15 mA
VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANH,L DC voltage between CANH and
CANL pin 0 < VCC < 5.5 V −50 +50 V
VESD Electrostatic discharge voltage IEC 61000−4−2 at pins CANH
and CANL −15 15 kV
VO(dif)(bus_dom) Differential bus output voltage in
dominant state 45 W < RLT < 65 W1.5 3 V
CM−range Input common−mode range for
comparator Guaranteed differential receiver
threshold and leakage current −35 +35 V
Cload Load capacitance on IC outputs 15 pF
tpd_dr Propagation delay TxD to RxD
dominant to recessive transition
See Figure 8
Ci = 100 pF between CANH to
CANL, CRxD = 15 pF 50 100 230 ns
tpd_rd Propagation delay TxD to RxD
recessive to dominant transition
See Figure 8
Ci = 100 pF between CANH to
CANL, CRxD = 15 pF 50 120 230 ns
TJJunction temperature −40 150 °C
1. Not tested in production. Guaranteed by design and prototype evaluation.
TXD C Tmer ¢ 5 Mode & Driver STB ( Wakeiup ‘— Comm Comm 4 RxD ( Wakeiup Fmer GNDC—_I_ _<—>
NCV7342
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BLOCK DIAGRAMS
Mode &
Wake−up
Control
Wake−up
Filter
STB
GND
RxD
2
3
7
6
COMP
COMP
5
Timer
TxD
1
Driver
Control
Thermal
Shutdown
8
4
CANH
CANL
NCV7342−0
Figure 1. NCV7342−0 Block Diagram
RB 20121109
VSPLIT
VCC
VCC
VCC
VCC
VSPLIT
TXD C Txmer $ 4 Mode & STE ( Wakeiup Comm f RxD C — —o}°_ Wake’w Fflter GND ( www.0nsemi.com 4
NCV7342
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Mode &
Wake−up
Control
Wake−up
Filter
STB
GND
RxD
2
3
7
6
COMP
COMP
5
Timer
TxD
1
Driver
Control
Thermal
Shutdown
8
4
CANH
CANL
NCV7342−3
Figure 2. NCV7342−3 Block Diagram
RB 20121109
VCC
VIO
VIO
VIO
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NCV7342
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TYPICAL APPLICATION
NCV7342−3
STB
RxD
TxD 1
4
Micro
Controller
GND
VBAT
5V−reg
GND
2
5
8
CANH
CANL
3
6
7
CAN
BUS
3V−reg
RB20120816
RLT = 60 W
RLT = 60 W
Figure 3. Application Diagram NCV7342−3
NCV7342−0
STB
RxD
TxD
1
4
Micro
Controller
GND
VBAT
5V−reg
IN OUT
GND
2
3
8CANH
CANL
5
6
7
CAN
BUS
RB20120816
VSPLIT
RLT = 60 W
RLT = 60 W
CLT = 4.7 nF
Figure 4. Application Diagram NCV7342−0
CLT = 4.7 nF
VIO VIO VCC
VCC VCC
Table 2. PIN FUNCTION DESCRIPTION
Pin Name Description
1 TxD Transmit data input; Low input Ù dominant driver; internal pull−up current
2 GND Ground
3 VCC Supply voltage
4 RxD Receive data output; dominant transmitter Ù Low output
5
5VIO
VSPLIT
Input/Output pins supply voltage. On NCV7342−3 only
Common−mode stabilization output. On NCV7342−0 only
6 CANL Low−level CAN bus line (Low in dominant mode)
7 CANH High−level CAN bus line (High in dominant mode)
8 STB Standby mode control input
EP Exposed Pad Connect to GND or left floating
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FUNCTIONAL DESCRIPTION
NCV7342 has two versions which differ from each other
only by function of pin 5.
NCV7342−0: Pin 5 is common mode stabilization output
VSPLIT. (see Figure 4) This version is full replacement of
NCV7340.
NCV7342−3: Pin 5 is VIO pin, which is supply pin for
transceiver digital inputs/output (supplying pins TxD, RxD,
STB) The VIO pin should be connected to microcontroller
supply pin. By using VIO supply pin shared with
microcontroller, the I/O levels between microcontroller and
transceiver are properly adjusted. This adjustment allows
communication between 3 V microcontroller and the
transceiver. (See Figure 3)
Operating Modes
NCV7342 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
Table 3. OPERATING MODES
Pin
STB Mode
Pin RxD
Low High
Low Normal Bus dominant Bus recessive
High Standby Wake−up
request
detected
No wake−up
request detected
Normal Mode
In normal mode, the transceiver is able to communicate
via the bus lines. The signals are transmitted and received to
the CAN controller via the pins TxD and RxD. The slopes
on the bus lines outputs are optimized to give extremely low
EME.
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10 mA. When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of tdwakerd. The RxD pin is driven Low by the
transceiver to inform the controller of the wake−up request.
VIO Supply Pin
The VIO pin (available only on NCV7342−3 version)
should be connected to microcontroller supply pin. By using
VIO supply pin shared with microcontroller the I/O levels
between microcontroller and transceiver are properly
adjusted. See Figure 3. Pin VIO also provides the internal
supply voltage for low−power differential receiver of the
transceiver. This allows detection of wake−up request even
when there is no supply voltage on Pin VCC.
Split Circuit
The VSPLIT pin (available on NCV7342−0 version) is
operational only in normal mode. In standby mode this pin
is floating. The VSPLIT can be connected as shown in
Figure 4 or, if it’s not used, can be left floating. Its purpose
is to provide a stabilized DC voltage of 0.5 · VCC to the bus
reducing possible steps in the common−mode signal,
therefore reducing EME. These unwanted steps could be
caused by an unpowered node on the network with excessive
leakage current from the bus that shifts the recessive voltage
from its nominal 0.5 · VCC voltage.
Wake−up
When a valid wake−up (dominant state longer than tWake)
is received during the standby mode, the RxD pin is driven
Low after tdwakerd. The wake−up detection is not latched:
RxD returns to High state after tdwakedr when the bus signal
is released back to recessive – see Figure 5.
CANH
CANL
STB
RxD1
time
normal standby
Figure 5. NCV7342 Wake−up behavior
>tWake <tWake
tdwakerd tdwakedr
tWake(RxD)
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Over−temperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 180°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes High. The thermal protection
circuit is particularly needed in case of a bus line failure.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication), if pin TxD is forced
permanently Low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (tdom(TxD)) limits the
minimum possible bit rate to 8 kbps.
Bus Dominant Time−out Function
Bus dominant time−out timer is started in the standby
mode when CAN bus changes from recessive to dominant
state. If the dominant state on the bus is kept for longer time
than tdom(bus), the RxD pin is released to High level. The
timer is reset when CAN bus changes from dominant to
recessive state. This feature prevents generating permanent
wake−up request by the bus clamped to the dominant level.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by an accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
VCC supply dropping below VUVVcc undervoltage level
will force transceiver to switch into the standby mode. The
logic level on pin STB will be ignored as long as
undervoltage condition is not recovered. (NCV7342−3
version only)
VIO supply dropping below VUVDVIO undervoltage
detection level will cause the transceiver to disengage from
the bus (no bus loading) until the VIO voltage recovers.
(NCV7342−3 version only)
The pins CANH and CANL are protected against
automotive electrical transients (according to ISO 7637; see
Figure 6). Pins TxD and STB are pulled High internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
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ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min Max Unit
VSUP Supply voltage VCC, VIO −0.3 +6 V
VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −50 +50 V
VCANH,Lmax DC voltage at pin CANH and CANL during load dump
condition 0 < VCC < 5.5 V; less than
one second 58 V
VSPLIT DC voltage at VSPLIT pin (On NCV7342−0 version only) 0 < VCC < 5.5 V; no time limit −50 +50 V
VIO DC voltage at pin TxD, RxD, STB −0.3 +6 V
Vesd Electrostatic discharge voltage at all pins according to
EIA−JESD22 (Note 2) −4 +4 kV
Standardized charged device model ESD pulses
according to ESD−STM5.3.1−1999 −750 +750 V
Electrostatic discharge voltage at CANH,CANL, VSPLIT
pins according to EIA−JESD22 (Note 2) −8 +8 kV
Electrostatic discharge voltage at CANH, CANL pins
According to IEC 61000−4−2 (Note 3) −15 +15 kV
Vschaff Transient voltage at CANH, CANL pins, See Figure 6 (Note 4) −150 +100 V
Latch−up Static latch−up at all pins (Note 5) 150mA
Tstg Storage temperature −55 +150 °C
Tamb Ambient temperature −40 +125 °C
TJMaximum junction temperature −40 +170 °C
MSL Moisture Sensitivity Level SOIC 2 −
MSL Moisture Sensitivity Level DFN 1 −
TSLD Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 6) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330 W resistor
referenced to GND. Verified by external test house
4. Pulses 1, 2a,3a and 3b according to ISO 7637 part 3. Verification by external test house.
5. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78.
6. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 5. THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, SOIC−8 (Note 7)
Thermal Resistance, Junction−to−Air, Free air, 1S0P PCB (Note 8)
Thermal Resistance, Junction−to−Air, Free air, 2S2P PCB (Note 9) RqJA
RqJA
125
75
°C/W
°C/W
Thermal Characteristics, DFN−8, 3x3 mm (Note 7)
Thermal Resistance, Junction−to−Air, Free air, 1S0P PCB (Note 8)
Thermal Resistance, Junction−to−Air, Free air, 2S2P PCB (Note 9) RqJA
RqJA
140
47
°C/W
°C/W
7. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
8. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
9. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and
4 thermal vias connected between exposed pad and first inner Cu layer.
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Table 6. CHARACTERISTICS
VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 10); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions
without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO.
Symbol Parameter Conditions Min Typ Max Unit
SUPPLY (Pin VCC)
ICC Supply current Dominant; VTxD = 0 V
Recessive; VTxD = VIO
50
6.8 75
10 mA
ICCS0Supply current in standby mode
for NCV7342−0 TJ v 100°C (Note 11) 8 15 mA
ICCS3 Supply current in standby mode
for NCV7342−3 including current
into VIO
TJ v 100°C (Note 11) 17 mA
VUVVcc Undervoltage detection voltage on
VCC pin (NCV7342−3 only) 3.5 4.5 V
TRANSMITTER DATA INPUT (Pin TxD)
VIH High−level input voltage Output recessive 2.0 6 V
VIL Low−level input voltage Output dominant −0.3 +0.8 V
IIH High−level input current VTxD = VIO −5 0 +5 mA
IIL Low−level input current VTxD = 0V −385 −200 −45 mA
CiInput capacitance Not tested 5 10 pF
TRANSMITTER MODE SELECT (Pin STB)
VIH High−level input voltage Standby mode 2.0 VIO+0.3
(Note 12) V
VIL Low−level input voltage Normal mode −0.3 +0.8 V
IIH High−level input current VSTB = VIO −5 0 +5 mA
IIL Low−level input current VSTB = 0 V −10 −4 −1 mA
CiInput capacitance Not tested 5 10 pF
RECEIVER DATA OUTPUT (Pin RxD)
IOH High−level output current Normal mode
VRxD = VIO – 0.4 V −1.2 −0.4 0.1mA
IOL Low−level output current VRxD = 0.4 V 1.5 6 12 mA
VOH High−level output voltage Standby mode
IRxD = −100 mAVIO
1.1 VIO
–0.7 VIO – 0.4 V
BUS LINES (Pins CANH and CANL)
Vo(reces) (norm) Recessive bus voltage
on pins CANH and CANL VTxD = VIO; no load; normal
mode 2.0 2.5 3.0 V
Vo(reces) (stby) Recessive bus voltage
on pins CANH and CANL VTxD = VIO; no load; standby
mode −100 0 +100 mV
Io(reces) (CANH) Recessive output current at pin
CANH −30 V < VCANH< 35 V;
0 V < VCC < 5.5 V −2.5 +2.5 mA
Io(reces) (CANL) Recessive output current at pin
CANL −30 V < VCANL < 35 V;
0 V <VCC < 5.5 V −2.5 +2.5 mA
ILI(CANH) Input leakage current to pin CANH 0W < R(VCC to GND) < 1 MW
0W < R(VIO to GND) < 1 MW
VCANL = VCANH = 5 V (Note 10)
−10 0 +10 mA
ILI(CANL) Input leakage current to pin CANL −10 0 +10 mA
Vo(dom) (CANH) Dominant output voltage at pin
CANH VTxD = 0 V 3.0 3.6 4.25 V
10.Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin.
11. Not tested in production. Guaranteed by design and prototype evaluation.
12.In case VIO > VCC, the limit is VIO + 0.3 V
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Table 6. CHARACTERISTICS
VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 10); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions
without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO.
Symbol UnitMaxTypMinConditionsParameter
BUS LINES (Pins CANH and CANL)
Vo(dom) (CANL) Dominant output voltage at pin
CANL VTxD = 0 V 0.5 1.4 1.75 V
Vo(dif) (bus_dom) Differential bus output voltage
(VCANH − VCANL)VTxD = 0 V; dominant;
45 W < RLT < 65 W
1.5 2.25 3.0 V
Vo(dif) (bus_rec) Differential bus output voltage
(VCANH − VCANL)VTxD = VIO; recessive;
no load −120 0 +50 mV
Vo(sym) (bus_dom) Bus output voltage symmetry
VCANH + VCANL
VTxD = 0 V 0.9 1.1 VCC
Io(sc) (CANH) Short circuit output current at pin
CANH VCANH = 0 V; VTxD = 0 V −90−70 −40 mA
Io(sc) (CANL) Short circuit output current at pin
CANL VCANL = 36 V; VTxD = 0 V 40 70 100 mA
Vi(dif) (th) Differential receiver threshold
voltage −12 V < VCANL < 12 V;
−12 V < VCANH < 12 V;
VCC = 4.75 V to 5.25 V
0.5 0.7 0.9 V
Vihcm(dif) (th) Differential receiver threshold
voltage for high common−mode −30 V < VCANL < 35 V;
−30 V < VCANH < 35 V;
VCC = 4.75 V to 5.25 V
0.40 0.7 1.0 V
Vi(dif) (th)_STDBY Differential receiver threshold
voltage in standby mode −12 V < VCANL < 12 V;
−12 V < VCANH < 12 V;
VCC = 4.5 V to 5.5 V
0.4 0.8 1.15 V
Ri(cm) (CANH) Common−mode input resistance
at pin CANH 15 26 37 kW
Ri(cm) (CANL) Common−mode input resistance
at pin CANL 15 26 37 kW
Ri(cm) (m) Matching between pin CANH and
pin CANL common mode input
resistance
VCANH = VCANL −0.8 0 +0.8 %
Ri(dif) Differential input resistance 25 50 75 kW
Ci(CANH) Input capacitance at pin CANH VTxD = VIO; not tested 7.5 20 pF
Ci(CANL) Input capacitance at pin CANL VTxD = VIO; not tested 7.5 20 pF
Ci(dif) Differential input capacitance VTxD = VIO ; not tested 3.75 10 pF
COMMON−MODE STABILIZATION (Pin VSPLIT) Only for NCV7342−0 version
VSPLIT Reference output voltage at pin
VSPLIT
Normal mode;
−500 mA < ISPLIT < 500 mA0.3 0.7 VCC
VSPLITo Reference output voltage at pin
VSPLIT
RloadVsplit > 1 MW0.45 0.55 VCC
ISPLIT(i) VSPLIT leakage current Standby mode −5 +5 mA
ISPLIT(lim) VSPLIT limitation current Normal mode 1.3 5 mA
VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version
VIO Supply voltage on pin VIO 2.8 5.5 V
IIOS Supply current on pin VIO in
standby mode TJ v 100°C (Note 11) 14 mA
10.Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin.
11. Not tested in production. Guaranteed by design and prototype evaluation.
12.In case VIO > VCC, the limit is VIO + 0.3 V
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Table 6. CHARACTERISTICS
VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 10); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions
without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO.
Symbol UnitMaxTypMinConditionsParameter
VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version
IIONM Supply current on pin VIO Normal mode
Dominant; VTxD = 0 V
Recessive; VTxD = VIO
0.30
0.29 0.70
0.44 1.10
0.68
mA
VUVDVIO Undervoltage detection voltage on
VIO pin 1.3 2.7 V
THERMAL SHUTDOWN
TJ(SD) Shutdown junction temperature junction temperature rising 160 180 200 °C
TIMING CHARACTERISTICS (See Figure 7 and 8)
td(TxD−BUSon) Delay TxD to bus active Ci = 100 pF between CANH to
CANL 60 ns
td(TxD−BUSoff) Delay TxD to bus inactive Ci = 100 pF between CANH to
CANL 30 ns
td(BUSon−RxD) Delay bus active to RxD CRxD = 15 pF 60 ns
td(BUSoff−RxD) Delay bus inactive to RxD CRxD = 15 pF 70 ns
tpd_dr Propagation delay TxD to RxD
dominant to recessive transition
See Figure 8
Ci = 100 pF between CANH to
CANL, CRxD = 15 pF 50 100 230 ns
tpd_rd Propagation delay TxD to RxD
recessive to dominant transition
See Figure 8
Ci = 100 pF between CANH to
CANL, CRxD = 15 pF 50 120 230 ns
td(stb−nm) Delay standby mode to normal
mode 47 ms
tWake Dominant time for wake−up via bus 0.5 2.1 5 ms
tdwakerd
Delay to flag wake event
(recessive to dominant transitions)
See Figure 5
Valid bus wake−up event,
CRxD = 15 pF 1 3.5 10 ms
tdwakedr
Delay to flag end of wake event
(dominant to recessive transition)
See Figure 5
Valid bus wake−up event,
CRxD = 15 pF 0.5 2.6 6 ms
tWake(RxD) Minimum pulse width on RxD
See Figure 5 5 ms tWake
CRxD = 15 pF 0.5 ms
tdom(TxD) TxD dominant time for time out VTxD = 0 V 1.3 5 ms
tdom(bus) Bus dominant time out Standby mode 1.3 5 ms
10.Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin.
11. Not tested in production. Guaranteed by design and prototype evaluation.
12.In case VIO > VCC, the limit is VIO + 0.3 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
— CANH TxD 7 I —> 1 N g N > 0 z RxD 4 I H 6 —| CANL B 2 15 DFT s‘ra GND + —> 1 a h > L) z RxD 4 6 CANL 2 T s‘ra GND
NCV7342
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12
MEASUREMENT SET−UPS AND DEFINITIONS
NCV7342
GND
2
3CANH
CANL
5
6
7
STB
8
RxD 4
TxD
1
1 nF
100 nF
+
1 nF
Transient
Generator
RB20121608
15 pF
5V
Figure 6. Test Circuit for Automotive Transients
8
NCV7342
GND
2
3
CANH
CANL
5
6
7
STB
RxD 4
TxD
1
100 nF
+5 V
47 uF
100 pF
RB20120816
15 pF
RL
Figure 7. Test Circuit for Timing Characteristics
VCC
VIO
VCC
VIO
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NCV7342
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13
dominant
0.9 V
0.5 V
recessive
50%
recessive
50%
TxD
CANH
CANL
RxD
RB20130429
0.7 x VCC*0.3 x VCC*
td(BUSoff−RxD)
td(BUSon−RxD)
td(TxD−BUSoff)
td(TxD−BUSon)
Vi(dif) = VCANH − VCANL
*On NCV7342−3 VCC is replaced by VIO
Figure 8. Transceiver Timing Diagram
tpd_rd tpd_dr
DEVICE ORDERING INFORMATION
Part Number Description Package Shipping
NCV7342D10R2G High Speed CAN Transceiver
with Standby and VSPLIT pin SOIC 150 8 GREEN (Matte Sn,
JEDEC MS−012)
(Pb−Free) 3000 / Tape & Reel
NCV7342D13R2G High Speed CAN Transceiver
with Standby and VIO pin
NCV7342MW3R2G High Speed CAN Transceiver
with Standby and VIO pin DFN 8
Wettable Flank
(Pb−Free) 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
:Dj \Q‘MO‘C‘D‘ NOTE 5 El 1 i ax b I-IME NOTES us DETAIL A 70" V'EW NOTES 31.7 {A2 /n:mm I ‘ \ c. 010 (2 /’/¥—‘ , an»: , 9%4Ei Aim 4 FEI €33?” 1ND VIEW T "0,“ SIDE VIEW RECOMMENDED SOLDERING FOOTPRI 8X76 ax 1.52 w 7 gamma 7}7 7 ML D‘MENS‘O 1 1,27 F‘TCH ‘For addmona‘ Inmrmahcm on aur PbiFree detafls‘ p‘ease down‘oad the ON Semwcon Meunllng Techniques Refierence Manua‘ www.0nsemi.com 14
NCV7342
www.onsemi.com
14
PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ
ISSUE B
7.00
8X
0.76
8X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
14
85
SEATING
PLANE
DETAIL A
0.10 C
A1
DIM MIN MAX
MILLIMETERS
h0.25 0.41
A--- 1.75
b0.31 0.51
L0.40 1.27
e1.27 BSC
c0.10 0.25
A1 0.10 0.25
L2
M
0.25 A-B
b8X
CD
A
B
C
TOP VIEW
SIDE VIEW
0.25 BSC
E1 3.90 BSC
E6.00 BSC
D
e
D
0.20 C
0.10 C
2X
NOTE 6
NOTES 4&5
NOTES 4&5
SIDE VIEW
END VIEW
E E1
D
0.10 C D
D
NOTES 3&7
NOTE 6
NOTE 8
A
A2
A2 1.25 ---
D4.90 BSC
H
SEATING
PLANE
DETAIL A
LC
L2
h
45 CHAMFER5
c
NOTE 7
Ui II E g a s m 5 a F 7 f \ ‘ T \ 065 LAP PITCH ‘Far addmona‘ mlormamn on our PbiFree 0 NOTE: dams, p‘ease down‘aad me ON Sermca Mauntmg Techmques Relerence Manna BOTTOM VIEW
NCV7342
www.onsemi.com
15
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506DG
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
E
D
D2
E2
BOTTOM VIEW
b
e
8X
0.10 B
0.05
AC
CNOTE 3
2X
0.10 C
PIN ONE
REFERENCE
TOP VIEW
2X 0.10 C
A
A1
A3
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
L
8X
14
58
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.25 0.35
D3.00 BSC
D2 2.30 2.50
E3.00 BSC
E2 1.50 1.70
e0.65 BSC
L0.35 0.45
8X
0.60
2.56
1.70
0.40
1
0.65
PITCH
3.30
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
8X
DIMENSIONS: MILLIMETERS
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
L
DETAIL A
K
NOTE 4
e/2
SOLDERING FOOTPRINT*
K
0.30 TYP
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P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NCV7342/D
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