NCP1392B,D Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 4 1Publication Order Number:
NCP1392/D
NCP1392B, NCP1392D
High-Voltage Half-Bridge
Driver with Inbuilt
Oscillator
The NCP1392B/D is a self−oscillating high voltage MOSFET
driver primarily tailored for the applications using half bridge
topology. Due to its proprietary high−voltage technology, the driver
accepts bulk voltages up to 600 V. Operating frequency of the driver
can be adjusted from 25 kHz to 480 kHz using a single resistor.
Adjustable Brown−out protection assures correct bulk voltage
operating range. An internal 100 ms or 12.6 ms PFC delay timer
guarantee that the main downstream converter will be turned on in the
time the bulk voltage is fully stabilized. The device provides fixed
dead time which helps lowering the shoot−through current.
Features
Wide Operating Frequency Range − from 25 kHz to 480 kHz
Minimum frequency adjust accuracy $3%
Fixed Dead Time − 0.6 ms or 0.3 ms
Adjustable Brown−out Protection for a Simple PFC Association
100 ms or 12.6 ms PFC Delay Timer
Non−latched Enable Input
Internal 16 V VCC Clamp
Low Startup Current of 50 mA
1 A / 0.5 A Peak Current Sink / Source Drive Capability
Operation up to 600 V Bulk Voltage
Internal Temperature Shutdown
SOIC−8 Package
These are Pb−Free Devices
Typical Applications
Flat Panel Display Power Converters
Low Cost Resonant SMPS
High Power AC/DC Adapters for Notebooks
Offline Battery Chargers
Lamp Ballasts
Device Package Shipping
ORDERING INFORMATION
NCP1392BDR2G SOIC−8
(Pb−Free)
2500 /
Tape & Reel
MARKING
DIAGRAMS
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8
SOIC−8
CASE 751
1392x
ALYWW
G
1
8
1392x = Specific Device Code
x = B or D
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G= Pb−Free Package
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
PINOUT DIAGRAM
VCC
Rt
BO
GND
Vboot
Mupper
HB
Mlower
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(Pb−Free)
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W ; u n * ji M iii L Figure 1. Typical Application Example Ht* " V www.0nsemi.com 2
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Figure 1. Typical Application Example
+
+
PFC FRONT STAGE
Rbo2
Rf Rfmax Rfstart
Cbulk
Rbo1
Dboot
VCC
Rt
Bo
GND
Vboot
Mupper
HB
Mlower
Cboot
M2
NCP1392
DC
OUTPUT
AC
OUTPUT
CSS
M1
PIN FUNCTION DESCRIPTION
Pin # Pin Name Function Pin Description
1 VCC Supplies the Driver The driver accepts up to 16 V (given by internal zener clamp)
2 Rt Timing Resistor Connecting a resistor between this pin and GND, sets the operating frequency
3 BO Brown−Out/Enable Input Brown−Out function detects low input voltage conditions. Enable Input, when
brought above Vref_EN, stops the driver. Operation is then restored (without any
delay) when BO pin voltage drops by EN_Hyste below Vref_EN.
4 GND IC Ground
5 Mlower Low−Side Driver Output Drives the lower side MOSFET
6 HB Half−Bridge Connection Connects to the half−bridge output
7 Mupper High−Side Driver Output Drives the higher side MOSFET
8 Vboot Bootstrap Pin The floating supply terminal for the upper stage
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+
+
+
+
20ms
Filter
HIGH Level for 50ms After VCC On
VrefBO
+VrefEN
SW
Ihyster
BO
VCC
Rt
VCC
Management
PON
RESET
TSD
VCC
Clamp
VCC VDD
Vref
PFC Delay
(100ms)
Vref
VDD
+Vref
IDT
Ct
S
D
R
CLK
Q
Q
Pulse
Trigger
Level
Shifter
UV
Detect
DELAY
S
R
Q
Q
Vboot
Muppe
r
Bridg
e
Mlowe
r
GND
VCC
Figure 2. Internal Circuit Architecture (B Version)
0.5ms
Filter
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+
+
+
20ms
Filter
HIGH Level for 6.3 ms After VCC On
VrefBO
SW
Ihyster
BO
VCC
Rt
VCC
Management
PON
RESET
TSD
VCC
Clamp
VCC VDD
Vref
PFC Delay
(12.6 ms)
Vref
VDD
+Vref
IDT
Ct
S
D
R
CLK
Q
Q
Pulse
Trigger
Level
Shifter
UV
Detect
DELAY
S
R
Q
Q
Vboot
Muppe
r
Bridg
e
Mlowe
r
GND
VCC
Figure 3. Internal Circuit Architecture (D Version)
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MAXIMUM RATINGS TABLE
Symbol Rating Value Unit
Vbridge High Voltage Bridge Pin − Pin 6 −1 to +600 V
Vboot −
Vbridge Floating Supply Voltage 0 to 20 V
VDRV_HI High−Side Output Voltage Vbridge − 0.3 to
Vboot + 0.3 V
VDRV_LO Low−Side Output Voltage −0.3 to VCC +0.3 V
dVbridge/dt Allowable Output Slew Rate $50 V/ns
ICC Maximum Current that Can Flow into VCC Pin (Pin 1), (Note 1) 20 mA
V_Rt Rt Pin Voltage −0.3 to 5 V
Maximum Voltage, All Pins (Except Pins 4 and 5) −0.3 to 10 V
RqJA Thermal Resistance Junction−to−Air, IC Soldered on 50 mm2 Cooper 35 mm178 °C/W
RqJA Thermal Resistance Junction−to−Air, IC Soldered on 200 mm2 Cooper 35 mm147 °C/W
Storage Temperature Range −60 to +150 °C
ESD Capability, Human Body Model (All Pins Except HV Pins 6, 7 and 8) 2.0 kV
ESD Capability, Human Body Model (HV Pins 6, 7 and 8) 1.5 kV
ESD Capability, Machine Model 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains internal zener clamp connected between VCC and GND terminals. Current flowing into the VCC pin has to be limited
by an external resistor when device is supplied from supply which voltage is higher than VCCclamp (16 V typically). The ICC parameter is
specified for VBO = 0 V.
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 12 V, unless otherwise noted)
Characteristic Pin Symbol Min Typ Max Unit
SUPPLY SECTION
Turn−On Threshold Level, VCC Going Up 1 VCCON 10 11 12 V
Minimum Operating Voltage after Turn−On 1 VCCmin 8 9 10 V
Startup Voltage on the Floating Section 1 VbootON 7.8 8.8 9.8 V
Cutoff Voltage on the Floating Section, 1 Vbootmin 7 8 9 V
VCC Level at which the Internal Logic gets Reset 1 VCCreset − 6.5 − V
Startup Current, VCC < VCCON, 0°C v Tamb v +125°C 1 ICC − 50 mA
Startup Current, VCC < VCCON, −40°C v Tamb < 0°C 1 ICC − 65 mA
Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz 1 ICC1 − 2.2 − mA
Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz 1 ICC2 − 3.4 − mA
Consumption in Fault Mode (Drivers Disabled, VCC > VCC(min), RT = 3.5 kW)1 ICC3 − 2.56 mA
Consumption During PFC Delay Period, 0°C v Tamb v +125°C ICC4 − 400 mA
Consumption During PFC Delay Period, −40°C v Tamb < 0°C ICC4 − 470 mA
Internal IC Consumption, No Output Load on Pin 8/7 FSW = 100 kHz 8 Iboot1 − 0.3 − mA
Internal IC Consumption, 1 nF Load on Pin 8/7 FSW = 100 kHz 8 Iboot2 − 1.44 − mA
Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin) 8 Iboot3 − 0.1 − mA
VCC Zener Clamp Voltage @ 20 mA 1 VCCclamp 15.4 16 17.5 V
INTERNAL OSCILLATOR
Minimum Switching Frequency
(Rt = 35 kW on Pin 2 for DT = 600 ns, Rt = 70 kW on Pin 2 for DT = 300 ns) 2 FSW min 24.25 25 25.75 kHz
Maximum Switching Frequency (B Version), Rt = 3.5 kW on Pin 2, DT = 600 ns 2 FSW maxB 208 245 282 kHz
Maximum Switching Frequency (D Version), Rt = 3.5 kW on Pin 2, DT = 300 ns 2 FSW maxD 408 480 552 kHz
Reference Voltage for all Current Generations 2 Vref RT 3.33 3.5 3.67 V
Internal Resistance Discharging Csoft−start 2 Rtdischarge − 500 − W
Operating Duty Cycle Symmetry 5, 7 DC 48 50 52 %
NOTE: Maximum capacitance directly connected to Pin 2 must be under 100 pF.
DRIVE OUTPUT
Output Voltage Rise Time @ CL = 1 nF, 10−90% of Output Signal 5, 7 Tr− 40 − ns
Output Voltage Fall Time @ CL = 1 nF, 10−90% of Output Signal 5, 7 Tf− 20 − ns
Source Resistance 5, 7 ROH − 12 W
Sink Resistance 5, 7 ROL − 5 W
Deadtime (B Version) 5,7 TdeadB 540 610 720 ns
Deadtime (D Version) 5,7 TdeadD 260 305 360 ns
Leakage Current on High Voltage Pins to GND (600 Vdc) 6,7,8 IHVLeak − − 5 mA
PROTECTION
Brown−Out Input Bias Current 3 IBObias − 0.01 − mA
Brown−Out Level 3 VBO 0.95 1 1.05 V
Hysteresis Current, Vpin3 < VBO 3 IBO 15.6 18.2 20.7 mA
Reference Voltage for EN Input (B Version) 3 Vref EN 1.9 2 2.1 V
EN Comparator (not available in D Version) − Vref EN_D − − − V
Enable Comparator Hysteresis 3 EN_Hyste − 100 mV
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 12 V, unless otherwise noted)
Characteristic UnitMaxTypMinSymbolPin
PROTECTION
Propagation Delay Before Drivers are Stopped 3 EN_Delay − 0.5 ms
Delay Before Any Driver Restart (B Version) PFC Delay − 100 − ms
Delay Before Any Driver Restart (D Version) PFC Delay − 12.6 − ms
Temperature Shutdown TSD 140 − °C
Hysteresis TSDhyste − 30 °C
Brown Out discharge time (B Version) (Note 2) BOdisch − 50 − ms
Brown Out discharge time (D Version) (Note 2) BOdisch − 6.3 − ms
2. Guaranteed by design.
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TYPICAL CHARACTERISTICS
11.01
11.00
10.99
10.98
10.97
10.96
10.95
10.94
10.93
10.92
10.91
−40 −20 0 20 40 60 80 100 120
VOLTAGE (V)
TEMPERATURE (°C)
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOLTAGE (V)
8.98
8.97
8.96
8.95
8.94
8.93
8.92
8.91
8.90
Figure 4. VCCon Figure 5. VCCmin
VOLTAGE (V)
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 6. VBOOTon
8.85
8.80
8.75
8.70
8.65
8.60
8.55
TEMPERATURE (°C)
Figure 7. VBOOTmin
−40 −20 0 20 40 60 80 100 120
VOLTAGE (V)
8.10
8.05
8.00
7.95
7.90
7.85
7.80
7.75
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 8. ROH
20
18
16
14
12
10
8
6
4
2
0
TEMPERATURE (°C)
Figure 9. ROL
−40 −20 0 20 40 60 80 100 120
8
7
6
5
4
3
2
1
0
RESISTANCE (W)
RESISTANCE (W)
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TYPICAL CHARACTERISTICS
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 10. FSWmax (B Version)
FREQUENCY (kHz)
243.4
TEMPERATURE (°C)
Figure 11. FSWmax (D Version)
−40 −20 0 20 40 60 80 100 120
FREQUENCY (kHz)
25.05
25.00
24.95
24.90
24.85
24.80
24.75
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 12. FSWmin (B Version)
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
450
TEMPERATURE (°C)
Figure 13. FSWmin (D Version)
−40 −20 0 20 40 60 80 100 120
400
350
300
250
200
150
100
50
0
Figure 14. ICC_startup Figure 15. ICC4
CURRENT (mA)
CURRENT (mA)
243.2
243.0
242.8
242.6
242.4
242.2
242.0
241.8 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FREQUENCY (kHz)
490
485
480
475
470
465
460
455
450
TEMPERATURE (°C)
−40 −20 0 20 40 60 80 100 120
FREQUENCY (kHz)
24.92
24.90
24.88
24.86
24.84
24.82
24.80
25.00
24.98
24.96
24.94
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TYPICAL CHARACTERISTICS
Figure 16. Tdead (B Version)
TEMPERATURE (°C)
Figure 17. Tdead (D Version)
−40 −20 0 20 40 60 80 100 120
2.008
VOLTAGE (V)
2.006
2.004
2.002
2.000
1.998
1.996
1.994
1.992
1.990 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 18. PFCdelay (B Version)
VOLTAGE (V)
1.015
1.014
1.013
1.012
1.011
1.010
1.009
1.008
1.007
Figure 19. PFCdelay (D Version)
Figure 20. Vref_EN Figure 21. VBO
TIME (ns)
645
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
640
635
630
625
620
615
610 −40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
TIME (ns)
330
325
320
315
310
305
300
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
TIME (ms)
14.0
13.5
13.0
12.5
12.0
11.5
11.0
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
109
TIME (ms)
108
107
106
105
104
103
102
101
100
90
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TYPICAL CHARACTERISTICS
Irt (mA)
Figure 22. Rt_discharge
0.2
FREQUENCY (kHz)
290
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
240
190
140
90
40
Figure 23. ENhyste
Figure 24. IBO Figure 25. VCC_clamp
Figure 26. Irt and Appropriate Frequency
(B Version)
TEMPERATURE (°C)
−40 −20 0 20 40 60 80 100 120
VOLTAGE (V)
17.0
16.8
16.6
16.4
16.2
16.0
15.8
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
19.4
19.2
19.0
18.8
18.6
18.4
18.2
18.0
17.8
17.6
17.4
CURRENT (
m
A)
VOLTAGE (mV)
110
108
106
104
102
100
98
96
94
92
90
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 27. Irt and Appropriate Frequency
(D Version)
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
580
560
540
520
500
480
460
440
420
400
RESISTANCE (
W
)
Irt (mA)
0.2
FREQUENCY (kHz)
600
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1
.2
400
300
200
100
0
500
0.0 0.1
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APPLICATION INFORMATION
The NCP1392 is primarily intended to drive low cost half
bridge applications and especially resonant half bridge
applications. The IC includes several features that help the
designer to cope with resonant SPMS design. All features
are described thereafter:
Wide Operating Frequency Range: The internal
current controlled oscillator is capable to operate over
wide frequency range. Minimum frequency accuracy is
$3%.
Fixed Dead−Time: The internal dead−time helping to
fight with cross conduction between the upper and
lower power transistors. Three versions with different
dead time values are available to cover wide range of
applications.
PFC Timer: Fixed delay is placed to IC operation
whenever the driver restarts (VCCON or BO_OK detect
events). This delay assures that the bulk voltage will be
stabilized in the time the driver provides pulses on the
outputs. Another benefit of this delay is that the soft
start capacitor will be full discharged before any restart.
Brown−Out Detection: The BO input monitors bulk
voltage level via resistor divider and thus assures that
the application is working only for wanted bulk voltage
band. The BO input sinks current of 18.2 mA until the
VrefBO threshold is reached. Designer can thus adjust
the bulk voltage hysteresis according to the application
needs.
Non−Latched Enable Input: The enable comparator
input is connected in parallel to the BO terminal to
allow the designer stop the output drivers when needed.
There is no PFC delay when enable input is released so
skip mode for resonant SMPS applications and
dimming for light ballast applications are possible.
Internal VCC Clamp: The internal zener clamp offers
a way to prepare passive voltage regulator to maintain
VCC voltage at 16 V in case the controller is supplied
from unregulated power supply or from bulk capacitor.
Low Startup Current: This device features maximum
startup current of 50 mA which allows the designer to
use high value startup resistor for applications when
driver is supplied from the auxiliary winding. Power
dissipation of startup resistor is thus significantly
reduced.
Current Controlled Oscillator
The current controlled oscillator features a high−speed
circuitry allowing operation from 50 kHz up to 960 kHz.
However, as a division by two internally creates the two Q
and Q outputs, the final effective signal on output Mlower
and Mupper switches in half frequency range. The VCO is
configured in such a way that if the current that flows out
from the Rt pin increases, the switching frequency also goes
up. Figure 28 shows the architecture of this oscillator.
Figure 28. The Internal Current Controlled Oscillator Architecture
+
+
Delay
Vref Rt
From PFC Delay
Ct
Rt
Rt
Vref
S
D
CLK
R
IDT
Q
Q
From EN
Cmp.
PON
Reset
VDD
A
B
Dead
Time
Csoft−start
+
+
Rsoft−start
The internal timing capacitor Ct is charged by current
which is proportional to the current flowing out from the
Rt pin. The discharging current IDT is applied when voltage
on this capacitor reaches 2.5 V. The output drivers are
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. The charging
current and thus also whole oscillator is disabled during the
PFC delay period to keep the IC consumption below 400 mA.
Figure 29. Typical RI Pin Connection
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This is valuable for applications that are supplied from
auxiliary winding and VCC capacitor is supposed to provide
energy during PFC delay period.
For the resonant applications and light ballast applications
it is necessary to adjust minimum operating frequency with
high accuracy. The designer also needs to limit maximum
operating and startup frequency. All these parameters can be
adjusted using few external components connected to the Rt
pin as depicted in Figure 29.
Figure 29. Typical Rt Pin Connection
Rfmax
Rt
VCC
Rt
Rfstart Rbias
Rfmax−OCP
Rcomp Ccomp
CSS
D1
TLV431 (to primary
current sensor)
(to secondary
voltage regulator)
NCP1392
Voltage Feedback Current Feedback
The minimum switching frequency is given by the Rt
resistor value. This frequency is reached if there is no
optocoupler or current feedback action and soft start period
has been already finished. The maximum switching
frequency excursion is limited by the Rfmax selection. Note
that the Fmax value is influenced by the optocoupler
saturation voltage value. Resistor Rfstart together with
capacitor CSS prepares the soft start period after PFC timer
elapses. The Rt pin is grounded via an internal switch during
the PFC delay period to assure that the soft start capacitor
will be fully discharged via Rfstart resistor.
There is a possibility to connect other control loops (like
current control loop) to the Rt pin. The only one limitation
lies in the Rt pin reference voltage which is VrefRt = 3.5 V.
Used regulator has to be capable to work with voltage lower
than VrefRt.
The TLV431 shunt regulator is used in the example from
figure 4 to prepare current feedback loop. Diode D1 is used
to enable regulator biasing via resistor Rbias. Total
saturation voltage of this solution is 1.25 + 0.6 = 1.85 V for
room temperature. Shottky diode will further decrease
saturation voltage. Rfmax − OCP resistor value, limits the
maximum frequency that can be pushed by this regulation
loop. This parameter is not temperature stable because of the
D1 temperature drift.
Brown−Out Protection
The Brown−Out circuitry (BO) offers a way to protect the
application from low DC input voltages. Below a given
level, the controller blocks the output pulses, above it, it
authorizes them. The internal circuitry, depicted by
Figure 30, offers a way to observe the high−voltage (HV)
rail.
Figure IBO is on IBO is o" www.cnsem om
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Figure 30. The internal Brown−Out Configuration with an Offset Current Sink
+
Rupper
BO
Rlower
VrefBO
IBO
SW
20ms
Filter
Vbulk
High Level for BOdisch time after VCC ON
BO_OK to and gates
To PFC Delay
+
A resistive divider made of Rupper and Rlower, brings a
portion of the HV rail on Pin 3. Below the turn−on level,
the 18.2 mA current sink (IBO) is on. Therefore, the turn−on
level is higher than the level given by the division ratio
brought by the resistive divider. To the contrary, when the
internal BO_OK signal is high (PFC timer runs or Mlower
and Mupper pulse), the IBO sink is deactivated. As a result,
it becomes possible to select the turn−on and turn−off levels
via a few lines of algebra:
IBO is on
VrefBO +Vbulk1 @
Rlower
Rlower )Rupper *IBO @ǒRlower @Rupper
Rlower )RupperǓ(eq. 1)
IBO is off
VrefBO +Vbulk2 @
Rlower
Rlower )Rupper
(eq. 2)
We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper:
Rlower +VrefBO @
Vbulk1 *Vbulk2
IBO @ǒVbulk2 *VrefBOǓ(eq. 3)
Rupper +Rlower @
Vbulk2 *VrefBO
VrefBO
(eq. 4)
If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then for IBO = 18.2 mA
and VrefBO = 1.0 V we obtain:
Rupper = 5.494 MW
Rlower = 22.066 kW
The bridge power dissipation is 4002 / 5.517 MW = 29 mW when front−end PFC stage delivers 400 V. Figure 31 simulation
result confirms our calculations.
v m o c m e s n o W W W mm. ,777,777,7J7L777%77777777777777777 r77777777747L777k77777777777777777
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Figure 31. Simulation Results for 350/250 ON/OFF Brown−Out Levels
The IBO current sink is turned ON for BOdisch time after
any controller restart to let the BO input voltage stabilize
(there can be connected big capacitor to the BO input and the
IBO is only 18.2 mA so it will take some time to discharge).
Once the BOdisch time one shoot pulse ends the BO
comparator is supposed to either hold the IBO sink turned
ON (if the bulk voltage level is not sufficient) or let it turned
OFF (if the bulk voltage is higher than Vbulk1).
See Figures 10 13 for better understanding on how the
BO input works.
Figure 32. BO Input Functionality − Vbulk2 < Vbulk < Vbulk1
Vbulk
VBO
BO_OK
Vcc
DRV_EN
Vbulk_ON
Vbulk_OFF
1 V
IBO is turned ON after Vcc_ON by
internal logic (for BOdisch time)
< BOdisch
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Figure 33. BO Input Functionality −Vbulk2 < Vbulk < Vbulk1, PFC Start Follows
Vbulk
VBO
BO_OK
Vcc
DRV_EN
Vbulk_ON
Vbulk_OFF
1 V
PFCdelay
Figure 34. BO Input Functionality − Vbulk > Vbulk1
Vbulk
VBO
BO_OK
Vcc
DRV_EN
Vbulk_ON
Vbulk_OFF
1 V
Checking VBO by activating IBO
sink, released after BOdisch time
BOdisch
The drivers are activated with delay specify by
PFCdelay after Vcc_ON, IBO sing has been
turned OFF by BOdisch time after Vcc_ON, BO
capacitor had enough time to charge
PFCdelay
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NCP1392B, NCP1392D
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17
Figure 35. BO Input Functionality − Vbulk < Vbulk2, PFC Start Follows
Vbulk
VBO
BO_OK
Vcc
DRV_EN
Vbulk_ON
Vbulk_OFF
1 V
PFCdelay
Non−Latched Enable Input (B Version only)
The non−latched input stops output drivers immediately
the BO terminal voltage grows above 2 V threshold. The
enable comparator features 100 mV hysteresis so the BO
terminal has to go down below 1.9 V to recover IC operation.
This input offers other features to the NCP1392 like
dimming function for lamp ballasts (Figure 36) or skip
mode capability for resonant converters (Figures 37
and 39).
Figure 36. Dimming Feature Implementation Using Nonlatched Input on BO Terminal
+
+
Q2
R2
R3 R4
R1
D1
Q1
GND
to AND gates
to AND gates
SW
VrefBO
VrefEN
Rupper
BO
Rlower
20ms
Filter
Vbulk
Rt
Rfstart
CSS
Rt
VCC
Dimming
Input
NCP1392
Ihyste
High Level for BOdisch time after VCC ON
To PFC Delay
0.5ms
Filter
+
+
Figure 37. Skip Mode Feature Implementation (Temperaiure Dependeni, Casi Effeciive) Figure 38. Skip Mode with Transisior Feaiu www.0nsemi.com 13
NCP1392B, NCP1392D
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18
The dimming feature can be easily aid to the ballast
application by adding two bipolar transistors (Figure 14).
Transistor Q2 pullup BO input when dimming signal is high.
In the same time the Q1 discharges soft start capacitor via
diode D1. Ballast application is enabled (including
soft−start phase) when dimming signal becomes low again.
Figure 37. Skip Mode Feature Implementation (Temperature Dependent, Cost Effective)
+
+
R1
Voltage
R2
GND
to AND gates
to AND gates
SW
VrefBO
VrefEN
Rupper
BO
Rlower
20ms
Filter
Vbulk
Rt
Rfstart
CSS
Rt
NCP1392
Feedback
D1
Ihyste
High Level for BOdisch time after VCC ON
To PFC Delay
0.5ms
Filter
+
+
Figure 38. Skip Mode with Transistor Feature Implementation (Temperature Dependent, Cost Effective)
+
+
R4
Voltage
R5
GND
to AND gates
to AND gates
SW
VrefBO
VrefEN
Rupper
BO
Rlower
20ms
Filter
Vbulk
Rt
Rfstart
CSS
Rt
NCP1392
Feedback
Ihyste
C1
R6
R3
R2
R1
VCC
Q1
High Level for BOdisch time after VCC ON
To PFC Delay
Q2
Soft−Start After Skip (If Needed)
D1
+
+
0.5ms
Filter
Figure 39. Skip Mode Fealure Imp 35-k
NCP1392B, NCP1392D
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19
Figure 39. Skip Mode Feature Implementation (Better Accuracy)
+
+
R4
Voltage
R5
GND
to AND gates
to AND gates
SW
VrefBO
VrefEN
Rupper
BO
Rlower
20ms
Filter
Vbulk
Rt
Rfstart
CSS
Rt
NCP1392
Feedback
Ihyste
IC1
TLV431
C1
R6
R3
R2
R1
VCC
Q1
High Level for BOdisch time after VCC ON
To PFC Delay
0.5ms
Filter
+
+
Figures 37 and 39 shows skip mode feature
implementation using NCP1392 driver. Voltage across
resistor R1 (R4) increases when converter enters light load
conditions. The enable comparator is triggered when
voltage across R1 is higher than Vref EN + Vf(D1) for
connection from Figure 37 (voltage across R4 is higher than
1.24 V for connection from figure 16). IC then prevents
outputs from pulsing until BO terminal voltage decreases
below 1.92 V.
Note that enable comparator serves also as an automatic
overvoltage protection. When bulk voltage is too high, the
enable input is triggered via BO divider.
Following equations can be used for easy calculations of
devices connected to Rt pin:
Minimum frequency:
Rt+3.5 @k
Frequency *q(eq. 5)
Maximum frequency where soft−start begins:
Rfstart +3.5 @k@Rt
Frequency @Rt*Rt@q*3.5 @k(eq. 6)
The soft−start duration is set by Css capacitor:
CSS +SSduration
Rfstart @5(eq. 7)
A resistor to set maximum frequency, if the optocoupler is
fully conductive is calculated by the following equation:
R
(R4)R5) +ǒ−3.5 )Vce_satǓ@k@Rt
Frequency @Rt−R
t@q−3.5@k)k@Vce_sa
t
(eq. 8
)
The constants in the equations are as follows:
Version B: k = 244.4106, q = 0.555103
Version D: k = 478.9106, q = 1.053103
i Figure 40. The lmernal High—Voflage Section ol the NCP1392 m E: 1 I w 3w E Hfl [fiflmaaflfii :
NCP1392B, NCP1392D
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The High−Voltage Driver
Figure 40 shows the internal architecture of the
high−voltage section. The device incorporates an upper
UVLO circuitry that makes sure enough Vgs is available for
the upper side MOSFET. The VCC for floating driver section
is provided by Cboot capacitor that is refilled by external
bootstrap diode.
Figure 40. The Internal High−Voltage Section of the NCP1392
Hgd
Delay
UV
Detect
HB
VCC
Lgd
GND
Pulse
Trigger
Level
Shifter
from latch
high if OK
from PFC
Delay
Boot
S
R
Q
Q
Cboot
A
B
DEAD TIME
A
B+
Dboot
Vaux
Vbulk
The A and B outputs are delivered by the internal logic, as
depicted in block diagram. This logic is constructed in such
a way that the Mlower driver starts to pulse firs after any
driver restart. The bootstrap capacitor is thus charged during
first pulse. A delay is inserted in the lower rail to ensure good
matching between these propagating signals. As stated in the
maximum rating section, the floating portion can go up to
600 Vdc and makes the IC perfectly suitable for offline
applications featuring a 400 V PFC front−end stage.
H’H’H’H
NCP1392B, NCP1392D
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21
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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NCP1392/D
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