XRT91L34 Datasheet by MaxLinear, Inc.

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EXA ourcrc CDRREFSEL RESET HOST W Dmsms /sm cnnmsn munmran
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
OCTOBER 2007 REV. 1.0.1
GENERAL DESCRIPTION
The XRT91L34 is a fully integrated quad channel
multirate Clock and Data Recovery (CDR) device for
SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52
Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0
applications. The device provides Clock and Data
Recovery (CDR) function by synchronizing its on-chip
Voltage Controlled Oscillator (VCO) to the incoming
serial data stream. The device internally monitors
Loss of Lock (LOL) conditions and automatically
mutes recovered data upon Loss of Signal (LOS)
conditions.
C
LOCK
AND
D
ATA
R
ECOVERY
O
VERVIEW
The clock and data recovery (CDR) unit accepts the
high speed NRZ serial data from the LVDS or
Differential LVPECL receiver and generates a clock
that is the same frequency as the incoming data. The
CDR block uses a reference clock to train and
monitor its clock recovery PLL. All four channels
share a single 77.76MHz or 19.44MHz reference
clock. Upon startup, the PLL locks to the local
reference clock. Once this is achieved, the PLL
attempts to lock onto the incoming receive serial data
stream. Whenever the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately ±500 ppm, the clock
recovery PLL will switch and lock back onto the local
reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event
occurs, the CDR will continue to supply a recovered
clock (based on the local reference) to the framer/
mapper device. When the SDEXT is de-asserted by
the optical module or when internal DLOS is
asserted, the receive serial data output will be forced
to a logic zero state for the entire duration that a LOS
condition is declared. This acts as a receive data
mute upon LOS function to prevent random noise
from being misinterpreted as valid incoming data.
When the SDEXT becomes active and the recovered
clock is determined to be within ±500 ppm accuracy
with respect to the local reference source and LOS is
no longer declared, the clock recovery PLL will switch
and lock back onto the incoming receive serial data
stream. Figure 1 shows the block diagram of the
XRT91L34.
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L34
Channel 3
Channel 2
RXDO0P
RXDO0N
RXCLKO0P
RXCLKO0N
LOL0
Channel 0
LVDS/LVPECL
Output Drivers
CDR
RECVD-
DATAOUT
RECVD-
CLKOUT
Channel Control Block
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
LVDS/LVPECL
Input Drivers
RXDI0P
RXDI0N
RXDATAIN
RX LOOP
FILTER
SDEXT0
POL0
CDRDIS0
DATA0RATE0
DATA0RATE1
Global Control Block
RESET
INT
REFCLKP
HOST /HW
REFCLKN
1
0
CDRREFSEL
Channel 1
TTLREFCLK
19.44 / 77.76 MHz
100
OUTCFG
Serial Proccesor
Interface
SCLK
DLOSDIS /SDI
SDO
CS
XRT91L34
1
0
HOST MODE
ONLY
RCLKDIS0
LVDS/LVPECL LEVEL SELECT
DLOS
DLOSDIS
TEST
SDI
DLOSDIS
1
0
XRT91L34
2
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
APPLICATIONS
SONET/SDH-based Transmission Systems
Add/Drop Multiplexers
Cross Connect Equipment
ATM and Multi-Service Switches, Routers and Switch/Routers
DSLAMS
SONET/SDH Test Equipment
DWDM Termination Equipment
FEATURES
Quad Channel CDR targeted for SONET STS-12/STS-3/STS-1 and SDH STM-4/STM-1/STM-0 Applications
Selectable data rate operation between 622.08 Mbps, 155.52 Mbps, or 51.84 Mbps.
Single-chip fully integrated solution containing quad-channel clock and data recovery (CDR) functions
Optional flexibility to configure for LVDS or Differential LVPECL High Speed I/O Interface
Internal 100 termination for the high speed LVDS/Differential LVPECL inputs included
Utilizes reference clock frequency of either 19.44 MHz or 77.76 MHz
Host mode serial microprocessor interface simplifies monitor and control, including LOS monitoring
Diagnostics features include LOS monitoring in Host Mode and automatic recovered data mute upon LOS
Loss of Lock Detect output for each channel
Permits mixed data rate configuration of the four channels
Independent power down control of unused channels for lower power operation
Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications.
Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V Differential LVPECL, and
JESD 8-B LVTTL and LVCMOS standard.
Operates with dual power supply of 1.8V core and 3.3V IO supply
90mW LVDS/ 350mW Differential LVPECL per channel Typical Power Dissipation
Package: 14 x 14 x 1.4 mm 128-pin LQFP
RoHS Compliant Lead-Free package availability
ESD greater than 2kV on all pins
XRT91L34
3
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
F
IGURE
2. 128 LQFP P
IN
O
UT
OF
THE
XRT91L34 (T
OP
V
IEW
)
CAP2P
CAP2N
CAP3P
CAP3N
CDRDIS2
CDRDIS3
SDEXT2
POL2
SDEXT3
POL3
DATA2RATE1
SCLK
CS
DLOSDIS/SDI
SDO
AVDD1.8
GND
LOL2
LOL3
AVDD1.8
GND
GND
AVDD1.8
GND
DVDD1.8
INT
OUTCFG
RESET
TEST
CAP0P
CAP0N
CAP1P
CAP1N
CDRDIS0
CDRDIS1
DATA0RATE0
DATA0RATE1
SDEXT0
POL0
SDEXT1
POL1
GND
GND
AVDD1.8
GND
LOL0
AVDD1.8
DVDD1.8
GND
AVDD1.8
GND
TTLREFCLK
REFCLKN
REFCLKP
CDRREFSEL
HOST/HW
LOL1
DATA1RATE0
DATA1RATE1
n/c
n/c
DATA2RATE0
DATA3RATE1
DATA3RATE0
RXDI0P
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
RXDI0N
RXDI1P
RXDI1N
RXDI2P
RXDI2N
RXDI3P
RXDI3N
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
XRT91L34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
122
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
RXDO0P
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
GND_IO
VDD_IO
VDD_IO
VDD_IO
GND_IO
GND_IO
GND_IO
RXDO0N
RXCLKO0P
RXCLKO0N
RXDO1P
RXDO1N
RXCLKO1P
RXCLKO1N
RXDO2P
RXDO2N
RXCLKO2P
RXCLKO2N
RXDO3P
RXDO3N
RXCLKO3P
RXCLKO3N
ORDERING INFORMATION
P
ART
N
UMBER
P
ACKAGE
O
PERATING
T
EMPERATURE
R
ANGE
XRT91L34IV 128 Pin Lead LQFP -40
°
C to +85
°
C
XRT91L34IV-F 128 Pin Lead-Free LQFP -40
°
C to +85
°
C
XRT91L34
IV
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L34 ...................................................................................................................................... 1
APPLICATIONS...........................................................................................................................................2
FEATURES
......................................................................................................................................................2
F
IGURE
2. 128 LQFP P
IN
O
UT
OF
THE
XRT91L34 (T
OP
V
IEW
)........................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3
T
ABLE
OF
C
ONTENTS
..........................................................................................................
IV
PIN DESCRIPTIONS ..........................................................................................................6
H
ARDWARE
C
ONTROL
....................................................................................................................................6
R
ECEIVER
S
ECTION
........................................................................................................................................9
P
OWER
AND
G
ROUND
..................................................................................................................................10
SERIAL
M
ICROPROCESSOR
INTERFACE......................................................................................................11
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12
1.2 STS-12/STM-4 AND STS-3/STM-1 AND STS-1/STM-0 MODE OF OPERATION ......................................... 12
T
ABLE
1: C
HANNEL
D
ATA
R
ATE
S
ELECTION
.................................................................................................................................... 12
1.3 REFERENCE CLOCK INPUT ......................................................................................................................... 13
T
ABLE
2: CDR R
EFERENCE
F
REQUENCY
O
PTIONS
(LVDS/ D
IFF
LVPECL
OR
S
INGLE
-E
NDED
LVTTL/LVCMOS)............................ 13
F
IGURE
3. R
EFERENCE
C
LOCK
D
ESIGN
O
PTIONS
............................................................................................................................ 13
2.0 RECEIVE SECTION .............................................................................................................................14
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
F
IGURE
4. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
USING
LVDS/D
IFF
LVPECL DC
COUPLING
INTERNAL
TERM
....................................... 14
F
IGURE
5. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
USING
D
IFF
LVPECL AC
COUPLING
INTERNAL
TERMINATION
..................................... 15
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
3: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 16
2.2.1 INTERNAL CLOCK AND DATA RECOVERY DISABLE ........................................................................................... 16
2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 16
2.4 INTERNAL DIGITAL LOSS OF SIGNAL AND EXTERNAL SIGNAL DETECTION ...................................... 17
F
IGURE
7. L
OSS
OF
S
IGNAL
D
ECLARATION
C
IRCUIT
........................................................................................................................ 17
T
ABLE
4: E
XTERNAL
LOS D
ECLARATION
P
OLARITY
S
ETTING
........................................................................................................... 17
2.5 MULTICHANNEL RECOVERED OUTPUT INTERFACE ............................................................................... 18
F
IGURE
8. M
ULTICHANNEL
R
ECOVERED
O
UTPUT
I
NTERFACE
B
LOCK
................................................................................................ 18
2.6 DIFFERENTIAL RECOVERED DATA OUTPUT TIMING ............................................................................... 19
F
IGURE
9. D
IFFERENTIAL
R
ECOVERED
O
UTPUT
T
IMING
................................................................................................................... 19
T
ABLE
5: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
).................................................................................... 19
T
ABLE
6: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
)...................................................................................... 19
T
ABLE
7: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-1/STM-0 O
PERATION
)...................................................................................... 19
3.0 JITTER PERFORMANCE ....................................................................................................................20
3.1 SONET JITTER REQUIREMENTS ................................................................................................................. 20
3.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 20
F
IGURE
10. GR-253/G.783 J
ITTER
T
OLERANCE
M
ASK
................................................................................................................... 20
F
IGURE
11. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
51.84 M
BPS
STS-1/STM-0.................................................................. 20
F
IGURE
12. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
155.52 M
BPS
STS-3/STM-1................................................................ 21
F
IGURE
13. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
622.08 M
BPS
STS-12/STM-4.............................................................. 21
3.1.2 RX JITTER TRANSFER .............................................................................................................................................. 22
F
IGURE
14. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
51.84 M
BPS
STS-1/STM-0.................................................................... 22
F
IGURE
15. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
155.52 M
BPS
STS-3/STM-1.................................................................. 22
F
IGURE
16. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
622.08 M
BPS
STS-12/STM-4................................................................ 23
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................24
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 24
4.1 SERIAL TIMING INFORMATION .................................................................................................................... 24
F
IGURE
18. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 24
4.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 25
4.2.1 R/W (SCLK1)............................................................................................................................................................... 25
4.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 25
4.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 25
4.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 25
4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 25
XRT91L34
V
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
5.0 REGISTER MAP AND BIT DESCRIPTIONS .......................................................................................26
T
ABLE
8: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
M
AP
................................................................................................................ 26
T
ABLE
9: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
00 B
IT
D
ESCRIPTION
.................................................................................... 27
T
ABLE
10: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
01 B
IT
D
ESCRIPTION
.................................................................................. 28
T
ABLE
11: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
02 B
IT
D
ESCRIPTION
.................................................................................. 28
T
ABLE
12: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
03 B
IT
D
ESCRIPTION
.................................................................................. 29
T
ABLE
13: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
04 B
IT
D
ESCRIPTION
.................................................................................. 29
T
ABLE
14: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
05 B
IT
D
ESCRIPTION
.................................................................................. 29
T
ABLE
15: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
08, 0
X
10, 0
X
18, 0
X
20 B
IT
D
ESCRIPTION
.................................................... 30
T
ABLE
16: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
09, 0
X
11, 0
X
19, 0
X
21 B
IT
D
ESCRIPTION
.................................................... 31
T
ABLE
17: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
0A, 0
X
12, 0
X
1A, 0
X
22 B
IT
D
ESCRIPTION
................................................... 32
6.0 ELECTRICAL CHARACTERISTICS ...................................................................................................33
A
BSOLUTE
M
AXIMUM
RATINGS .................................................................................................................. 33
T
ABLE
18: A
BSOLUTE
M
AXIMUM
P
OWER
A
ND
I
NPUT
/O
UTPUT
R
ATINGS
........................................................................................... 33
T
ABLE
19: P
OWER
AND
C
URRENT
DC E
LECTRICAL
C
HARACTERISTICS
............................................................................................ 33
T
ABLE
20: LVDS/D
IFFERENTIAL
LVPECL I
NPUT
L
OGIC
S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
................................................ 34
F
IGURE
19. LVDS/D
IFFERENTIAL
LVPECL V
OLTAGE
P
ARAMETER
C
ONVENTION
............................................................................. 35
T
ABLE
21: LVDS O
UTPUT
L
OGIC
S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
................................................................................. 36
T
ABLE
22: D
IFFERENTIAL
LVPECL O
UTPUT
L
OGIC
S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
....................................................... 36
T
ABLE
23: LVTTL/LVCMOS S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
....................................................................................... 36
T
ABLE
24: O
RDERING
I
NFORMATION
............................................................................................................................................... 37
PACKAGE DIMENSIONS ................................................................................................ 37
T
ABLE
25: R
EVISION
H
ISTORY
........................................................................................................................................................ 38
XRT91L34
6
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
PIN DESCRIPTIONS
HARDWARE CONTROL
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RESET LVTTL,
LVCMOS
I 46 Master Reset Input
Active "Low." When this pin is pulled "Low", the internal state
machines and registers are set to their default state.
"Low" = Master Hardware Reset
"High" = Normal Operation
This pin is provided with an internal pull-up.
TEST LVTTL,
LVCMOS
I 45 Test Input
Active "High." When this pin is pulled "High", the 91L34 internal
state machines will enter into a factory test mode.
"Low" = Normal Operation
"High" = Factory Test Diagnostic Mode
N
OTE
: This pin should be pulled Low for normal operation.
This pin is provided with an internal pull-down.
DATA0RATE[1:0] LVTTL,
LVCMOS
I 115, 116 Data Rate Selection
Selects SONET/SDH reception speed rate for each of the four
channels independently according to the logic below.
N
OTE
: These pins have no function in Host Mode.
These pins are provided with internal pull-down.
DATA1RATE[1:0] LVTTL,
LVCMOS
I 113, 114
DATA2RATE[1:0] LVTTL,
LVCMOS
I 50, 49
DATA3RATE[1:0] LVTTL,
LVCMOS
I 48, 47
DATA
N
RATE[1:0] D
ATA
R
ATE
0 0 STS-1/STM-0
51.84 Mbps
0 1 STS-3/STM-1
155.52 Mbps
1 0 STS-12/STM-4
622.08 Mbps
1 1 STS-12/STM-4
622.08 Mbps
XRT91L34
7
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
CDRREFSEL LVTTL,
LVCMOS
I 119 Clock and Data Recovery Unit Reference Frequency Select
Selects the Clock and Data Recovery Unit reference frequency
on REFCLKP/N pins or TTLREFCLK pin based on the table
below.
"Low" = 77.76 MHz reference clock
"High" = 19.44 MHz reference clock
N
OTE
: REFCLKP/N or TTLREFCLK input should be generated
from a crystal oscillator which has a frequency
accuracy better than 100ppm in order for the received
data rate frequency to have the necessary accuracy
required for SONET systems.
N
OTE
: This pin has no function in Host Mode.
This pin is provided with an internal pull-down.
OUTCFG LVTTL,
LVCMOS
I 44 Output Configuration
Globally selects recovered clock and data outputs to be LVDS
or Differential LVPECL on all four channels based on table
below.
"Low" = LVDS Standard Output
"High" = Differential LVPECL Standard Output
This pin is provided with an internal pull-down.
CDRDIS0
CDRDIS1
CDRDIS2
CDRDIS3
LVTTL,
LVCMOS
I 107
106
56
55
Clock and Data Recovery Unit Disable
Active "High." Disables internal Clock and Data Recovery unit
for respective channel. This enables lower power operation
when channel is unused.
"Low" = Internal CDR unit is Enabled
"High" = Internal CDR unit is Disabled
N
OTE
: These pins have no function in Host Mode.
These pins are provided with internal pull-down.
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
CDRREFSEL REFCLKP/N
OR
TTLREFCLK
F
REQUENCY
C
HANNEL
0 - 3
A
VAILABLE
D
ATA
R
ATES
077.76 MHz STS-12/STM-4 622.08 Mbps
STS-3/STM-1 155.52 Mbps
STS-1/STM-0 51.84 Mbps
119.44 MHz
OUTCFG Input
Configuration
Output
Configuration
0LVDS/
Differential LVPECL LVDS
1LVDS/
Differential LVPECL Differential LVPECL
XRT91L34
8
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
DLOSDIS
/SDI
LVTTL,
LVCMOS
I 39 DLOS (Digital Loss of Signal) Disable
Hardware Mode Disables internal DLOS monitoring and auto-
matic muting of RXDO[3:0]P/N recovered data output pins upon
DLOS detection. DLOS is declared when the incoming data
stream has no transition for more than 2.5µs. DLOS is cleared
when transitions are detected within a 128µs interval sliding
window.
"Low" = Monitor & Mute recovered data upon DLOS declaration
"High" = Disable internal DLOS monitoring
This pin is provided with an internal pull-down.
Host Mode This pin is functions as the microprocessor Serial
Data Input.
POL0
POL1
POL2
POL3
LVTTL,
LVCMOS
I 126
124
36
34
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"Low" = SDEXT is active "Low."
"High" = SDEXT is active "High."
N
OTE
: These pins have no function in Host Mode.
These pins are provided with internal pull-down.
SDEXT0
SDEXT1
SDEXT2
SDEXT3
LVTTL,
LVCMOS,
I 127
125
35
33
Signal Detect Input from Optical Module
When inactive, it will immediately declare a Loss of Signal
(LOS) condition and assert LOS register bit and mute the activ-
ity of the RXDO[3:0]P/N serial data output on the respective
channel.
"Active" = Normal Operation
"Inactive" = LOS Condition (SDEXT detects signal absence)
These pins are provided with internal pull-down.
REFCLKP
REFCLKN
LVDS,
Diff LVPECL
I 117
118
Reference Clock Input (77.76 MHz or 19.44 MHz)
This differential reference clock input will accept either a 77.76
MHz or a 19.44 MHz LVDS/Differential LVPECL clock source.
Pin CDRREFSEL determines the value used as the reference.
See Pin CDRREFSEL for more details. REFCLKP/N inputs are
internally biased to 1.2V via 15k resistance. These pins are
equipped with a 100 line-to-line internal termination.
N
OTE
: In the event that TTLREFCLK LVTTL/LVCMOS input is
used instead of these differential inputs for clock
reference, the REFCLKP should be left unconnected
and REFCLKN should be tied to GND.
TTLREFCLK LVTTL,
LVCMOS
I 120 TTL Reference Clock Input (77.76 MHz or 19.44 MHz)
This optional single-ended clock input reference can be used
instead of the differential REFCLKP/N input. It will accept
either a 77.76 MHz or a 19.44 MHz LVTTL clock source. Pin
CDRREFSEL determines the value used as the reference. See
Pin CDRREFSEL for more details.
N
OTE
: In the event that REFCLKP/N differential inputs are
used instead of this LVTTL/LVCMOS input for clock
reference, the TTLREFCLK should be tied to ground.
This pin is provided with an internal pull-down.
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
XRT91L34
9
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
RECEIVER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RXDI0P
RXDI0N
RXDI1P
RXDI1N
RXDI2P
RXDI2N
RXDI3P
RXDI3N
LVDS,
Diff LVPECL
I 3
4
11
12
22
21
30
29
Receive Serial Data Input
The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps
STS-1/STM-0 is applied to these differential input pins. These
pins accept LVDS or Differential LVPECL input standard.
These pins are internally biased to 1.2V via 15k resistance
and are equipped with a 100 line-to-line internal termination.
RXDO0P
RXDO0N
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
LVDS,
Diff LVPECL
O 94
93
86
85
75
76
67
68
Recovered Serial Data Output
622.08 Mbps STS-12/STM-4 / 155.52 Mbps STS-3/STM-1 /
51.84 Mbps STS-1/STM-0 differential recovered serial data out-
put that is updated simultaneously on the falling edge of the
corresponding channel RXCLKO output. User selectable LVDS
standard or Differential LVPECL standard output based on
OUTCFG pin state.
RXCLKO0P
RXCLKO0N
RXCLKO1P
RXCLKO1N
RXCLKO2P
RXCLKO2N
RXCLKO3P
RXCLKO3N
LVDS,
Diff LVPECL
O 90
89
82
81
79
80
71
72
Recovered Clock Output
(622.08 MHz/ 155.52 MHz/ 51.84 MHz)
622.08 MHz STS-12/STM-4 / 155.52 MHz STS-3/STM-1 /
51.84 MHz STS-1/STM-0 differential clock output for the corre-
sponding recovered data output RXDO[0:3]P/N. The recovered
serial data output port will be updated on the falling edge of
this clock. User selectable LVDS standard or Differential
LVPECL standard output based on OUTCFG pin state.
LOL0
LOL1
LOL2
LOL3
LVCMOS O 98
99
63
64
CDR LOL Detect Output
This pin is used to monitor the lock condition of the PLL in the
clock and data recovery unit of each channel.
"Low" = CDR Locked
"High" = CDR Out of Lock
CAP0P
CAP0N
Analog - 109
108
CDR Non-polarized External Loop Filter Capacitors
Mode of Operation:
1. STS12/STM4: CAP[0:3]P/N = 0.47µF ± 10% tolerance
2. STS3/STM1: CAP[0:3]P/N = 0.47µF ± 10% tolerance
3. STS1/STM0: CAP[0:3]P/N = 1.0µF ± 10% tolerance
Use type X7R or X5R for improved stability over temperature.
(Isolate from noise and place close to pin)
CAP1P
CAP1N
Analog - 103
102
CAP2P
CAP2N
Analog - 59
60
CAP3P
CAP3N
Analog - 53
54
XRT91L34
10
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
POWER AND GROUND
N
AME
T
YPE
P
IN
D
ESCRIPTION
AVDD1.8 PWR 42, 57, 58, 104, 105,
123 1.8V Analog Core Power Supply
AVDD1.8 should be isolated from DVDD1.8 and 3.3V VDD_IO
power supplies. For best results, use a ferrite bead along with an
internal power plane separation. The AVDD1.8 power supply pins
should have bypass capacitors to the nearest ground.
DVDD1.8 PWR 51, 112 1.8V Digital Core Power Supply
DVDD1.8 should be isolated from AVDD1.8 and 3.3V VDD_IO
power supplies. For best results, use an internal power plane
separation. The DVDD1.8 power supply pins should have bypass
capacitors to the nearest ground.
VDD_IO PWR 5, 6, 13, 14, 19, 20, 27,
28, 65, 66, 73, 74, 87,
88, 95, 96
3.3V Input/Output Bus Power Supply
These pins require a 3.3V potential voltage for properly biasing
the Differential LVDS/Differential LVPECL and LVCMOS/LVTTL
input and output pins.
VDD_IO should be isolated from the AVDD1.8 and DVDD1.8
Core power supplies. For best results, use a ferrite bead along
with an internal power plane separation. The VDD_IO power sup-
ply pins should have bypass capacitors to the nearest ground.
GND_IO GND 7, 8, 15, 16, 17, 18, 25,
26, 69, 70, 77, 78, 83,
84, 91, 92
Ground for 3.3V VDD Input/Output Power Supplies
It is recommended that all ground pins of this device be tied
together.
GND GND 43, 52, 61, 62, 100, 101,
110, 111, 121 Power Supply and Thermal Ground
It is recommended that all ground pins of this device be tied
together.
NC 1, 2, 9, 10, 23, 24, 31,
32, 97, 128 No Connect
XRT91L34
11
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
SERIAL MICROPROCESSOR INTERFACE
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
HOST/HW LVTTL,
LVCMOS
I 122 Host or Hardware Mode Select Input
The XRT91L34 offers two modes of operation for interfacing to the
device. The Host mode uses a serial microprocessor interface for
programming individual registers. The Hardware mode is controlled
by the state of the hardware pins set by the user. When left uncon-
nected, by default, the device is configured in the Hardware mode.
"Low" = Hardware Mode
"High" = Host Mode
This pin is provided with an internal pull-down.
CS LVTTL,
LVCMOS
I 38 Chip Select Input (Host Mode)
Active "Low" signal. This signal enables the serial microprocessor
interface by pulling chip select "Low". The serial microprocessor is
disabled when the chip select signal returns "High".
N
OTES
:
1. The serial microprocessor interface does not support burst
mode. Chip Select must be de-asserted after each
operation cycle.
2. Chip Select is only active in Host Mode.
This pin is provided with an internal pull-up.
SCLK LVTTL,
LVCMOS
I 37 Serial Clock Input (Host Mode Only)
Once CS is pulled "Low", the serial microprocessor interface
requires 16 clock cycles for a complete Read or Write operation.
Serial Clock Input is only active in Host Mode.
This pin is provided with an internal pull-down.
DLOSDIS
/SDI
LVTTL,
LVCMOS
I 39 Serial Data Input (Host Mode Only)
When CS is pulled "Low", the serial data input is sampled on the ris-
ing edge of SCLK.
Serial Data Input is only active in Host Mode.
This pin is provided with an internal pull-down.
Hardware Mode This pin is functions as the DLOSDIS control pin.
SDO LVCMOS O 40 Serial Data Output (Host Mode Only)
If a Read function is initiated, the serial data output is updated on
the falling edge of SCLK8 through SCLK15, with the LSB (D0)
updated first. This enables the data to be sampled on the rising
edge of SCLK9 through SCLK16.
Serial Data Output is only active in Host Mode.
INT LVCMOS O 41 Interrupt Output (Host Mode Only)
Active "Low" signal. This signal is asserted "Low" when a change in
alarm status occurs. Once the status registers have been read, the
interrupt pin will return "High".
Interrupt Output is only active in Host Mode.
N
OTE
: This open-drain output pin requires an external pull-up
resistor.
XRT91L34
12
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
1.0 FUNCTIONAL DESCRIPTION
The XRT91L34 Quad Channel CDR is designed to operate with a multichannel SONET Framer/ASIC device
and provide a high-speed serial clock and data recovery interface to optical networks. The CDR receives
differential NRZ serial bit stream running at STS-12/STM-4 or STS-3/STM-1 or STS-1/STM-0, and outputs
recovered serial clock and data via differential LVDS/LVPECL drivers. It implements four independently
configurable receive clock and data recovery (CDR) units and a LOL and LOS detection circuit (Host Mode
Only) for each channel. The CDR is used to provide the front end component of SONET equipment.
1.1 Hardware Mode vs. Host Mode
Functional control of the receiver can be configured by using either Host mode or Hardware mode. Hardware
mode is selected by pulling HOST/HW "Low" or leaving this pin unconnected. The receiver functionality is then
controlled by the hardware pins described in the Hardware Pin Descriptions. Host mode is selected by pulling
HOST/HW "High". In Host mode the functionality is controlled by programming internal R/W registers using the
Serial Microprocessor interface. Host mode offers functions not available in Hardware mode, such as Loss of
Signal Monitoring, Interrupt Generation and Disabling of the recovered clock output.
1.2 STS-12/STM-4 and STS-3/STM-1 and STS-1/STM-0 Mode of Operation
The data rate of each receiver channel can be configured by using the appropriate signal level on the
DATAnRATE1:0] pins (where n = channel 0, 1, 2, or 3) as shown in Table 1.
N
OTE
: n denotes channel number.
T
ABLE
1: C
HANNEL
D
ATA
R
ATE
S
ELECTION
DATA
N
RATE[1:0] D
ATA
RATE
S
ELECTED
FOR
CHANNEL
N
0 0 STS-1/STM-0
51.84 Mbps
0 1 STS-3/STM-1
155.52 Mbps
1 0 STS-12/STM-4
622.08 Mbps
1 1 STS-12/STM-4
622.08 Mbps
XRT91L34
13
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
1.3 Reference Clock Input
The XRT91L34 can accept either a 19.44 MHz or 77.76 MHz Differential clock input at REFCLKP/N or a
Single-Ended LVTTL clock input at TTLREFCLK. The REFCLKP/N or TTLREFCLK should be generated from
a source which has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to
have the necessary accuracy required for SONET systems. The reference clock can be provided with one of
two frequencies chosen by CDRREFSEL. The reference frequency options for the XRT91L34 are listed in
Table 2. Figure 3 illustrate the reference clock design options.
T
ABLE
2: CDR R
EFERENCE
F
REQUENCY
O
PTIONS
(LVDS/ D
IFF
LVPECL
OR
S
INGLE
-E
NDED
LVTTL/LVCMOS)
CDRREFSEL REFCLKP/N
OR
TTLREFCLK
FREQUENCY
C
HANNEL
0 - 3
A
VAILABLE
D
ATA
R
ATES
077.76 MHz STS-1/STM-0 51.84 Mbps
STS-3/STM-1 155.52 Mbps
STS-12/STM-4 622.08 Mbps
119.44 MHz
F
IGURE
3. R
EFERENCE
C
LOCK
D
ESIGN
O
PTIONS
Single-Ended LVTTL/LVCMOS
Reference Clock Option
Differential LVPECL or LVDS
Reference Clock Option
XRT91L34
130 Ohm
REFCLKP and REFCLKN pins
internally biased and terminated with
100 Ohm line-to-line
Tie unused TTLREFCLK
input pin to GND
Differential Clock
Source
77.76/19.44 MHz
TTLREFCLK
XRT91L34
Leave REFCLKP unconnected
and
tie REFCLKN pin to GND
Single Ended
Clock Source
77.76/19.44 MHz
Resistors for LVPECL
Remove for LVDS
REFCLKP
REFCLKN
VBB
1.2
100
Internal
REFCLK
VBB
1.2
100
Internal
REFCLK
REFCLKP
REFCLKN
TTLREFCLK
RXDIZN RXDISN
XRT91L34
14
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
2.0 RECEIVE SECTION
The receive section of XRT91L34 includes four differential input buffers RXDI[3:0]P/N, followed by clock and
data recovery units (CDR) and recovered serial data and clock differential output drivers. The receiver accepts
the high speed Non-Return to Zero (NRZ) serial data at 622.08/155.52/51.84 Mbps through the input interfaces
RXDI[3:0]P/N. The clock and data recovery unit recovers the high-speed receive clock from the incoming data
stream. The recovered serial data is presented to the RXDO[3:0]P/N differential output driver interface. The
high-speed recovered clock RXCLKO[3:0]P/N, is used to synchronize the transfer of the RXDO[3:0]P/N data
with the receive portion of a framer/mapper device. The recovered data RXDO[3:0]P/N and clock
RXCLKO[3:0]P/N differential output driver interfaces are designed for ultimate flexibility by supporting either
LVDS or Differential LVPECL protocol level. Upon initialization or loss of signal or loss of lock, the external
reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock recovery phase-locked loop for
proper operation. The included CDR blocks in the XRT91L34 can be individually disabled by asserting the
CDRDIS[3:0] pins to permit the flexibility of powering down unused channels.
2.1 Receive Serial Input
The receive serial inputs are applied to RXDI[3:0]P/N. The XRT91L34 includes internal termination, this has
the advantage of reducing the number of external board components. The XRT91L34 terminates the receive
inputs using 100 line-to-line method of termination. Differential LVPECL operation of receive inputs can be
supported, provided each optical module Differential LVPECL output pin must have a 130 DC current path
resistor to GND whether internally or externally. A simplified LVDS/Differential LVPECL DC coupling block
diagram is shown in Figure 4.
N
OTE
: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.
AC or DC coupling is largely specific to system design and optical module of choice.
F
IGURE
4. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
USING
LVDS/D
IFF
LVPECL DC
COUPLING
INTERNAL
TERM
RXDIOF A RXDION A HXD|1 P RXDI1N HXDIZP RXDIZN RXDIZF HXDISN
XRT91L34
15
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
The receive serial inputs can also be AC coupled to an optical module or an electrical interface. A simplified
Differential LVPECL AC coupling using external passive components block diagram is shown in Figure 5.
N
OTE
: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.
2.2 Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the
reference clock from REFCLKP/N or TTLREFCLK to train and monitor its clock recovery PLL. Upon startup,
the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock onto the
incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch to the
local reference clock, declare a Loss of Lock and output a high level signal on the LOL output pin. Whenever a
Loss of Lock (LOL) or a Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock
(based on the local reference). When the SDEXT becomes active and internal DLOS is cleared and the
recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source, the
clock recovery PLL will switch back to the incoming receive serial data stream. Table 3 specifies the Clock and
Data Recovery Unit performance characteristics.
F
IGURE
5. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
USING
D
IFF
LVPECL AC
COUPLING
INTERNAL
TERMINATION
Optical Module
RXDI0P
RXDI0N
Optical Fiber
Install DC current path resistors
as close to Optical Module
LVPECL output driver pins
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
RXDI1P
RXDI1N
RXDI2P
RXDI2N
RXDI3P
RXDI3N
Optical Module
Optical Fiber
Optical Module
Optical Fiber
Optical Module
Optical Fiber
Channel 0
Channel 1
Channel 2
Channel 3
D
IFF
LVPECL A/C Coupling using
External Passive Components
130 x 8
100
100
100
100
VBB
1.2
VBB
1.2
VBB
1.2
VBB
1.2
Internal 100 Ohm line-to-line
termination active on
RXDI[3:0]P and RXDI[3:0]N pins
XRT91L34
16
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
Jitter specification is defined using a 12kHz to 0.4/1.3/5MHz LP-HP single-pole filter.
1
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
rms
).
2
Required to meet SONET output frequency stability requirements.
2.2.1 Internal Clock and Data Recovery Disable
Optionally, each of the four internal CDR unit can be disabled and powered down when the channel is not in
use. Asserting the CDRDISn pin (where n = channel 0, 1, 2, or 3 ) "High" in Hardware Mode or setting
CDRDISn bit (where n = channel 0, 1, 2, or 3 ) in Host Mode, disables the internal Clock and Data Recovery
unit for that particular channel.
2.3 External Receive Loop Filter Capacitors
For STS12/STM4 and STS3/STM1 operation, use 0.47µF (or greater) non-polarized external loop filter
capacitors to achieve the required receiver jitter performance for each of the channels. For STS1/STM0
operation, use a minimum of 1.0µF non-polarized capacitors. If all 3 data rates STS12/STS3/STS1 are
required in an application, then use 1uF loop filter capacitors. They must be well isolated to prohibit noise
entering the CDR block and should be placed as close to the pins as possible. Figure 6 shows the pin
connections and external loop filter components. These four non-polarized capacitors should be of +/- 10%
tolerance. Use type X7R or X5R capacitors for improved stability over temperature.
T
ABLE
3: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
40 60 %
REF
TOL
Reference clock frequency tolerance
2
-100 +100 ppm
TOL
JIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.3 0.4 UI
OCLK
DUTY
Clock output duty cycle
45 55 %
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
CAP1NCAP1P
0.47uF
non-polarized
CAP3NCAP3P
0.47uF
non-polarized
CAP0NCAP0P
0.47uF
non-polarized
Channel 0 Loop Filter
External Capacitor
pin 108
pin 109 pin 103 pin 102
Channel 1 Loop Filter
External Capacitor
CAP2NCAP2P
0.47uF
non-polarized
Channel 2 Loop Filter
External Capacitorpin 60
pin 59 pin 53 Pin 54
Channel 3 Loop Filter
External Capacitor
Use 1.
.
..
.
0uF non-polarized
capacitors for
STS1/STM0 Operation
XRT91L34
17
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
2.4 Internal Digital Loss of Signal and External Signal Detection
XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection
(SDEXT) for detecting and determining received signal integrity. The internal DLOS circuit monitors the
incoming data stream. If the incoming data stream has no transition for more than 2.5µs, Loss of Signal is
declared. This LOS condition will be cleared when the circuit detects transitions in a 128µs interval sliding
window. Pulling the DLOSDIS pin signal to a high level in hardware mode or setting DLOSDIS bit in host mode
will disable the internal DLOS detection circuit to permit the framer/mapper interface to determine the Loss of
Signal declaration and clearance criteria for specific applications. The external Signal Detect function is
supported by the SDEXT input. An LVCMOS/LVTTL signal comes from the optical module through an output
usually called SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The
SDEXT and POL inputs are Exclusive OR’ed to determine external Loss of Signal (LOS) condition. In the event
that internal DLOS is detected or an external SDEXT input indicates signal absence, the recovered serial data
output will be forced to a logic state "0," and the LOS status register is set whenever the host mode serial
microprocessor interface is active. This acts as a receive data mute upon LOS function to prevent data
chattering and to prevent random noise from being misinterpreted as valid incoming data. Figure 7 shows the
Loss of Signal Detection logic circuit. Table 4 specifies LOS declaration polarity settings.
F
IGURE
7. L
OSS
OF
S
IGNAL
D
ECLARATION
C
IRCUIT
T
ABLE
4: E
XTERNAL
LOS D
ECLARATION
P
OLARITY
S
ETTING
SDEXT POL I
NTERNAL
S
IGNAL
D
ETECT
LOS
BIT
STATE
(H
OST
MODE
O
NLY
)RXDO[3:0]P/N
0 0 Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module. Low Normal
Operation
0 1 Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
High
LOS declared Muted
1 0 Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
High
LOS declared Muted
1 1 Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module. Low Normal
Operation
DLOSDIS
(Internal) DLOS Detect
(External) SDEXT
LOS Declaration
POL and
Recovered Data Mute
>> >> >> >> § §
XRT91L34
18
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
2.5 Multichannel Recovered Output Interface
The recovered data RXDO[3:0]P/N differential output drivers along with the recovered clock RXCLKO[3:0]P/N
differential output drivers can be configured for LVDS or Differential LVPECL standard operation. In addition,
Host Mode operation permits each of the channelized recovered clock output to be independently disabled
such as in repeater applications to save power.
F
IGURE
8. M
ULTICHANNEL
R
ECOVERED
O
UTPUT
I
NTERFACE
B
LOCK
OUTCFG = 0
RXDO0P
RXDO0N
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
Channel 0
Channel 1
Channel 2
Channel 3
LVDS Operation
100
100
100
100
Internal or External 100 Ohm
line-to-line termination required on
RXDO[3:0]P and RXDO[3:0]N pins
on the SONET Framer/ASIC end
SONET Framer/
ASIC
RXCLKO[3:0]P and
RXCLKO[3:0]N
Clock Output pins
terminated similarly
RXDO0P
RXDO0N
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
Channel 0
Channel 1
Channel 2
Channel 3
LVPECL Operation
SONET Framer/
ASIC
82 x 8
Install terminators as close to
SONET Framer/ ASIC pins
120 x 8
VDD
IO
RXCLKO[3:0]P and
RXCLKO[3:0]N
Clock Output pins
terminated similarly
OUTCFG = 1
XRT91L34
19
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
2.6 Differential Recovered Data Output Timing
The differential recovered data and clock outputs operating at the STS-12/STM-4 or STS-3/STM-1 or STS-1/
STM-0 datarates will adhere to the data valid output timing shown in Figure 9 ,Table 5, Table 6, and Table 7.
F
IGURE
9. D
IFFERENTIAL
R
ECOVERED
O
UTPUT
T
IMING
T
ABLE
5: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
)
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
RXCLKO
Recovered high-speed output clock period 1.608 ns
t
RXDO_VALID
Time the data is valid on RXDO[3:0]P/N before and after the
rising edge of RXCLKO[3:0]P/N 0.5 ns
T
ABLE
6: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
)
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
RXCLKO
Recovered high-speed output clock period 6.43 ns
t
RXDO_VALID
Time the data is valid on RXDO[3:0]P/N before and after the
rising edge of RXCLKO[3:0]P/N 2.8 ns
T
ABLE
7: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-1/STM-0 O
PERATION
)
S
YMBOL
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
t
RXCLKO
Recovered high-speed output clock period 19.29 ns
t
RXDO_VALID
Time the data is valid on RXDO[3:0]P/N before and after the
rising edge of RXCLKO[3:0]P/N 8.3 ns
RXCLKO[3:0]P/N
RXDO[3:0]P/N
t
RXDO_VALID
t
RXCLKO
D1 D2 D4D3 D5
XRT91L34
20
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
3.0 JITTER PERFORMANCE
3.1 SONET Jitter Requirements
SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of
each of these types of jitter are given below.
3.1.1 Rx Jitter Tolerance:
OC-1/STM-0, OC-3/STM-1, and OC-12/STM-4 category II SONET interfaces should tolerate, the input jitter
applied according to the mask of Figure 10, with the corresponding parameters specified in the figure.
F
IGURE
10. GR-253/G.783 J
ITTER
T
OLERANCE
M
ASK
F
IGURE
11. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
51.84 M
BPS
STS-1/STM-0
OC-N STM-X LEVEL
1
3
12
F0 (HZ)
10
10
10
F1 (HZ)
30
30
30
F2 (HZ)
300
300
300
F3 (HZ)
2K
6.5K
25K
F4 (HZ)
20K
65K
250K
A1 (UIPP)
0.15
0.15
0.15
A2 (UIPP)
1.5
1.5
1.5
A3 (UIPP)
15
15
15
Input
Jitter
Amplitude
(UI
pp
)
A
3
A
2
A
1
f
0
f
1
f
2
f
3
f
4
slope= -20dB/decade
slope= -20dB/decade
Jitter Frequency (Hz)
3
12
10
10
10
30
30
30
300
300
300
2K
6.5K
25K
20K
65K
250K
0.15
0.15
0.15
1.5
1.5
1.5
15
15
15
OC1/STS1 STM0
OC3/STS3 STM1
OC12/STS12 STM4
Jitter Tolerance, GR-253, OC-1 (51 Mbps)
0.01
0.10
1.00
10.00
100.00
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Amplitude (UI)
Mask Jitter Tolerance
XRT91L34
21
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
F
IGURE
12. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
155.52 M
BPS
STS-3/STM-1
F
IGURE
13. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
622.08 M
BPS
STS-12/STM-4
Jitter Tolerance, GR-253, OC-3 (155 Mbps)
0.01
0.10
1.00
10.00
100.00
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7
Frequency (Hz)
Amplitude (UI)
Jitter Tolerance Mask
Jitter Tolerance, GR-253, OC-12 (622 M bps)
0.01
0.10
1.00
10.00
100.00
1000.00
1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7
Frequency (Hz)
Amplitude (UI)
Jitter Tolerance Mask
XRT91L34
22
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
3.1.2 Rx Jitter Transfer
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency. It displays the ability of the component unit to attenuate jitter at the specified injected jitter
frequencies. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the
highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a low
bandwidth loop.
The XRT91L34 meets the latest jitter transfer characteristics as shown in the Figure 14, Figure 15, and
Figure 16. The XRT91L34 complies with STS-12/3/1 and STM-4/1/0 jitter transfer masks set forth by Bellcore
GR-253 Core section 5.6.2.1 and ITUT G.783 section 15.1.3 as defined in G.825.
F
IGURE
14. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
51.84 M
BPS
STS-1/STM-0
F
IGURE
15. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
155.52 M
BPS
STS-3/STM-1
Jitter Transfer, GR253H, OC-1 (52Mbps)
-30
-25
-20
-15
-10
-5
0
5
1E+1 1E+2 1E+3 1E+4 1E+5 1E+6
Frequuency (Hz)
Gain (dB)
Mask Jitter Transfer
Jitter Transfer, GR253H, OC-3 (155 Mbps)
-30
-25
-20
-15
-10
-5
0
5
1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7
Frequuency (Hz)
Gain (dB)
Mask Jitter Transfer
Jitter Transler, GR253H, 00-12 (622 Mbps)
XRT91L34
23
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
F
IGURE
16. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
622.08 M
BPS
STS-12/STM-4
Jitter Transfer, GR253H, OC-12 (622 Mbps)
-30
-25
-20
-15
-10
-5
0
5
1E+1 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7
Frequuency (Hz)
Gain (dB)
Mask Jitter Transfer
b—> »D D7 —D— D— 4» 4» €14? W 4{|||\|||||\||\||>7 —C|:|:EI:I:EI:I— NOT
XRT91L34
24
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK
The Serial Microprocessor Interface uses a standard 3-pin serial port with CS, SCLK, and SDI for programming
the device. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers,
monitor the device via an interrupt pin, and reset the device to its default configuration by pulling reset "Low"
for more than 10ns. A simplified block diagram of the Serial Microprocessor Interface is shown in Figure 17.
4.1 S
ERIAL
T
IMING
I
NFORMATION
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
Interface samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device
until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor Interface is
shown in Figure 18.
N
OTE
: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active
"Low") must be de-asserted at the end of each write or read operation.
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
F
IGURE
18. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
Shift Register
Data out
Register
Bank
Address
bus Data
bus
Status bits and error
Flags from CDRs Controls to
CDRs
RESET
CS INT
SDI
SCLK
SDO
CS
SDI
SCLK
SDO
1210
9
8
7654
311 16
15
13 1412
R/W A0 A1 A2 A3 A4 A5 X D0 D1 D7D6D5D4D3D2
D0 D1 D7D6D5D4D3D2
High-Z High-Z
25nS 50nS
XRT91L34
25
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
4.2 16-B
IT
S
ERIAL
D
ATA
I
NPUT
D
ESCRITPTION
The serial data input is sampled on the rising edge of SCLK. For read operations, the SDO signal is updated
on the falling edge of SCLK. The serial data must be applied to the serial port LSB first. The 16 bits of serial
data are described below.
4.2.1 R/W (SCLK1)
The first serial bit applied to the device SDI pin determines whether a Read or Write operation is desired. If the
R/W bit is set to “0”, the serial port is configured for a Write operation. If the R/W bit is set to “1”, the serial port
is configured for a Read operation.
4.2.2 A[5:0] (SCLK2 - SCLK7)
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0
(LSB) must be sent to the SDI pin first followed by A1 and so forth until all 6 address bits have been sampled
by SCLK.
4.2.3 X (Dummy Bit SCLK8)
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data
if the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold
either “0” or “1” during both Read and Write operations.
4.2.4 D[7:0] (SCLK9 - SCLK16)
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the ad-
dress bits. D0 (LSB) must be sent to the SDI pin first followed by D1 and so forth until all 8 data bits have been
sampled by SCLK. Once 16 SCLK cycles have been complete, the data is held until CS is pulled “High”
whereby, the serial port latches the data into the selected internal register.
4.3 8-B
IT
S
ERIAL
D
ATA
O
UTPUT
D
ESCRIPTION
When R/W is set to “1” (Read operation) the serial data output is updated on the falling edge of SCLK8 -
SCLK16, D0 (LSB) is provided at the SDO pin on the falling edge of SCLK8, followed by D1 and so forth until
all 8 data bits have been updated after which the SDO output pin returns to a high impedance state until the
next read operation.
XRT91L34
26
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
5.0 REGISTER MAP AND BIT DESCRIPTIONS
The XRT91L34 consists of 6 Common Registers including the Device ID and Revision ID registers and 12
channelized registers. Table 8 below presents the overall Register Map.
T
ABLE
8: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
M
AP
REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0
Control Registers (0x00 - 0x22)
0 0x00 R/W Reserved Reserved Reserved DLOSDIS Reserved MINT_EN CDRREFSEL SWRST
1 0x01 RO Reserved Reserved Reserved Reserved INTS3 INTS2 INTS1 INTS0
2 0x02 RO
Device ID MSB (See Bit Description)
3 0x03 RO
Device ID LSB (See Bit Description)
4 0x04 RO
Revision ID MSB (Register value is 0x00)
5 0x05 RO
Revision ID LSB (See Bit Description)
6 0x06 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
7 0x07 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
CHANNEL 0
8 0x08 R/W Reserved Reserved Reserved Reserved Reserved RCLKDIS0 CDRDIS0 POL0
9 0x09 R/W Reserved Reserved DATA0RATE1 DATA0RATE0 Reserved Reserved LOL0_IE LOS0_IE
10 0x0A RO
RUR Reserved Reserved LOL0 LOS0 Reserved Reserved LOL0_IS LOS0_IS
0x0B - 0x0F RO
Reserved
CHANNEL 1
16 0x10 R/W Reserved Reserved Reserved Reserved Reserved RCLKDIS1 CDRDIS1 POL1
17 0x11 R/W Reserved Reserved DATA1RATE1 DATA1RATE0 Reserved Reserved LOL1_IE LOS1_IE
18 0x12 RO
RUR Reserved Reserved LOL1 LOS1 Reserved Reserved LOL1_IS LOS1_IS
0x13 - 0x17 RO
Reserved
CHANNEL 2
24 0x18 R/W Reserved Reserved Reserved Reserved Reserved RCLKDIS2 CDRDIS2 POL2
25 0x19 R/W Reserved Reserved DATA2RATE1 DATA2RATE0 Reserved Reserved LOL2_IE LOS2_IE
26 0x1A RO
RUR Reserved Reserved LOL2 LOS2 Reserved Reserved LOL2_IS LOS2_IS
0x1B - 0x1F RO
Reserved
CHANNEL 3
32 0x20 R/W Reserved Reserved Reserved Reserved Reserved RCLKDIS3 CDRDIS3 POL3
33 0x21 R/W Reserved Reserved DATA3RATE1 DATA3RATE0 Reserved Reserved LOL3_IE LOS3_IE
34 0x22 RO
RUR Reserved Reserved LOL3 LOS3 Reserved Reserved LOL3_IS LOS3_IS
XRT91L34
27
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
COMMON CONTROL REGISTERS
T
ABLE
9: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
00
B
IT
D
ESCRIPTION
GLOBAL CONTROL REGISTER (0X00)
BIT NAME FUNCTION
Regis-
ter
Type
Default
Value
(HW Reset)
D7 Reserved This Register Bit is Not Used RO 0
D6 Reserved This Register Bit is Not Used RO 0
D5 Reserved This Register Bit is Not Used RO 0
D4 DLOSDIS DLOS (Digital Loss of Signal) Disable
This global bit is used to disable the channelized internal DLOS
monitoring and automatic muting of RXDO[3:0]P/N recovered data
output pins upon DLOS detection.
"0" = Monitor & Mute recovered data upon LOS declaration
"1" = Disable internal DLOS monitoring
R/W 0
D3 Reserved This Register Bit is Not Used RO 0
D2 MINT_EN Master Interrupt Enable
"0" = Disables Interrupt generation
"1" = Enables Interrupt generation
R/W 0
D1 CDRREFSEL Clock and Data Recovery Unit Reference Frequency Select
This bit is used to select the clock input reference.
"0" = 77.76 MHz reference frequency support
"1" = 19.44 MHz reference frequency support
R/W 0
D0 SWRST Software Reset
A "0" to "1" transition will asynchronously reset the device and all
register bit settings to their default state. This bit will automatically
reset itself to "0". User does not have to write "0" to this bit to resume
normal operation.
"0" = Normal Operation
"1" = Resets all registers to default values
R/W 0
XRT91L34
28
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
T
ABLE
10: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
01
B
IT
D
ESCRIPTION
CHANNEL INTERRUPT STATUS REGISTER (0X01)
BIT NAME FUNCTION
Regis-
ter
Type
Default
Value
(HW Reset)
D7 Reserved This Register Bit is Not Used RO 0
D6 Reserved This Register Bit is Not Used RO 0
D5 Reserved This Register Bit is Not Used RO 0
D4 Reserved This Register Bit is Not Used RO 0
D3 INTS3 Channel 3 Interrupt Status
This bit indicates an interrupt occuring in Channel 3.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
D2 INTS2 Channel 2 Interrupt Status
This bit indicates an interrupt occuring in Channel 2.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
D1 INTS1 Channel 1 Interrupt Status
This bit indicates an interrupt occuring in Channel 1.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
D0 INTS0 Channel 0 Interrupt Status
This bit indicates an interrupt occuring in Channel 0.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
T
ABLE
11: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
02 B
IT
D
ESCRIPTION
DEVICE "ID" REGISTER (0X02)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Device "ID"
MSB
The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the
revision "ID", the device "ID" is used to enable software to identify
the silicon adding flexibility for system control and debug.
RO 1
0
0
0
0
1
0
0
XRT91L34
29
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
T
ABLE
12: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
03 B
IT
D
ESCRIPTION
DEVICE "ID" REGISTER (0X03)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Device "ID"
LSB
The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the
revision "ID", the device "ID" is used to enable software to identify
the silicon adding flexibility for system control and debug.
RO 0
0
0
0
0
1
0
1
T
ABLE
13: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
04 B
IT
D
ESCRIPTION
REVISION "ID" REGISTER (0X04)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Revision
"ID"
MSB
The revision "ID" of the XRT91L34 CDR is used to enable software
to identify which revision of silicon is currently being tested. This
MSB revision "ID" register will always contain the value 0x00h.
RO 0
0
0
0
0
0
0
0
T
ABLE
14: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
05 B
IT
D
ESCRIPTION
REVISION "ID" REGISTER (0X05)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Revision
"ID"
LSB
The revision "ID" of the XRT91L34 CDR is used to enable software
to identify which revision of silicon is currently being tested. The
revision "ID" for the first revision of silicon (Revision A) will be
0x01h.
RO This byte
shows the
revision of
the device.
XRT91L34
30
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
CHANNELIZED REGISTERS
N
OTE
: n denotes channel number.
T
ABLE
15: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
08, 0
X
10, 0
X
18, 0
X
20 B
IT
D
ESCRIPTION
CHANNEL CONTROL REGISTER (CH0 = 0X08, CH1 = 0X10, CH2 = 0X18, CH3 = 0X20)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7 Reserved This Register Bit is Not Used RO 0
D6 Reserved This Register Bit is Not Used RO 0
D5 Reserved This Register Bit is Not Used RO 0
D4 Reserved This Register Bit is Not Used RO 0
D3 Reserved This Register Bit is Not Used RO 0
D2 RCLKDISn Recovered Serial Clock Output Disable
This bit is used to control the activity of the 622.08/155.52/51.84
MHz differential serial clock output. Tristating RXCLKOnP/N output
reduces power consumption.
"0" = RXCLKOnP/N output Enabled
"1" = RXCLKOnP/N output Tristated
R/W 0
D1 CDRDISn Clock and Data Recovery Unit Disable
Disables Internal Clock and Data Recovery Unit.
"0" = Internal CDR Unit is Enabled
"1" = Internal CDR Unit is Disabled
R/W 0
D0 POLn Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W 0
XRT91L34
31
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
N
OTE
: n denotes channel number.
T
ABLE
16: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
09, 0
X
11, 0
X
19, 0
X
21 B
IT
D
ESCRIPTION
CONFIGURATION AND INTERRUPT ENABLE CHANNEL REGISTER (CH0 = 0X09, CH1 = 0X11, CH2 = 0X19, CH3 = 0X21)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7 Reserved This Register Bit is Not Used RO 0
D6 Reserved This Register Bit is Not Used RO 0
D5 DATAnRATE1 Data Rate Selection Bit-1 and Bit-0
These bits selects SONET/SDH reception speed rate for each of
the four channels independently according to the logic below.
R/W 0
D4 DATAnRATE0 R/W 0
D3 Reserved This Register Bit is Not Used RO 0
D2 Reserved This Register Bit is Not Used RO 0
D1 LOLn_IE Loss of Lock Interrupt Enable
"0" = Masks the LOL interrupt generation
"1" = Enables Interrupt generation
R/W 0
D0 LOSn_IE Loss of Signal Interrupt Enable
"0" = Masks the LOS interrupt generation
"1" = Enables Interrupt generation
R/W 0
DATANRATE[1:0] DATA RATE
0 0 STS-1/STM-0
51.84 Mbps
0 1 STS-3/STM-1
155.52 Mbps
1 0 STS-12/STM-4
622.08 Mbps
1 1 STS-12/STM-4
622.08 Mbps
XRT91L34
32
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
N
OTE
: n denotes channel number.
T
ABLE
17: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
0A, 0
X
12, 0
X
1A, 0
X
22 B
IT
D
ESCRIPTION
INTERRUPT STATUS CONTROL REGISTER (CH0 = 0X0A, CH1 = 0X12, CH2 = 0X1A, CH3 = 0X22)
BIT NAME FUNCTION
Register
Type Default
Value
(HW reset)
D7 Reserved This Register Bit is Not Used RO 0
D6 Reserved This Register Bit is Not Used RO 0
D5 LOLn Loss of Lock Detection
The Loss of Lock Detect is used to indicate whether the CDR PLL
is locked.
"0" = CDR Locked
"1" = CDR Out of Lock
RO 0
D4 LOSn Loss of Signal
The LOS indicates the Loss of Signal activity.
"0" = No Alarm
"1" = A LOS condition is present
RO 0
D3 Reserved This Register Bit is Not Used RO 0
D2 Reserved This Register Bit is Not Used RO 0
D1 LOLn_IS Loss of Lock Interrupt Status
An external interrupt will not occur unless the LOLn_IE interrupt
enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and
0x21 for channels 0, 1, 2, and 3 respectively.
"0" = No Change
"1" = Change in CDR Lock Status Occurred
RUR 0
D0 LOSn_IS Loss of Signal Interrupt Status
An external interrupt will not occur unless the LOSn_IE interrupt
enable bit is set in the appropriate registers 0x09, 0x11, 0x19, and
0x21 for channels 0, 1, 2, and 3 respectively.
"0" = No Change
"1" = Change in LOS Status Occurred
RUR 0
XRT91L34
33
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
6.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
N
OTE
: Stresses listed under Absolute Maximum Power and I/O ratings may be applied to devices one at a time without
causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for
extended periods will severely affect device reliability.
Air Thermal Resistance of LQFP Package.....
Θ
jA
=
25
°C/W Operating Temperature Range.................-4C t o 85°C
Case Thermal Resistance of LQFP Package.
Θ
jC
=
4
°C/W Case Temperature under bias..................-55°C to 125°C
ESD Protection (HBM)..........................................>2000V Storage Temperature ...............................-65°C to 15C
T
ABLE
18: A
BSOLUTE
M
AXIMUM
P
OWER
A
ND
I
NPUT
/O
UTPUT
R
ATINGS
SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS
VDD
1.8
1.8V Core Power Supplies -0.5 3.6 V
VDD
IO
3.3V Input/Output Power Supplies -0.5 5.5 V
LVDS DC logic signal input voltage -0.5 VDD
IO
+0.5 V
LVPECL DC logic signal input voltage -0.5 VDD
IO
+0.5 V
LVTTL/
LVCMOS
DC logic signal input voltage -0.5 VDD
IO
+0.5 V
LVDS DC logic signal output voltage -0.5 VDD
IO
+0.5 V
LVPECL DC logic signal output voltage -0.5 VDD
IO
+0.5 V
LVCMOS DC logic signal output voltage -0.5 VDD
IO
+0.5 V
LVDS Input current -200 200 mA
LVPECL Input current -200 200 mA
LVTTL/
LVCMOS
Input current -200 200 mA
T
ABLE
19: P
OWER
AND
C
URRENT
DC E
LECTRICAL
C
HARACTERISTICS
Test Conditions: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified
SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
VDD
1.8
Core Power Supply Voltage 1.710 1.8 1.890 V
VDD
IO
I/O Power Supply Voltage 3.135 3.3 3.465 V
I
DD1.8-OC1
1.8V 51.84Mbps Total Power Supply Current mA LVDS Mode
I
DD1.8-OC3
1.8V 155.52Mbps Total Power Supply Current mA LVDS Mode
I
DD1.8-OC12
1.8V 622.08Mbps Total Power Supply Current 117 mA LVDS Mode
I
DD3.3-OC1
3.3V 51.84Mbps Total Power Supply Current mA LVDS Mode
I
DD3.3-OC3
3.3V 155.52Mbps Total Power Supply Current mA LVDS Mode
XRT91L34
34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
I
DD3.3-OC12
3.3V 622.08Mbps Total Power Supply Current 50 mA LVDS Mode
I
DD3.3-OC12
3.3V 622.08Mbps Total Power Supply Current 30 mA LVDS Mode
RXCLKO dis-
abled
P
DD-OC1
Total Power Consumption mW LVDS Mode
P
DD-OC3
Total Power Consumption mW LVDS Mode
P
DD-OC12
Total Power Consumption 376 mW LVDS Mode
P
DD-OC12
Total Power Consumption 310 mW LVDS Mode
RXCLKO dis-
abled
I
DD1.8-OC1
1.8V 51.84Mbps Total Power Supply Current mA LVPECL Mode
I
DD1.8-OC3
1.8V 155.52Mbps Total Power Supply Current mA LVPECL Mode
I
DD1.8-OC12
1.8V 622.08Mbps Total Power Supply Current 117 mA LVPECL Mode
I
DD3.3-OC1
3.3V 51.84Mbps Total Power Supply Current mA LVPECL Mode
I
DD3.3-OC3
3.3V 155.52Mbps Total Power Supply Current mA LVPECL Mode
I
DD3.3-OC12
3.3V 622.08Mbps Total Power Supply Current 386 mA LVPECL Mode
I
DD3.3-OC12
3.3V 622.08Mbps Total Power Supply Current 198 mA LVPECL Mode
RXCLKO dis-
abled
P
DD-OC1
Total Power Consumption mW LVPECL Mode
P
DD-OC3
Total Power Consumption mW LVPECL Mode
P
DD-OC12
Total Power Consumption 1485 mW LVPECL Mode
P
DD-OC12
Total Power Consumption 865 mW LVPECL Mode
RXCLKO dis-
abled
T
ABLE
20: LVDS/D
IFFERENTIAL
LVPECL I
NPUT
L
OGIC
S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
Test Condition: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified
SYMBOL TYPE PARAMETER MIN TYP MAX UNITS CONDITIONS
V
IH
LVDS/LVPECL Input High Voltage VDD
IO
+ 100 mV
V
IL
LVDS/LVPECL Input Low Voltage VDD
IO
- 100 mV
V
IDIFF
LVDS/LVPECL Input Differential Voltage
| V
IH
- V
IL
|
100 2400 mV
V
ICOMM
LVDS/LVPECL Input Common Mode Voltage 0 1200 VDD
IO
mV
T
ABLE
19: P
OWER
AND
C
URRENT
DC E
LECTRICAL
C
HARACTERISTICS
Test Conditions: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified
SYMBOL TYPE PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
XRT91L34
35
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
F
IGURE
19. LVDS/D
IFFERENTIAL
LVPECL V
OLTAGE
P
ARAMETER
C
ONVENTION
VIN_P
VIN_N
"1" "0" "1" V
IH
V
IL
V
ICOMM
V
IDIFF
V
IDIFF
=
|
V
IH
- V
IL
|
V
ICOMM
= ( V
IH
+ V
IL
) / 2
XRT91L34
36
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
N
OTE
: All input control pins are LVCMOS and LVTTL compatible. All output control pins are LVCMOS compatible only.
T
ABLE
21: LVDS O
UTPUT
L
OGIC
S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
Test Condition: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified
SYMBOL TYPE PARAMETER MIN TYP MAX UNITS CONDITIONS
V
OH
LVDS Output High Voltage 1100 1250 1500 mV 100
line - line
V
OL
LVDS Output Low Voltage 700 900 1200 mV 100
line - line
V
ODIFF
LVDS Output Differential Voltage
| V
OH
- V
OL
|
250 450 mV 100
line - line
V
OCOMM
LVDS Output Common Mode Voltage 850 1050 1350 mV 100
line - line
T
ABLE
22: D
IFFERENTIAL
LVPECL O
UTPUT
L
OGIC
S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
Test Conditions: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified
SYMBOL TYPE PARAMETER MIN TYP MAX UNITS CONDITIONS
V
OH
LVPECL Output High Voltage VDD
IO
- 900 mV
V
OL
LVPECL Output Low Voltage VDD
IO
- 1800 mV
V
ODIFF
LVPECL Output Differential Voltage
| V
OH
- V
OL
|
600 1100 mV Terminate with
50
to
VDD_IO-2.0
V
OCOMM
LVPECL Output Common Mode Voltage VDD
IO
- 1350 V
T
ABLE
23: LVTTL/LVCMOS S
IGNAL
DC E
LECTRICAL
C
HARACTERISTICS
Test Condition: VDD1.8 = 1.8V + 5%, VDDIO = 3.3V + 5% unless otherwise specified
SYMBOL TYPE PARAMETER MIN TYP MAX UNITS CONDITIONS
V
OH
LVCMOS Output High Voltage 2.4 VDD
_IO
V I
OH
= -8.0mA
V
OL
LVCMOS Output Low Voltage 0 0.4 V I
OH
= 8.0mA
V
IH
LVTTL/
LVCMOS
Input High Voltage 2.0 VDD
_IO
V
V
IL
LVTTL/
LVCMOS
Input Low Voltage 0 0.8 V
I
LEAK
LVTTL/
LVCMOS
Input Leakage Current -10 10
µ
A V
IN
= VDD
_IO
or V
IN
= 0
I
LEAK_PU
LVTTL/
LVCMOS
Input Leakage Current with
Pull-Up Resistor -100 10
µ
A V
IN
= 0
I
LEAK_PD
LVTTL/
LVCMOS
Input Leakage Current with
Pull-Down Resistor -10 100
µ
A V
IN
= VDD
_IO
XRT91L34
37
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
PACKAGE DIMENSIONS
T
ABLE
24: O
RDERING
I
NFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT91L34IV 128-pin Plastic Quad Flat Pack (14.0 x 14.0 x 1.4 mm, LQFP) -40
°
C to +85
°
C
XRT91L34IV-F 128-pin Pb-Free Quad Flat Pack (14.0 x 14.0 x 1.4 mm, LQFP) -40
°
C to +85
°
C
33
64
65
96
128
97
128-PIN Low Profile QUAD FLAT PACK
(14 x 14 x 1.4 mm, LQFP)
D
D
1
DD
1
B
e
132
Seating
Plane
A
2
A
1
C
L
α
A
MIN MAX MIN MAX
A 0.055 0.063 1.40 1.60
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B 0.005 0.009 0.13 0.23
C 0.004 0.008 0.09 0.20
D 0.622 0.638 15.80 16.20
D1 0.547 0.555 13.90 14.10
e
L 0.018 0.030 0.45 0.75
α0
o
7
o
0
o
7
o
Note: The control dimension is in millimeter.
SYMBOL
INCHES
MILLIMETERS
0.0157BSC 0.40BSC
Rev. 1.00
XRT91L34
38
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
T
ABLE
25: R
EVISION
H
ISTORY
REVISION # DATE DESCRIPTION
1.0.0 September 2007 New Release
1.0.1 October 2007 Fixed V
OH
, V
OL
and V
OCOMM
specs in
Figure 21
as per design input and prod-
uct engineering characterization.

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