NCP1083 Datasheet by Rochester Electronics, LLC

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© Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 3
1Publication Order Number:
NCP1083/D
NCP1083
Integrated High Power
PoE-PD Interface & DC-DC
Converter Controller with
9V Auxiliary Supply Support
Introduction
The NCP1083 is a member of ON Semiconductor’s high power
HIPO Power over Ethernet Powered Device (PoEPD) product family
and represents a robust, flexible and highly integrated solution
targeting demanding medium and high power Ethernet applications. It
combines in a single unit an enhanced PoEPD interface supporting
the IEEE 802.3af and the 802.3at standard and a flexible and
configurable DCDC converter controller.
The NCP1083’s exceptional capabilities enable applications to
smoothly transition from nonPoE to PoE enabled networks by also
supporting power from auxiliary sources such as AC power adapters
and battery supplies, eliminating the need for a second switching
power supply.
ON Semiconductors unique manufacturing process and design
enhancements allow the NCP1083 to deliver up to 25.5 W for the
IEEE 802.3at standard and up to 40 W for proprietary high power PoE
applications. The NCP1083 enables the IEEE 802.3at and implements
a two event physical layer classification. Additional proprietary
classification procedures support high power power sourcing
equipment (PSE) on the market. The unique high power features
leverage the significant cost advantages of PoE enabled systems to a
much broader spectrum of products in emerging markets such as
industrial ethernet devices, PTZ and Dome IP cameras, RFID readers,
MIMO WLAN access points, highend VoIP phones, notebooks, etc.
The integrated current mode DCDC controller facilitates
isolated and nonisolated flyback, forward and buck
converter topologies. It has all the features necessary for a
flexible, robust and highly efficient design including
programmable switching frequency, duty cycle up to 80
percent, slope compensation, and soft startup.
The NCP1083 is fabricated in a robust high voltage
process and integrates a rugged vertical Nchannel DMOS
with a low loss current sense technique suitable for the most
demanding environments and capable of withstanding harsh
environments such as hot swap and cable ESD events.
The NCP1083 complements ON Semiconductors ASSP
portfolio in industrial devices and can be combined with
stepper motor drivers, CAN bus drivers and other high
voltage interfacing devices to offer complete solutions to the
industrial and security market.
Features
These are PbFree Devices
Powered Device Interface
Flexible Auxiliary Power Supply Support
9 V Front, Rear and Direct Auxiliary Supply Connections
Supporting the IEEE 802.3af and the 802.3at Standard
Supports IEEE 802.3at Two Event Layer 1
Classification
High Power Layer 1 Classification Indicator
Extended Power Ranges up to 40 W
Programmable Classification Current
Adjustable Under Voltage Lock Out
Programmable Inrush Current Limit
Programmable Operational Current Limit up to
1100 mA for Extended Power Ranges
Overtemperature Protection
Industrial Temperature Range 40°C to 85°C with Full
Operation up to 150°C Junction Temperature
0.6 W HotSwap Passswitch with Low Loss Current
Sense Technique
Vertical Nchannel DMOS Passswitch Offers the
Robustness of Discrete MOSFETs with Integrated
Temperature Control
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NCP1083 = Specific Device Code
XXXX = Date Code
Y = Assembly Location
ZZ = Traceability Code
TSSOP20 EP
DE SUFFIX
CASE 948AB
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
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DCDC Converter Controller
Current Mode Control
Supports Isolated and Nonisolated DCDC Converter
Applications
Internal Voltage Regulators
Wide Duty Cycle Range with Internal Slope
Compensation Circuitry
Programmable Oscillator Frequency
Programmable Softstart Time
(Top View)
PIN DIAGRAM
Exposed
Pad
1SS
FB
COMP
VDDL
VDDH
GATE
ARTN
nCLASS_AT
CS
OSC
VPORTP
CLASS
UVLO
INRUSH
ILIM1
VPORTN1
RTN
VPORTN2
AUX
TEST
ORDERING INFORMATION
Part Number Temperature Range Package Shipping Configuration
NCP1083DEG 40°C to 85°CTSSOP20 EP
(PbFree)
74 units / Tube
NCP1083DER2G 40°C to 85°CTSSOP20 EP
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
INTERNAL
SUPPLY
&
BANDGAP
VDDH
INRUSH
ILIM1
CLASSIFICATION
DETECTION
VPORTN1,2
VPORTP
CLASS
INRUSH
ILIM1
VDDH
nCLASS_AT
VDDL
THERMAL
SHUT
DOWN
HOT SWAP SWITCH
CONTROL & CURRENT
LIMIT BLOCKS
UVLO
UVLO
RTN
ARTN
1.2 V
DCDC
CONVERTER
CONTROL
OSC
SS
FB
COMP
CS
GATE
VDDL
VDDL
VDDL
VDDH
5 K
OSC
VPORT
MONITOR
VDDL
Figure 1. NCP1083 Block Diagram
5 mA
AUX
DETECTION
AUXILIARY
SUPPLY
VDDL
20 mA
NCP1083 SIMPLIFIED APPLICATION DIAGRAMS UVLO GATE AUX 05 TEST FB VPORTNI ARTN VPORTN2 RTN ss osc COM CssI Rose VAUX(—) Figure 2. Isolated Flyiback Convener with near Aux Figure 2 shows Ihc intcgmmd Pull—PD swimh and DC—DC cummllcr configured I ompm vulmgc rcglllmion is accomplished wilh an memnl npto—collplcr and a shu UVLD GATE AUX cs TEST F5 VPORTNI ARTN VPORTN2 am 55 use COMP Spare Pairs Rose VAUXI-I Figure 3. Nonilsolaled Flyiback Convener wilh Rear Auxilia hllp://onsemi.com a
NCP1083
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SIMPLIFIED APPLICATION DIAGRAMS
Figure 2. Isolated Flyback Converter with Rear Auxiliary Supply
NCP1083
Rcs
Cvddl
Cvddh
Cpd
Css
Rosc
M1
T1
Cload
LD1
Rd1
Rclass
Rilim1
Rinrush
Optocoupler
R3
R4
R5
C1
Z1
Rslope
C2
Voutput
D1
OC1
GATE
RTN
FB
VPORTN2
VDDH
VDDL
VPORTN1
CLASS
ARTN
ILIM1
INRUSH
TEST
AUX
UVLO
CS
VPORTP
Data
Pairs
Spare
Pairs
R1
R2
RJ45
DB1
DB2
Raux1
VAUX(+)
VAUX()
Raux2
Raux3
D2
D3
Cline
Z_line COMPSS OSC
nCLASS_AT
Figure 2 shows the integrated PoEPD switch and DCDC controller configured to work in a fully isolated application. The
output voltage regulation is accomplished with an external optocoupler and a shunt regulator (Z1).
Figure 3. NonIsolated Flyback Converter with Rear Auxiliary Supply
NCP1083
Rcs
Cvddl
Cvddh
Cpd
Css
Rosc
M1
T1
Cload
LD1
Rd1
Rclass
Rilim1
Rinrush
Rslope
Voutput
D1
GATE
RTN
FB
VPORTN2
VDDH
VDDL
VPORTN1
CLASS
ARTN
ILIM1
INRUSH
TEST
AUX
UVLO
CS
VPORTP
Data
Pairs
Spare
Pairs
R1
R2
RJ45
DB1
DB2
Raux1
VAUX(+)
VAUX()
Raux2
Raux3
D2
D3
Cline
Z_line COMPSS OSC
R3
R4
C1comp
C2comp
Rcomp
nCLASS_AT
Figure 3 shows the integrated PoEPD and DCDC controller configured in a nonisolated flyback configuration. A
compensation network is inserted between the FB and the COMP pin for overall stability of the feedback loop.
NCP1083 SIMPLIFIED APPLICATION DIAGRAMS ”VLO GATE AUX cs TEST F3 VPDRTN1 ARTN VPDRTN2 RTN SS 050 COM Rcomp Rosc Cicomp Css'|_' cacomp Figure 4. Nonilsolated Flyrback with Extra Win mg and Hear Auxiliary Supply ”VLO GATE AUX cs TEST F3 VPDRTN1 ARTN VPDRTN2 am 55 use COMP Spare Fairs Rose (251 r VAUXI-I Figure 5. Nonilsolated Forward Converter with Rear A hilp://onsemi.com A
NCP1083
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SIMPLIFIED APPLICATION DIAGRAMS
Figure 4. NonIsolated Flyback with Extra Winding and Rear Auxiliary Supply
NCP1083
Rcs
Cvddl
Cvddh
Cpd
Css
Rosc
M1
T1
Cload
LD1
Rd1
Rclass
Rilim1
Rinrush
Rslope
Voutput
D1
GATE
RTN
FB
VPORTN2
VDDH
VDDL
VPORTN1
CLASS
ARTN
ILIM1
INRUSH
TEST
AUX
UVLO
CS
VPORTP
Data
Pairs
Spare
Pairs
R1
R2
RJ45
DB1
DB2
Raux1
VAUX(+)
VAUX()
Raux2
Raux3
D3
D4
Cline
Z_line COMPSS OSC
R3
R4
C1comp
C2comp
Rcomp
R5
D2
nCLASS_AT
Figure 4 shows the same nonisolated flyback configuration as Figure 3, but adds a 12 V auxiliary bias winding on the
transformer to provide power to the NCP1083 DCDC controller via its VDDH pin. This topology shuts off the current flowing
from VPORTP to VDDH and therefore reduces the internal power dissipation of the PD, resulting in higher overall power
efficiency.
Figure 5. NonIsolated Forward Converter with Rear Auxiliary Supply
NCP1083
Rcs
Cvddl
Cvddh
Cpd
Css
Rosc
M1
T1
Cload
LD1
Rd1
Rclass
Rilim1
Rinrush
Rslope
VoutputD1
GATE
RTN
FB
VPORTN2
VDDH
VDDL
VPORTN1
CLASS
ARTN
ILIM1
INRUSH
TEST
AUX
UVLO
CS
VPORTP
Data
Pairs
Spare
Pairs
R1
R2
RJ45
DB1
DB2
Raux1
VAUX(+)
VAUX()
Raux2
Raux3
D4
D5
Cline
Z_line COMPSS OSC
R3
R4
C1comp
C2comp
Rcomp
D3
D2
L1
nCLASS_AT
Figure 5 shows the NCP1083 used in a nonisolated forward topology.
High Power Considerations
The NCP1083 is designed to implement various
configurations of highpower PoE systems including those
based on the IEEE 802.3at standard. High power operation
can be enabled by a Dual Event Layer 1 classification or a
Single Event Layer 1 classification combined with a Layer 2
high power classification. The NCP1083 also supports
proprietary designs capable of delivering 25 W to 40 W to
the load in twopair configurations. A separate application
note describes these implementations (AND8332).
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Table 1. PIN DESCRIPTIONS
Name Pin No. Type Description
VPORTP 1 Supply Positive input power. Voltage with respect to VPORTN1,2.
VPORTN1
VPORTN2
6,8 Ground Negative input power. Connected to the source of the internal passswitch.
RTN 7 Ground DCDC controller power return. Connected to the drain of the internal passswitch. It must
be connected to ARTN. This pin is also the drain of the internal passswitch.
ARTN 14 Ground DCDC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
VDDH 16 Supply Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
VDDL 17 Supply Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external lowpower LED (1 mA max.) connected to nCLASS_AT, and can
also be used to add extra biasing current in the external optocoupler. VDDL must be by-
passed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
CLASS 2 Input Classification current programming pin. Connect a resistor between CLASS and VPORTN1,2.
INRUSH 4 Input Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN1,2.
ILIM1 5 Input Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN1,2.
UVLO 3 Input DCDC controller undervoltage lockout input. Voltage with respect to VPORTN1,2. Connect
a resistordivider from VPORTP to UVLO to VPORTN1,2 to set an external UVLO threshold.
GATE 15 Output DCDC controller gate driver output pin.
OSC 11 Input Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
nCLASS_AT 13 Output,
Open Drain
Activelow, opendrain Layer 1 dualfinger classification indicator.
COMP 18 I/O Output of the internal error amplifier of the DCDC controller. COMP is pulledup internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
optocoupler. Voltage with respect to ARTN.
FB 19 Input DCDC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
CS 12 Input Currentsense input for the DCDC controller. Voltage with respect to ARTN.
SS 20 Input Softstart input for the DCDC controller. A capacitor between SS and ARTN determines the
softstart timing.
AUX 9 Input When the pin is pulled up, the IEEE detection mode is disabled and the device can be sup-
plied by an auxiliary supply. Voltage with respect to VPORTN1,2. Connect the pin to the auxili-
ary supply through a resistor divider.
TEST 10 Input Digital test pin must always be connected to VPORTN1,2.
EP Exposed pad. Connected to VPORTN1,2 ground.
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Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min Max Unit
VPORTP Input power supply Voltage with respect to VPORTN1,2 0.3 72 V
RTN
ARTN
Analog ground supply 2 Passswitch in offstate
(Voltage with respect to VPORTN1,2)
0.3 72 V
VDDH Internal regulator output Voltage with respect to ARTN 0.3 17 V
VDDL Internal regulator output Voltage with respect to ARTN 0.3 3.6 V
CLASS Analog output Voltage with respect to VPORTN1,2 0.3 3.6 V
INRUSH Analog output Voltage with respect to VPORTN1,2 0.3 3.6 V
ILIM1 Analog output Voltage with respect to VPORTN1,2 0.3 3.6 V
UVLO Analog input Voltage with respect to VPORTN1,2 0.3 3.6 V
OSC Analog output Voltage with respect to ARTN 0.3 3.6 V
COMP Analog input / output Voltage with respect to ARTN 0.3 3.6 V
FB Analog input Voltage with respect to ARTN 0.3 3.6 V
CS Analog input Voltage with respect to ARTN 0.3 3.6 V
SS Analog input Voltage with respect to ARTN 0.3 3.6 V
nCLASS_AT Analog output Voltage with respect to ARTN 0.3 3.6
AUX Analog input Voltage with respect to VPORTN1,2 0.3 3.6 V
TEST Digital input Voltage with respect to VPORTN1,2 0.3 3.6 V
Ta Ambient temperature 40 85 °C
Tj Junction temperature 150 °C
TjTSD Junction temperature (Note 1) Thermal shutdown condition 175 °C
Tstg Storage Temperature 55 150 °C
TθJA Thermal Resistance,
Junction to Air (Note 2)
Exposed pad connected to VPORTN1,2 ground 37.6 °C/W
ESDHBM Human Body Model per JEDEC Standard JESD22 4kV
ESDCDM Charged Device Model 750 V
ESDMM Machine Model 300 V
LU Latchup per JEDEC Standard JESD78 ±200 mA
ESDSYS System ESD (contact/air) (Note 3) 8/15 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. TjTSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Mounted on a 1S2P (3 layer) test board with copper coverage of 25 percent for the signal layers and 90 percent copper coverage for the
inner planes at an ambient temperature of 85°C in still air. Refer to JEDEC JESD517 for details.
3. Surges per EN6100042, 1999 applied between RJ45 and output ground and between adapter input and output ground of the evaluation
board. The specified values are the test levels and not the failure levels.
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Recommended Operating Conditions
Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the
functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the
recommended operating conditions for extended periods of time may affect device reliability.
All values concerning the DCDC controller, VDDH, VDDL, and nCLASS_AT blocks are with respect to ARTN. All others
are with respect to VPORTN1,2 (unless otherwise noted).
Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
INPUT SUPPLY
VPORT Input supply voltage VPORT = VPORTP
VPORTN1,2.
0 57 V
SIGNATURE DETECTION
Vsignature Input supply voltage signature detection
range
1.4 9.5 V
Rsignature Signature resistance (Note 4) 23.75 26.25 kW
Offset_current I_VportP + I_Rtn VPORTP = RTN = 1.4 V 1.8 5 mA
Sleep_current I_VportP + I_Rtn VPORTP = RTN = 9.5 V 15 25 mA
CLASSIFICATION
Vcl Input supply voltage classification range 13 20.5 V
V_mark Mark event voltage range
(VPORTP falling)
5.4 9.7 V
I_mark Current consumption I_VportP +
I_Rdet in Mark Event range
5.4 V VPORT 9.5 V 0.5 2.0 mA
dR_mark Input signature during Mark Event
(Note 7)
For information only 12 kW
Vreset Classification Reset range
(VPORTP falling)
4.3 4.9 5.4 V
Iclass0 Class 0: Rclass 10 kW (Note 6) Iclass0 = I_VportP + I_Rdet 04 mA
Iclass1 Class 1: Rclass 130 W (Note 6) Iclass1 = I_VportP + I_Rdet 912 mA
Iclass2 Class 2: Rclass 69.8 W (Note 6) Iclass2 = I_VportP + I_Rdet 17 20 mA
Iclass3 Class 3: Rclass 44.2 W (Note 6) Iclass3 = I_VportP + I_Rdet 26 30 mA
Iclass4 Class 4: Rclass 30.9 W (Note 6) Iclass4 = I_VportP + I_Rdet 36 44 mA
Iclass5 Class 5: Rclass 22.1 W (Notes 5 and 6)
(for proprietary high power applications)
Iclass5 = I_VportP + I_Rdet 50 60 mA
IDCclass Internal current consumption during
classification (Note 8)
For information only 600 mA
CLASSIFICATION INDICATOR
nCLASS_AT_i nCLASS_AT current source 13 20 27 mA
NCLASS_AT_pd RDS,ON of NCLASS_AT pull down
transistor
For information only 130 W
4. Test done according to the IEEE 802.3af 2 Point Measurement. The minimum probe voltages measured at the PoEPD are 1.4 V and 2.4 V,
and the maximum probe voltages are 8.5 V and 9.5 V.
5. This extended classification range can be used with a PSE which also uses this classification range to deliver more current than specified
by IEEE 802.3.
6. Measured with an external Rdet of 25.5 kW between VPORTP and VPORTN1,2, and for 13 V < VPORT < 20.5 V (with VPORT = VPORTP
– VPORTN1,2). Resistors are assumed to have 1% accuracy.
7. Measured with the 2 Point Measurement defined in the IEEE 802.3af standard with 5.4 V and 9.5 V the extreme values for V2 and V1.
8. This typical current excludes the current in the Rclass and Rdet external resistors.
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Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
UVLO
Vuvlo_on Default turn on voltage (VportP rising) UVLO pin tied to VPORTN1,2 38 40 V
Vuvlo_off Default turn off voltage (VportP falling) UVLO pin tied to VPORTN1,2 29.5 32 V
Vhyst_int UVLO internal hysteresis UVLO pin tied to VPORTN1,2 6V
Vuvlo_pr UVLO external programming range UVLO pin connected to the res-
istor divider (R1 & R2).
AUX pin tied to VPORTN1,2
For information only
13 50 V
Vuvlo_pr_aux UVLO external programming VPORT
range with auxiliary supply support
UVLO & AUX pins configured
for auxiliary supply support
8.5 18 V
Vhyst_ext UVLO external hysteresis UVLO pin connected to the res-
istor divider (R1 & R2)
15 %
Uvlo_Filter UVLO on/off filter time For information only 90 mS
AUXILIARY SUPPLY OPERATION – INPUT SUPPLY
Vaux_min1 VPORTPARTN voltage at startup
(required for VDDH > VDDH_Por_R)
VAUX rising No external load
on VDDL & VDDH
8.7 V
Vaux_min2 VPORTPARTN voltage during PWM
operation
(required for VDDH > VDDH_Por_F)
Voltage with respect to
Ivddl_load1 & Ivddh_load1 for
the load current conditions
8.5 V
AUXILIARY SUPPLY OPERATION – AUX PIN
Vaux_off Voltage range of the AUX pin where the
auxiliary supply circuit is guaranteed
not operational.
Voltage with respect to
VPORTN1,2.
0.2 V
Vaux_on Voltage range of the AUX pin where the
auxiliary supply circuit is guaranteed
operational.
Voltage with respect to
VPORTN1,2
1.5 3.3 V
Raux Total resistance value of the resistor di-
vider connected to the AUX pin (sum of
Raux1 and Raux3)
Between VAUX supply &
VPORTN1,2
25 kW
AUXILIARY SUPPLY OPERATION – VDDL REGULATOR
Ivddl_load1 Current load on the VDDL pin with
VPORTP ARTN = 8.5 V
(Notes 9 and 10)
Ivddh_load + Ivddl_load <
4.5 mA
− − 1 mA
Ivddl_load2 Current load on the VDDL pin with
VPORTP ARTN > 12.5 V
(Notes 9 and 10)
Ivddh_load + Ivddl_load <
10 mA
2.25 mA
AUXILIARY SUPPLY OPERATION – VDDH REGULATOR
Ivddh_load1 Current load on the VDDH regulator
with VPORTP ARTN = 8.5 V
(Notes 9 and 10)
Ivddh_load + Ivddl_load <
4.5 mA
4.5 mA
Ivddh_load2 Current load on the VDDH regulator
with VPORTP ARTN > 12.5 V
(Notes 9 and 10)
Ivddh_load + Ivddl_load <
10 mA
10 mA
9. Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
10.See Figures 6 and 7 for specifications on the load current at lower or higher VPORTP - ARTN voltages. In case the application requires more
current capability on VDDL and VDDH, it is recommended to externally supply the VDDH pin with a bias winding from the transformer or
to add a diode between VAUX(+) and VDDH pin (verify the VAUX voltage does not exceed the VDDH voltage range).
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Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
PASSSWITCH AND CURRENT LIMITS
Ron Passswitch Rdson Max Ron specified at Tj = 130°C0.6 1.2 W
I_Rinrush1 Rinrush = 150 kW (Note 11) Measured at RTNVPORTN1,2 = 3 V 95 125 155 mA
I_Rinrush2 Rinrush = 57.6 kW (Note 11) Measured at RTNVPORTN1,2 = 3 V 260 310 360 mA
I_Rilim1 Rilim1 = 84.5 kW (Note 11) Current limit threshold 450 510 570 mA
I_Rilim2 Rilim1 = 66.5 kW (Note 11) Current limit threshold 600 645 690 mA
I_Rilim3 Rilim1 = 55.6 kW (Note 11) Current limit threshold 720 770 820 mA
I_Rilim4 Rilim1 = 38.3 kW (Note 11) Current limit threshold 970 1100 1230 mA
INRUSH AND ILIM1 CURRENT LIMIT TRANSITION
Vds_pgood VDS required for power good sta-
tus
RTNVPORTN1,2 falling; voltage
with respect to VPORTN1,2
0.8 1 1.2 V
Vds_pgood_hyst VDS hysteresis required for power
good status
Voltage with respect to VPORTN1,2 8.2 V
VDDH REGULATOR
VDDH_reg Regulator output voltage
(Notes 12 and 13)
Ivddh_load + Ivddl_load < 10 mA
with Ivddl_load < 2.25 mA and
12.5 V < VPORTP ARTN < 57 V
8.4 9 9.6 V
VDDH_Off Regulator turnoff voltage For information only VDDH_reg + 0.5 V V
VDDH_lim VDDH regulator current limit
(Notes 12 and 13)
13 26 mA
VDDH_Por_R VDDH POR level (rising) 7.3 8.3 V
VDDH_Por_F VDDH POR level (falling) 67 V
VDDH_ovlo VDDH overvoltage level (rising) 16 18.5 V
VDDL REGULATOR
VDDL_reg Regulator output voltage
(Notes 12 and 13)
Ivddl_load < 2.25 mA with
Ivddh_load + Ivddl_load < 10 mA and
12.5 V < VPORTP ARTN < 57 V
3.05 3.3 3.55 V
VDDL_Por_R VDDL POR level (rising) VDDL
0.2
VDDL
0.02
V
VDDL_Por_F VDDL POR level (falling) 2.5 2.9 V
GATE DRIVER
Gate_Tr GATE rise time (1090%) Cload = 2 nF, VDDHreg = 9 V 50 ns
Gate_Tf GATE fall time (9010%) Cload = 2 nF, VDDHreg = 9 V 50 ns
PWM COMPARATOR
VCOMP COMP control voltage range For information only 1.3 3 V
ERROR AMPLIFIER
Vbg_fb Reference voltage Voltage with respect to ARTN 1.15 1.2 1.25 V
Av_ol DC open loop gain For information only 80 dB
GBW Error amplifier GBW For information only 1 MHz
11. The current value corresponds to the PoEPD input current (the current flowing in the external Rdet and the quiescent current of the device
are included). Resistors are assumed to have 1% accuracy.
12.Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.
13.Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
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Table 3. OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
SOFTSTART
Vss Softstart voltage range 1.15 V
Vss_r Softstart low threshold (rising edge) 0.35 0.45 0.55 V
Iss Softstart source current 3 5 7 mA
CURRENT LIMIT COMPARATOR
CSth CS threshold voltage 324 360 396 mV
Tblank Blanking time For information only 100 ns
OSCILLATOR
DutyC Maximum duty cycle Fixed internally 80%
Frange Oscillator frequency range 100 500 kHz
F_acc Oscillator frequency accuracy ±25 %
CURRENT CONSUMPTION
IvportP1VPORTP internal current consumption
(Note 14)
DCDC controller off 2.5 3.5 mA
IvportP2VPORTP internal current consumption
(Note 15)
DCDC controller on 4.7 6.5 mA
THERMAL SHUTDOWN
TSD Thermal shutdown threshold Tj = junction temperature 150 °C Tj
Thyst Thermal hysteresis Tj = junction temperature 15 °C Tj
THERMAL RATINGS
TAAmbient temperature 40 85 °C
TJJunction temperature Parametric values guaranteed
Max 1000 hours
125
150
°C
°C
14.Conditions
a. No current through the passswitch
b. DCDC controller inactive (SS shorted to RTN)
c. No external load on VDDH and VDDL
d. VPORTP = 57 V
15.Conditions
a. No current through the passswitch
b. Oscillator frequency = 100 kHz
c. No external load on VDDH and VDDL
d. Aux winding not used
e. 2 nF on GATE, DCDC controller enabled
f. VPORTP = 57 V
Figure 6. (Ivddl_load)max with Auxiliary
Supply Operation
Figure 7. (Ivddh_load+Ivddl_load)max with
Auxiliary Supply Operation
VPORTPARTN VOLTAGE DURING PWM
OPERATION (V)
VPORTPARTN VOLTAGE DURING PWM
OPERATION (V)
131211.51110.5109.08.5
4.0
4.5
5.0
6.5
7.5
8.5
9.5
10.5
0.50
0.75
1.00
1.25
1.75
2.00
2.25
2.50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
9.5 12.5 13.5
5.5
6.0
7.0
8.0
9.0
10.0
131211.51110.5109.08.5 9.5 12.5 13.5
1.50
NCP1083
http://onsemi.com
11
Description of Operation
Powered Device Interface
The PD interface portion of the NCP1083 supports the
IEEE 802.3af and 802.3at defined operating modes:
detection signature, current source classification, inrush and
operating current limits. In order to give more flexibility to
the user and also to keep control of the power dissipation in
the NCP1083, both current limits are configurable. The
device enters operation once its programmable Vuvlo_on
threshold is reached, and operation ceases when the supplied
voltage falls below the Vuvlo_off threshold. Sufficient
hysteresis and Uvlo filter time are provided to avoid false
power on/off cycles due to transient voltage drops on the
cable.
Detection
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE 802.3af standard specification range (23.75 kW to
26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non-linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1083 presents suitable impedance in parallel with the
25.5 kW Rdet external resistor connected between VPORTP
and VPORTN. For some types of diodes (especially Schottky
diodes), it may be necessary to adjust this external resistor.
When the Detection_Off level is detected (typically
11.5 V) on VPORTP, the NCP1083 turns on its internal
3.3 V regulator and biasing circuitry in anticipation of the
classification phase as the next step.
Classification
Once the PSE device has detected the PD device, the
classification process begins. The NCP1083 is fully capable
of responding and completing all classification handshaking
procedures as described next.
Classification Current Source Generation
In classification, the PD regulates a constant current
source that is set by the external resistor RCLASS value on
the CLASS pin. Figure 8 shows the schematic overview of
the classification block. The current source is defined as:
Iclass +
Vbg
Rclass
, (where Vbg is 1.2 V)
CLASS
VDDA1
1.2 V
VPORTP
VPORTN1,2 NCP1083
Rclass
Figure 8. Classification Block Diagram
The NCP1083 can handle all defined types of
classification, IEEE 802.3af, 802.3at and proprietary
classification.
In the IEEE 802.3af standard the classification is
performed with a Single Event Layer 1 classification.
Depending on the current level set during that single event
the power level is determined. The IEEE 802.3at standard
allows two ways of classification which can also be
combined. These two approaches enable higher power
applications through a variety of PSE equipment.
For power injectors and midspans a pure physical
hardware handshake is introduced called Two Event Layer
1 classification. This approach allows equipment that has no
data link between PSE and PD to classify as high power.
Since switches can establish a data link between PSE and
PD, a software handshake is possible. This type of
handshake is called Layer 2 classification (or Data Link
Layer classification). It has the main advantage of having a
finer power resolution and the ability for the PSE and PD to
participate in dynamic power allocation.
Table 4. SINGLE AND DUAL EVENT CLASSIFICATION
Standard Layer Handshake
802.3af 1 Single event physical classification
802.3at 1 Two event physical classification
802.3at 2 Data-link (IP) communication classi-
fication
One Event Layer 1 Classification
An IEEE 802.3af compliant PSE performs only One
Event Layer 1 classification event by increasing the line
voltage into the classification range only once.
Two Event Layer 1 Classification
A IEEE 802.3at compliant PSE using this physical
classification performs two classification events and looks
for the appropriate response from the PD to check if the PD
is IEEE 802.3at compatible.
The PSE will generate the sequence described in Figure 8.
During the first classification finger, the PSE will measure
the classification current which should be 40 mA if the PD
is at compliant. If this is the case, the PSE will exit the
classification range and will force the line voltage into the
Mark Event range. Within this range, the PSE may check the
non-valid input signature presented by the PD (using the two
point measurement defined in the IEEE 802.3af standard).
Then the PSE will repeat the same sequence with the second
classification finger. A PD which has detected the sequence
Finger + Mark + Finger + Mark” knows the PSE is IEEE
802.3at compliant, meaning the PSE will deliver more
current on the port. (Note that a PSE IEEE 802.3at compliant
may apply more than two fingers, but the final result will be
the same as two fingers).
Class AT ACWOBJ "CLASSJT : aw lsmaxmn [lw‘a‘ed was convened Powered Dewce Apphcalvon INZ vsuP Layer 2 angme H Mycraprocessowr Mycmwulrol‘er ++ names
NCP1083
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12
1st Class Event
Class range
Mark Range
Reset Range
2 Fingers Classification
0 V
5.4 V
9.7 V
13 V
20.5 V
UVLO_on
Power OnDetection
PSE identified as type 2 PSE (at)
PSE identified by default as type 1 PSE (af)
PSE Type identification:
Number of Mark Event: 0 1 2X
Operation Mode:
Figure 9. Hardware Physical Classification Event Sequence
with Mark Events (.at spec)
1st Mark Event 2nd Class Event 2nd Mark Event
nCLASS_AT Indicator
The nCLASS_AT active low open drain output pin can be
used to notify to the microprocessor of the powered device
that the PSE performed a one or two event hardware
classification. If a two event hardware classification has
occured and once the PD application is supplied power by
the NCP1083 DC-DC converter, the nCLASS_AT pin will
be pulled down to ARTN by the internal low voltage NMOS
switch (ARTN is the ground connection of the DC-DC
converter). Otherwise, nCLASS_AT will be disabled and
will be pulled up to VDDL (3.3 V typ) via an internal current
source (20 mA typ) and via the external pull-up resistor.
The following scheme illustrates how the nCLASS_AT
pin may be configured with the processor of the powered
device. An opto-coupler is used to guarantee full isolation
between the Ethernet cable and the application.
Figure 10. Isolated nClass_AT Communication with the Powered Device Application
As soon as the application is powered by the DC-DC
converter and completes initialization, the microprocessor
should check if the NCP1083 detected a two event hardware
classification by reading its digital input (pin IN1 in this
example). If pin IN1 is low, the application knows power is
supplied by a IEEE 802.3at compliant PSE, and can deliver
power up to the level specified by the IEEE 802.3at standard.
Otherwise the application will have to perform a Layer 2
classification with the PSE. There are several scenarios for
which the NCP1083 will not enable its nCLASS_AT pin:
k9 nimr determines when to apply power To use the default settings for U VP be p . as s11 1.2 VPORTNI ‘2 NCPloBa Figure 11. Default UVLO Settings To define the UVLO thIcshold externally, the UVLO pin nectcd m the center of an external resistor between VPURTP and VPORTNLZ , shown in The series resistance value of the external VAUXH) http://onsemi.com 13
NCP1083
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13
The PSE skipped the classification phase.
The PSE performed a one event hardware classification
(it can be a IEEE 802.3af or a 802.3at compliant PSE
with Layer 2 engine).
The PSE performed a two event hardware classification
but it did not properly control the input voltage in the
mark voltage window, (for example it crossed the reset
range).
Power Mode
When the classification handshake is completed, the
PSE and PD devices move into the operating mode.
Under Voltage Lock Out (UVLO)
The NCP1083 incorporates an under voltage lock out
(UVLO) circuit which monitors the input voltage and
determines when to apply power to the DCDC controller.
To use the default settings for UVLO (see Table 3), the pin
UVLO must be connected to VPORTN1,2. In this case the
signature resistor has to be placed directly between
VPORTP and VPORTN1,2, as shown in Figure 11.
Figure 11. Default UVLO Settings
UVLO
VPORTP
VPORTN1,2
NCP1083
VPORT Rdet
To define the UVLO threshold externally, the UVLO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN1,2 as shown in
Figure 12. The series resistance value of the external
resistors must add to 25.5 kW and replaces the internal
signature resistor.
Figure 12. External UVLO Configuration
UVLO
VPORTN1,2
NCP1083
VPORT
R2
R1
VPORTP
For a Vuvlo_on desired turnon voltage threshold, R1 and
R2 can be calculated using the following equations:
R1 )R2 +Rdet
R2 +1.2
Vulvo_on
Rdet
When using the external resistor divider, the NCP1083 has
an external reference voltage hysteresis of 15 percent typical.
Auxiliary Supply Support
To support applications connected to nonPoE enabled
networks and minimize the bill of materials, the NCP1083
supports drawing power from an external supply. The
NCP1083 supports the IEEE 802.3af/at standard when PoE
power sourcing is available and acts as a regular DCDC
converter when there is no power source available on the
Ethernet cable as shown in Figure 13.
Auxiliary supply support can be implemented in three
ways depending on where the auxiliary supply is injected.
The front, rear and direct auxiliary supply configurations are
explained in more detail in the application note AND9080.
UVLO
VPORTN1,2
NCP1083
VPORTP
Rdet1
Raux2
VAUX(+)
Rdet2
Pass
Switch
RTN
Raux1
Raux3
AUX
D1
D2
POE(+)
POE()
VPORT
Cpd
DCDC Stage
VAUX()to VPORTN1,2 (Front AUX Configuration)
to RTN (Rear AUX Configuration)
Or
Figure 13. Front and Rear Auxiliary Supply Input with Support for Very Low Input Voltages
Optional
for very low
VAUX only
m 24K i.~ mo volmgc dmp over Ihc rcaificrs an d d
NCP1083
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14
When the auxiliary input supply is above 13.5 V, connect
the AUX pin to VPORTN1,2. When the auxiliary supply is
below 13.5 V (but above 9 V), calculate the voltage dividers
Raux1, Raux3 and Raux2, Rdet1, Rdet2 to divide the input
voltage using the below formulas together with the formulas
from the previous section. This will ensure that for valid input
voltages, the voltage at the UVLO and AUX pins are above
their threshold voltages. Note that the maximum voltage is
3.3 V.
Raux3 +Raux1 Vt
Vaux *Vdp *Vt
Raux1 +20 kW
Raux2 +
Vaux *Vdp *Vd*Vt
Vt
845 *
Vaux*Vdp*Vd*Vt
24 K
Where Vd is the voltage drop over the rectifiers and masking
diodes (typical 0.6 V), Vdp is the forward drop of the
NCP1083 internal diode (typical 0.5 V), and Vt is the
threshold voltage on the AUX pin (typical 1.5 V).
Note that as soon as the auxiliary supply is connected the
PoE interface (detection and classification) is disabled and
does not allow the PD device to be powered from the
Ethernet until the auxiliary supply is removed.
If the PoE PD device was drawing the current from the
Ethernet cable before the auxiliary supply is connected, the
power will continue to be supplied from the Ethernet cable
unless the voltage of the auxiliary supply is higher than the
Ethernet supply voltage.
Inrush and Operational Current Limitations
The inrush current limit and the operational current limit
are programmed individually by an external Rinrush and
Rilim1 resistors respectively connected between INRUSH
and VPORTN1,2, and between ILIM1 and VPORTN1,2 as
shown in Figure 14.
ILIM1 /
INRUSH
VDDA1
Vbg1
VDDA1
VPORTNx
Ilim_ref
NCP1083
Figure 14. Current Limitation Configuration (Inrush & Ilim1 Pins)
Ilim1
Vds_pgood
threshold
VPORTNx
Pass Switch
Inrush
I_pass_switch
NCP1083
RTN
VDS_PGOOD
0
1
VDDA1 VDDA1
1 V / 9.2 V
2 V
Current_limit_ON
&
detector
Figure 15. Inrush and Ilim1 Selection Mechanism
VDDA1
/V hllp://onsemi.com 15
NCP1083
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15
When VPORT reaches the UVLO_on level, the Cpd
capacitor is charged with the INRUSH current (in order to
limit the internal power dissipation of the passswitch).
Once the Cpd capacitor is fully charged, the current limit
switches from the inrush current to the current level (ilim1)
as shown in Figure 15. This transition occurs when both
following conditions are satisfied:
1. The VDS of the passswitch is below the
Vds_pgood low level (1 V typical).
2. The passswitch is no longer in current limit
mode, meaning the gate of the passswitch is
“high” (above 2 V typical).
The operational current limit will stay selected as long as
Vds_pgood is true (meaning that RTNVPORTN1,2 is
below the high level of Vds_pgood). This mechanism allows
a current level transition without any current spike in the
passswitch because the operational current limit (ilim1) is
enabled once the passswitch is not limiting the current
anymore, meaning that the Cpd capacitor is fully charged.
Thermal Shutdown
The NCP1083 includes thermal protection which shuts
down the device in case of high power dissipation. Once the
thermal shutdown (TSD) threshold is exceeded, following
blocks are turned off:
DCDC controller
Passswitch
VDDH and VDDL regulators
CLASS regulator
When the TSD error disappears and if the input line
voltage is still above the UVLO level, the NCP1083
automatically restarts with the current limit set in the inrush
state, the DCDC controller is disabled and the Css
(softstart capacitor) discharged. The DCDC controller
becomes operational as soon as capacitor Cpd is fully
charged.
DCDC Converter Controller
The NCP1083 implements a current mode DCDC
converter controller which is illustrated in Figure 16.
VDDL
FB
CS
360 mV
Oscillator
COMP
SS
Gate
Driver
PWM comp
OSC
VDDL
VDDL
Blanking
time
Current Slope
Compensation
2
Softstart
R
S
Q
1.45 V
1.2 V
Current limit
comp
0
9 V LDO
3.3 V LDO
GATE
VDDH
ARTN
VPORTP
Set
CLK
Reset
CLK
Figure 16. DCDC Controller Block Diagram
5 kW
10 mA
11 kW
5 mA
&
Sawtooth
Generator
Internal VDDH and VDDL Regulators and Gate Driver
An internal linear regulator steps down the VPORTP
voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1083
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC-DC controller and
nCLASS_AT blocks. Moreover it can provide current to
light a LED connected on the nCLASS_AT pin.
In order to prevent uncontrolled operations, both regulators
include poweronreset (POR) detectors which prevent the
DCDC controller from operating when either VDDH or
VDDL is too low. In addition, an overvoltage lockout
(OVLO) on the VDDH supply disables the gate driver in case
of an openloop converter with a configuration using the bias
winding of the transformer (see Figure 4).
FOSC(kHz)
NCP1083
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16
Both VDDH and VDDL regulators turn on as soon as
VPORT reaches the Vuvlo_on threshold.
Error Amplifier
In nonisolated converter topologies, the high gain
internal error amplifier of the NCP1083 and the internal
1.2 V reference voltage regulate the DCDC output voltage.
In this configuration, the feedback loop compensation
network should be inserted between the FB and COMP pins
as shown in Figures 3, 4 and 5.
In isolated topologies the error amplifier is not used
because it is already implemented externally with the shunt
regulator on the secondary side of the DCDC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the optocoupler has to
be connected on the COMP pin where an internal 5 kW
pullup resistor is tied to the VDDL supply (see Figure 16).
SoftStart
The softstart function provided by the NCP1083 allows
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor CSS between the SS
and ARTN pins.
While the DCDC controller is in POR, the capacitor CSS
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
CSS to initiate softstart. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DCDC operation starts with a duty cycle limit which
increases with the SS pin voltage. The softstart function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
Softstart can be programmed by using the following
equation:
tSS(ms) +0.23 CSS(nF)
Current Limit Comparator
The NCP1083 current limit block behind the CS pin
senses the current flowing in the external MOSFET for
current mode control and cyclebycycle current limit. This
is performed by the current limit comparator which, on the
CS pin, senses the voltage across the external Rcs resistor
located between the source of the MOSFET and the ARTN
pin.
The NCP1083 also provides a blanking time function on
CS pin which ensures that the current limit and PWM
comparators are not prematurely trigged by the current spike
that occurs when the switching MOSFET turns on.
Slope Compensation Circuitry
To overcome subharmonic oscillations and instability
problems that exist with converters running in continuous
conduction mode (CCM) and when the duty cycle is close
or above 50 percent, the NCP1083 integrates a current slope
compensation circuit. The amplitude of the added slope
compensation is typically 110 mV over one cycle.
As an example, for an operating switching frequency of
250 kHz, the internal slope provided by the NCP1083 is
27.5 mV/ mA typically.
DCDC Controller Oscillator
The frequency is configured with the Rosc resistor
inserted between OSC and ARTN, and is defined by the
following equation:
ROSC(kW)+38600
FOSC(kHz)
The duty cycle limit is fixed internally at 80 percent.
E1 HHHHHHHHHLE EH >+ JLM TOP 7 -€Ha;m SIDE VIEW SOLDERING FOOTPRINT 4.30 immlflflfljlfl l— _l T | + | | IHHHHHHHHH ZHTJ new H JLS‘és PITCH DIMENSIONS MTLLLMETEHS HRH EHHHH :fifi sEAuua mm: DETAIL B H T I i c :1 I I H L I A SECTION 3-5 0N Semiwndudw" TEs DTMENsTDNuN v14 5M 1956 CONTROLUNG DTMENSLDN MILUMEIERS DTMENsTDN a DOES NoT INCLUDE DAMDAH PRDTRDSTDN ALLOWABLE DAMDAH PRDTRDSTDN sHALL HE a U7 TN EXCESS D; THE LEAD W‘DTH AT MMC DAMBAR cANNoT EE LoAcTED DN THE LOWER RADTus on THE F001 0: THE LEAD 4 DTMENsTDNs :7. Due a To BE MEASURED BE TWEEN u TO AND a 25 FROM LEAD THF DATuMs AAND a ARE ARE DEIERMINED AT DATDM H DATuM H Ts LDAcTED AT THE MOLD PAHTTNG UNE AND couNcTDENT W‘TH LEAD WHERE THE LEAD EXITS THE PLAsTTc DDDv DTMENsTDN D DoEs Not TNcLuDE MOLD FLASH PRDTRDSTDNS DH GATE BURRS MoLD FLASH PRDTRDSTDNS 0R GATE BURRS sHALL NDT EXCEEDD Ts PER sTDE DTMENsToN E1 DOES NDT INCLUDE TNTERLEAD FLASH 0R PHDTHusToN TN TERLEAD FLASH 0R PRoTRusToN sHALL NoT EXs CEED u Ts PER sTDE D AND ET ARE DETEHMTNED AT DATDM H MILuszzAs mu MIN MAX i ammo rLAN: L DETAILA ammj‘ ’ A nu M nus ms ms nu m 025 mu um nus nus m sin 030‘ an assasc aan mu GAUGE Miss!) u“ y , nu , 3m GENERIC MARKING DIAGRAM‘ HHHHHHHHH xxxx xxxx ALYW- o . HHHHHHHHH Evgfirnfi‘ *‘rms informahon IS genenc. PHease reler Io dewce dale Shea to! aclual pan mavkmg. ON SarnTaanuuaum and are hademavks av Samanaucxar Campunenls lnduslnes. LLC dba oN Samanaucxar Dr us saasmanas Tn xna Umled sxaxas andJm mhev cmmmes ON Samaanaucxar vesewes ma mm ID make changes wuhum Yunnan mouse In any amaans hecem oN Sammnuaa‘m makes nu walvamy. represenlalmn m guarantee regardmg ma suHaHHHy at w; manuals can any pamcu‘av purpase nnv aaas ON Samanuaamy assume any HaHHHy snsmg mac xna aachaHan m use M any pmdudnv cHTcml ana saaamcany mscxauns any and an HaHHHy an‘udmg mam Hnmauan spamaT cansequenha‘ m mudeflvla‘ damages oN Sammnaucxar dues nn| away any hcense under Hs paLanL nghls Ivar xna ngms av n|hers
TSSOP20 EP
CASE 948AB01
ISSUE O
DATE 17 JUN 2008
SCALE 1:1
DIM
D
MIN MAX
6.60
MILLIMETERS
E1 4.30 4.50
A1.10
A1 0.05 0.15
L0.50 0.70
e0.65 BSC
P--- 4.20
c0.09 0.20
c1 0.09 0.16
b0.19 0.30
b1 0.19 0.25
L2 0.25 BSC
M0 8
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.07 IN EXCESS OF THE LEAD WIDTH AT
MMC. DAMBAR CANNOT BE LOACTED ON THE
LOWER RADIUS OR THE FOOT OF THE LEAD.
4. DIMENSIONS b, b1, c, c1 TO BE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM LEAD TIP.
5. DATUMS A AND B ARE ARE DETERMINED AT DATUM
H. DATUM H IS LOACTED AT THE MOLD PARTING
LINE AND COINCIDENT WITH LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY.
6. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT
INCLUDE INTERLEAD FLASH OR PROTRUSION. IN-
TERLEAD FLASH OR PROTRUSION SHALL NOT EX-
CEED 0.15 PER SIDE. D AND E1 ARE DETERMINED
AT DATUM H.
PIN 1
REFERENCE
D
E1
0.08
A
SECTION BB
b
b1
cc1
SEATING
PLANE
20X b
E
e
DETAIL A
6.40
---
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
XXXX
XXXX
ALYWG
G
4.30
20X
0.98
20X
0.35
0.65
DIMENSIONS: MILLIMETERS
PITCH
SOLDERING FOOTPRINT
L
L2 GAUGE
DETAIL A
e/2
DETAIL B
A2 0.85 0.95
E6.40 BSC
P1 --- 3.00
PLANE
SEATING
PLANE
C
H
B
B
B
M
END VIEW
A-B
M
0.10 DC
TOP VIEW
SIDE VIEW
A-B0.20 D
C
110
1120
B
A
D
DETAIL B
2X 10 TIPS
A1
A2
C
0.05 C
C
P
P1
BOTTOM VIEW
3.106.76
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
(Note: Microdot may be in either location)
20X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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TSSOP20 EXPOSED PAD
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