IRFP4668PBF Datasheet by Infineon Technologies

International ISBR Rectitier Parameter m0 m0 1 G D 5 Gate Drain Source Single Pulse Avalanche Energy ® Avalanche Current 6) Repetitive Avalanche Energy ® Parameter
9/8/08
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HEXFET® Power MOSFET
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
S
D
G
GDS
Gate Drain Source
TO-247AC
S
D
G
D
IRFP4668PbF
VDSS 200V
RDS(on) typ. 8.0m:
max
.
9.7m:
ID 130A
Absolute Maximum Ratings
Symbol Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V A
IDM Pulsed Drain Current c
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
dv/dt Peak Diode Recovery eV/ns
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy dmJ
IAR Avalanche Current cA
EAR Repetitive Avalanche Energy fmJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case j––– 0.29
RθCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RθJA Junction-to-Ambient ij ––– 40
300
Max.
130
92
520
760
See Fig. 14, 15, 22a, 22b,
520
57
-55 to + 175
± 30
3.5
10lbxin (1.1Nxm)
PD -97140
lntemofiono‘ I: Rechfier Bod onde (Bod onde) G) -n'unchondiode.
IRFP4668PbF
2www.irf.com
S
D
G
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.23mH
RG = 25Ω, IAS = 81A, VGS =10V. Part not recommended for
use above this value.
ISD 81A, di/dt 520A/μs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400μs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Voltage 200 ––– ––– V
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.21 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 8.0 9.7 mΩ
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V
IDSS Drain-to-Source Leakage Current ––– ––– 20 μA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
RGInternal Gate Resistance ––– 1.0 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
gfs Forward Transconductance 150 ––– ––– S
QgTotal Gate Charge ––– 161 241 nC
Qgs Gate-to-Source Charge ––– 54 –––
Qgd Gate-to-Drain ("Miller") Charge ––– 52 –––
Qsync Total Gate Charge Sync. (Qg - Qgd)––– 109 –––
td(on) Turn-On Delay Time ––– 41 ––– ns
trRise Time ––– 105 –––
td(off) Turn-Off Delay Time ––– 64 –––
tfFall Time ––– 74 –––
Ciss Input Capacitance ––– 10720 –––
Coss Output Capacitance ––– 810 –––
Crss Reverse Transfer Capacitance ––– 160 ––– pF
Coss eff. (ER) Effective Output Capacitance (Energy Related)
h
––– 630 –––
Coss eff. (TR) Effective Output Capacitance (Time Related)g––– 790 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 130 A
(Body Diode)
ISM Pulsed Source Current ––– ––– 520
(Body Diode)c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time ––– 130 ––– ns TJ = 25°C VR = 100V,
––– 155 ––– TJ = 125°C IF = 81A
Qrr Reverse Recovery Charge ––– 633 ––– nC TJ = 25°C di/dt = 100A/μs f
––– 944 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 8.7 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
ID = 81A
RG = 2.7Ω
VGS = 10V f
VDD = 130V
ID = 81A, VDS =0V, VGS = 10V
TJ = 25°C, IS = 81A, VGS = 0V f
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250μA
Reference to 25°C, ID = 5mAc
VGS = 10V, ID = 81A f
VDS = VGS, ID = 250μA
VDS = 200V, VGS = 0V
VDS = 200V, VGS = 0V, TJ = 125°C
MOSFET symbol
showing the
VDS = 100V
Conditions
VGS = 10V f
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 160V h
VGS = 0V, VDS = 0V to 160V g
Conditions
VDS = 50V, ID = 81A
ID = 81A
VGS = 20V
VGS = -20V
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 81A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
0
4000
8000
12000
16000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 40 80 120 160 200
QG Total Gate Charge (nC)
0
4
8
12
16
VGS, Gate-to-Source Voltage (V)
VDS= 160V
VDS= 100V
VDS= 40V
ID= 81A
3.0 4.0 5.0 6.0 7.0 8.0 9.0
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current
(Α)
VDS = 50V
60μs PULSE WIDTH
TJ = 25°C
TJ = 175°C
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
60μs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
60μs PULSE WIDTH
Tj = 175°C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
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Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
0.0 0.5 1.0 1.5
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
25 50 75 100 125 150 175
TC , CaseTemperature (°C)
0
20
40
60
80
100
120
140
ID , Drain Current (A)
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
190
200
210
220
230
240
250
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
040 80 120 160 200
VDS, Drain-to-Source Voltage (V)
0
2
4
6
8
10
12
14
Energy (μJ)
0.1 1 10 100 1000
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
DC
25 50 75 100 125 150 175
Starting TJ, Junction Temperature (°C)
0
500
1000
1500
2000
2500
EAS, Single Pulse Avalanche Energy (mJ)
I D
TOP 18A
24A
BOTTOM 81A
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Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 14. Typical Avalanche Current vs.Pulsewidth
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z
thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W)
τι (sec)
0.063359 0.000278
0.110878 0.005836
0.114838 0.053606
τ
J
τ
J
τ
1
τ
1
τ
2
τ
2
τ
3
τ
3
R
1
R
1
R
2
R
2
R
3
R
3
τ
τ
C
Ci= τi/Ri
Ci= τi/Ri
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
200
400
600
800
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 81A
R T =125“C --- T = 25‘s _ lntemofiona‘ IEZR Rectifier 44 125‘0 - - 7 25%: _ R T =125‘c T = 25% _ R T =125“C --- T =25*c
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Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt
Fig. 20 - Typical Stored Charge vs. dif/dt
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
ID = 1.0mA
ID = 250μA
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
10
20
30
40
50
60
70
IRRM - (A)
IF = 52A
VR = 100V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
10
20
30
40
50
60
70
IRRM - (A)
IF = 81A
VR = 100V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
1000
2000
3000
4000
5000
QRR - (nC)
IF = 52A
VR = 100V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
0
1000
2000
3000
4000
5000
QRR - (nC)
IF = 81A
VR = 100V
TJ = 125°C
TJ = 25°C
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Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Inductor Current
D.U.T. VDS
ID
IG
3mA
VGS
.3μF
50KΩ
.2μF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
VGS
\, [ix 2 at )W m on _, i i m m m rai was i, n: aim mi)”. n x r T niw u ULERANCD mm W w. HWLLLD itx Li Y mm mtg w: M , w Dimmsnns wt, '[n A mm am in my Iniernoiionoi 1:211 Reciifier :u: w 5» i394 um, r m mm W ' r w m 'rnvim mnmr nr w p 3 us m a: m: vm ‘MH A mm m H‘LE )tm mm , Wit errrr 2m e T 3: , "' " I W me i J n i. L; ‘1 ‘ :1 as + t , us HP ._ m , g, , mt/ \ _ A / L \m p.“ 4 TO-247AC Part Marking Information EXAMPLE THiSISANiRFPESO ww Assn/aw toi com 5657 MERNAnoN/st ASSEMBLEDONWWSS. 2013] ”EU”? iNiHE ASSEMBLVUNE‘H“ LOGO i . ASSENBW Naiev'P inasgvbivilnevmmm LOT mm “LmFreé‘ TO-247AC packages ave not recommended tor Surlace Mount Application. O ii'IFPE3D I don mu as 57 Note: For the most current drawing please refer Io IR website at It“Ezllwwwtirl'tmmlpackage/ PART NU MBER DATE some VEAR l = 20131 WEEKS LiNE H Data and specifications subject to change Without notice. This product has been designed and quaiified for the Industrial market. Quaiification Standards can be iound on IR's Web site. Iniemoiionol 122R Rectifier IR WORLD HEADQUARTERS: 233 Kansas St., Ei Segundo, Calilomia 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact inlormation. 09/08 www.irf.com
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Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/08
TO-247AC packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-247AC Part Marking Information
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
LINE H
INTERNATIONAL
LOGO
RECTIFIER
AS S E MB L Y
56 57
IRFPE30
135H
YEAR 1 = 2001
DAT E CODE
PART NUMBER
indi cates "L ead-F r ee" WEEK 35
LOT CODE
IN THE ASSEMBLY LINE "H"
ASS E MBLED ON WW 35, 2001
Note: "P" in ass embly line position
EXAMPLE:
WI T H AS S E MB L Y
THIS IS AN IRFPE30
LOT CODE 5657