RoHS (A @ Halogen-Free 212 eGaN' FETs are supplied nnly in
eGaN® FET DATASHEET EPC2212
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EPC2212 eGaN® FETs are supplied only in
passivated die form with solder bars.
Die size: 2.1 x 1.6 mm
Applications
Lidar/Pulsed Power Applications
High Power Density DC-DC Converters
Class-D Audio
High Intensity Headlamps
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
EPC2212 - Automotive 100 V (D-S) Enhancement
Mode Power Transistor
VDS , 100 V
RDS(on) , 13.5 mΩ
ID , 18 A
AEC-Q101
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 100 V
ID
Continuous (TA = 25°C) 18 A
Pulsed (25°C, TPULSE = 300 µs) 75
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction-to-Case
2
°C/W RθJB
Thermal Resistance, Junction-to-Board
4
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
69
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA 100 V
IDSS Drain-Source Leakage VDS = 100 V, VGS = 0 V 10 250 µA
IGSS
Gate-to-Source Forward Leakage VGS = 6 V, TJ = 25°C 0.005 1.8 mA
Gate-to-Source Forward Leakage#VGS = 6 V, TJ = 125°C 0.015 3 mA
Gate-to-Source Reverse Leakage VGS = -4 V 10 250 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA 0.7 1 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 11 A 10 13.5
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET EPC2212
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Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance#
VDS = 50 V, VGS = 0 V
339 407
pF
CRSS Reverse Transfer Capacitance 3
COSS Output Capacitance#238 357
COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 0 to 50 V, VGS = 0 V 292
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 359
RGGate Resistance 0.4 Ω
QGTotal Gate Charge#VDS = 50 V, VGS = 5 V, ID = 11 A 3.2 4
nC
QGS Gate-to-Source Charge
VDS = 50 V, ID = 11 A
0.9
QGD Gate-to-Drain Charge 0.6
QG(TH) Gate Charge at Threshold 0.55
QOSS Output Charge#VDS = 50 V, VGS = 0 V 18 27
QRR Source-Drain Recovery Charge 0
ID – Drain Current (A)
VDS – Drain-to-Source Voltage (V)
60
40
20
0
40
30
20
10
0
40
30
20
10
0
60
40
20
0
1.0 1.5 2.0 2.5 3.0
VGS
GS
GS
GS
= 5 V
V = 4 V
V = 3 V
V = 2 V
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
RDS(on) – Drain to Source Resistance (mΩ)
RDS(on) – Drain to Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
2.5 2.0 3.0 3.5 4.0 4.5 5.0
VGS Gate-to-Source Voltage (V)
2.5 2.0 3.0 3.5 4.0 4.5 5.0
ID = 11 A
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics
Figure 3: RDS(on) vs. VGS for Various Drain Currents Figure 4: RDS(on) vs. VGS for Various Temperatures
0 0.5
ID = 6 A
ID = 12 A
ID = 18 A
ID = 24 A
All measurements were done with substrate connected to source.
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2212
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VGS Gate to Source Voltage (V)
QG – Gate Charge (nC)
5
4
3
2
1
00 1 2 3 4
ID = 11 A
VDS = 50 V
Figure 7: Gate Charge
Capacitance (pF)
600
500
400
300
200
100
00
Figure 5a: Capacitance (Linear Scale)
Capacitance (pF)
10
100
1000
1
25 50 75 100 0 25 50 75 100
0 20 40 60 80 100
Figure 5b: Capacitance (Log Scale)
EOSS — COSS Stored Energy (µJ)
VDS — Drain-to-Source Voltage (V)
QOSS — Output charge (nC)
30
25
20
15
10
5
0
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
Figure 6: Output Charge and COSS Stored Energy
VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
60
40
20
0
Figure 9: Normalized On-State Resistance vs. TemperatureFigure 8: Reverse Drain-Source Characteristics
Normalized On-State Resistance RDS(on)
0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 11 A
VGS = 5 V
25˚C
VGS = 0 V
125˚C
FL—
eGaN® FET DATASHEET EPC2212
EPCPOWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 4
Figure 11: Transient Thermal Response Curves
tp, Rectangular Pulse Duration, seconds
Z
θJB
, Normalized Thermal Impedance
0.5
0.05
0.02
Single Pulse
0.01
0.1
0.2
Duty Cycle:
Junction-to-Board
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
P
DM
t
1
t
2
10
-5
10
-4
10
-3
10
-2
10
-1
1 10
+1
1
0.1
0.01
0.001
0.0001
t
p
, Rectangular Pulse Duration, seconds
Z
θJC
, Normalized Thermal Impedance
0.5
0.1
0.02
0.05
Single Pulse
0.01
0.2
Duty Cycle:
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
P
DM
t
1
t
2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
1
1
0.1
0.01
0.001
0.0001
Figure 12: Safe Operating Area
0.1
1
10
100
0.1 1 10 100
ID – Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
100 ms
10 ms
1 ms
100 µs
Pulse Width
1 ms
100 µs
250 µs
Figure 9: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 3 mA
Figure 10: Normalized Threshold Voltage vs. Temperature
eGaN® FET DATASHEET EPC2212
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2212
YYYY
ZZZZ
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7”reel
7” reel
a
d e f g
c
b
EPC2212 (note 1)
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05
g 1.5 1.5 1.6
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
DIE MARKINGS
2212
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2212 2212 YYYY ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
<—> 4—» x4 ‘ I I e g UVVUV 400 ms we: Q ' 400 mu 052 m2 Si t
eGaN® FET DATASHEET EPC2212
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Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
1362
802
1632
560
180 180
X3
2106
X4
X2
3 4 5 61
2
RECOMMENDED
LAND PATTERN
(units in µm)
Pad no. 1 is Gate;
Pads no. 3, 5 are Drain;
Pads no. 4, 6 are Source;
Pad no. 2 is Substrate.*
*Substrate pin should be connected to Source
The land pattern is solder mask defined.
DIE OUTLINE
Solder Bar View
Side View
DIM MICROMETERS
MIN Nominal MAX
A2076 2106 2136
B1602 1632 1662
c1379 1382 1385
d577 580 583
e235 250 265
f195 200 205
g400 400 400
B
A
d
X2
c
e g
3 4 5 6
g
X3
f f
2
1
X4
815 Max
100 +/- 20
Seating Plane
(685)
Recommended stencil should be 4mil (100 µm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
RECOMMENDED
STENCIL DRAWING
(measurements in µm)
Pad no. 1 is Gate;
Pads no. 3, 5 are Drain;
Pads no. 4, 6 are Source;
Pad no. 2 is Substrate. *
*Substrate pin should be connected to Source
1362
802
1632
560
180 180
2106
X2
3 4 5 61
2
Information subject to
change without notice.
Revised April, 2021

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