SN74CB3Q3245GQNR Datasheet by Texas Instruments

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FEATURES
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
NC - No internal connection
RGY PACKAGE
(TOP VIEW)
1 20
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
OE
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A5
A6
A7
A8
B8 V
GND
CC
NC
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
Data and Control Inputs Provide UndershootClamp DiodesHigh-Bandwidth Data Path(up to 500 MHz
(1)
)Low Power Consumption (I
CC
= 1 mA Typical)Equivalent to IDTQS3VH384 Device V
CC
Operating Range From 2.3 V to 3.6 V5-V Tolerant I/Os With Device Powered Up or Data I/Os Support 0- to 5-V Signaling LevelsPowered Down (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)Low and Flat ON-State Resistance (r
on
)Control Inputs Can Be Driven by TTL orCharacteristics Over Operating Range 5-V/3.3-V CMOS Outputs(r
on
= 4 Typ)
I
off
Supports Partial-Power-Down ModeRail-to-Rail Switching on Data I/O Ports Operation
– 0- to 5-V Switching With 3.3-V V
CC
Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II 0- to 3.3-V Switching With 2.5-V V
CC
ESD Performance Tested Per JESD 22Bidirectional Data Flow With Near-ZeroPropagation Delay – 2000-V Human-Body Model(A114-B, Class II)Low Input/Output Capacitance MinimizesLoading and Signal Distortion – 1000-V Charged-Device Model (C101)(C
io(OFF)
= 3.5 pF Typ)
Supports Both Digital and AnalogFast Switching Frequency (f
OE
= 20 MHz Max) Applications: PCI Interface, Differential SignalInterface, Memory Interleaving, Bus Isolation,(1) For additional information regarding the performancecharacteristics of the CB3Q family, refer to the TI application
Low-Distortion Signal Gatingreport, CBT-C, CB3T, and CB3Q Signal-Switch Families,literature number SCDA008.
The SN74CB3Q3245 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage ofthe pass transistor, providing a low and flat ON-state resistance (r
on
). The low and flat ON-state resistance allowsfor minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The devicealso features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.Specifically designed to support high-bandwidth applications, the SN74CB3Q3245 provides an optimizedinterface solution ideally suited for broadband communications, networking, and data-intensive computingsystems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQN PACKAGE
(TOP VIEW)
1 2 3 4
A
B
C
D
E
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
The SN74CB3Q3245 is organized as an 8-bit bus switch with a single output-enable ( OE) input. When OE is low,the bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports.When OE is high, the bus switch is OFF and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry prevents damagingcurrent backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Tape and reel SN74CB3Q3245RGYR BU245
SSOP (QSOP) – DBQ Tape and reel SN74CB3Q3245DBQR CB3Q3245
Tube SN74CB3Q3245PW–40 °C to 85 °C TSSOP – PW BU245Tape and reel SN74CB3Q3245PWR
TVSOP – DGV Tape and reel SN74CB3Q3245DGVR BU245
VFBGA – GQN Tape and reel SN74CB3Q3245GQNR BU245
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
TERMINAL ASSIGNMENTS
(1)
1 2 3 4
AA1 NC V
CC
OE
BA3 B2 A2 B1
CA5 A4 B4 B3
DA7 B6 A6 B5
EGND A8 B8 B7
(1) NC - No internal connection
FUNCTION TABLE
INPUT INPUT/OUTPUT
FUNCTIONOE A
L B A port = B port
H Z Disconnect
2
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A1 SW B1
A8
OE
SW B8
2
9
19
18
11
Pin numbers shown are for the DBQ, DGV, PW, and RGY packages.
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A
EN(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
VCC
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
3
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 V
V
IN
Control input voltage range
(2) (3)
–0.5 7 V
V
I/O
Switch I/O voltage range
(2) (3) (4)
–0.5 7 V
I
IK
Control input clamp current V
IN
< 0 –50 mA
I
I/OK
I/O port clamp current V
I/O
< 0 –50 mA
I
IO
ON-state switch current
(5)
±64 mA
Continuous current through V
CC
or GND ±100 mA
DBQ package
(6)
68
DGV package
(6)
92
θ
JA
Package thermal impedance GQN package
(6)
78 °C/W
PW package
(6)
83
RGY package
(7)
37
T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground, unless otherwise specified.(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(4) V
I
and V
O
are used to denote specific conditions for V
I/O
.(5) I
I
and I
O
are used to denote specific conditions for I
I/O
.(6) The package thermal impedance is calculated in accordance with JESD 51-7.(7) The package thermal impedance is calculated in accordance with JESD 51-5.
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 V
V
CC
= 2.3 V to 2.7 V 1.7 5.5V
IH
High-level control input voltage VV
CC
= 2.7 V to 3.6 V 2 5.5
V
CC
= 2.3 V to 2.7 V 0 0.7V
IL
Low-level control input voltage VV
CC
= 2.7 V to 3.6 V 0 0.8
V
I/O
Data input/output voltage 0 5.5 V
T
A
Operating free-air temperature –40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
(1)
Switching Characteristics
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(2)
MAX UNIT
V
IK
V
CC
= 3.6 V, I
I
= –18 mA –1.8 V
I
IN
Control inputs V
CC
= 3.6 V, V
IN
= 0 to 5.5 V ±1µA
V
O
= 0 to 5.5 V, Switch OFF,I
OZ
(3)
V
CC
= 3.6 V, ±1µAV
I
= 0, V
IN
= V
CC
or GND
I
off
V
CC
= 0, V
O
= 0 to 5.5 V, V
I
= 0 1 µA
I
I/O
= 0,I
CC
V
CC
= 3.6 V, V
IN
= V
CC
or GND 1 2 mASwitch ON or OFF,
I
CC
(4)
Control inputs V
CC
= 3.6 V, One input at 3 V, Other inputs at V
CC
or GND 30 µA
V
CC
= 3.6 V, A and B ports open,Per control mA/I
CCD
(5)
0.30 0.35input MHzControl input switching at 50% duty cycle
C
in
Control inputs V
CC
= 3.3 V, V
IN
= 5.5 V, 3.3 V, or 0 2.5 3.5 pF
Switch OFF,C
io(OFF)
V
CC
= 3.3 V, V
I/O
= 5.5 V, 3.3 V, or 0 3.5 5 pFV
IN
= V
CC
or GND,
Switch ON,C
io(ON)
V
CC
= 3.3 V, V
I/O
= 5.5 V, 3.3 V, or 0 9 11 pFV
IN
= V
CC
or GND,
V
I
= 0, I
O
= 30 mA 4 8V
CC
= 2.3 V,TYP at V
CC
= 2.5 V
V
I
= 1.7 V, I
O
= –15 mA 4.5 9r
on
(6)
V
I
= 0, I
O
= 30 mA 4 6V
CC
= 3 V
V
I
= 2.4 V, I
O
= –15 mA 4 8
(1) V
IN
and I
IN
refer to control inputs. V
I
, V
O
, I
I
, and I
O
refer to data pins.(2) All typical values are at V
CC
= 3.3 V (unless otherwise noted), T
A
= 25 °C.(3) For I/O ports, the parameter I
OZ
includes the input leakage current.(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (seeFigure 2 ).(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance isdetermined by the lower of the voltages of the two (A or B) terminals.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 )
V
CC
= 2.5 V V
CC
= 3.3 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX
f
OE
(1)
OE A or B 10 20 MHz
t
pd
(2)
A or B B or A 0.12 0.20 ns
t
en
OE A or B 1.5 7.5 1.5 6.5 ns
t
dis
OE A or B 1 6.5 1 6.5 ns
(1) Maximum switching frequency for control input (V
O
> V
CC
, V
I
= 5 V, R
L
1 M , C
L
= 0)(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).
5
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0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ron - ON-State Resistance -
VI - V
TYPICAL ron
vs
VI
VCC = 3.3 V
TA = 25°C
IO = -15 mA
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
Figure 1. Typical r
on
vs V
I
Figure 2. Typical I
CC
vs OE Switching Frequency
6
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PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
tPLH tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOH
VOL
0 V
VOL + V
VOH − V
0 V
Output
Control
(VIN)
VCC
VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50
VG1
VCC
DUT
50
VIN
50
VG2 50
VI
TEST RL
S1 V
CL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
VCC VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
2 × VCC
2 × VCC
GND
GND
500
500
500
500
500
500
VCC or GND
VCC or GND
GND
GND
VCC
VCC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2 VCC/2
VCC/2
VO
SN74CB3Q3245
8-BIT FET BUS SWITCH2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS124B – JULY 2003 – REVISED MARCH 2005
Figure 3. Test Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74CB3Q3245RGYRG4 ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BU245
SN74CB3Q3245DBQR ACTIVE SSOP DBQ 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 CB3Q3245
SN74CB3Q3245DGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU245
SN74CB3Q3245PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU245
SN74CB3Q3245PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU245
SN74CB3Q3245PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BU245
SN74CB3Q3245RGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 BU245
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension destgned to accommodate the component with ED Dimension destgned to accommodate the component \engm K0 Dimenslun destgneo to accommodate the component thickness , w OveraH wtdm loe earner tape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74CB3Q3245DBQR SSOP DBQ 20 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74CB3Q3245DGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74CB3Q3245PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74CB3Q3245RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74CB3Q3245DBQR SSOP DBQ 20 2500 853.0 449.0 35.0
SN74CB3Q3245DGVR TVSOP DGV 20 2000 367.0 367.0 35.0
SN74CB3Q3245PWR TSSOP PW 20 2000 853.0 449.0 35.0
SN74CB3Q3245RGYR VQFN RGY 20 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Dec-2020
Pack Materials-Page 2
MECHANICAL DATA ‘LAS HC S‘WALLiC‘L 1LN¥PAC A AH Hnec' dimensmrs c'e m mc'ves ['m‘hmeters) Th5 drawer ‘5 sumac: :0 change mm: Home, Body dwmcnswons do not mcmae mom flash or cromsm m m exceed 0006 (055) per 3m FuHs mm JEDEC M07137 vunumn AD 4073301 fit/H 10/2008 Q; ”Dams INSI'RUMENTS www.1i.com
0.16 NOM 17 i Gage Plane 0,15 7|,20MAX 0,? PINS N 14 1s 20 24 as 43 56 DIM AMAX 3‘70 3.70 5‘10 5.10 700 9,00 11,40 AMIN 350 3,50 400 4,90 7‘70 9,50 11,20 407325| /E 03/00 *5 TEXAS INSTRUMENTS p057 omca aox $55303 - DALLAS IEXAS 752s5
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA ‘m‘ ,vm 7 F ‘ a 7 , >4/_)(/7k;/’u/, J‘ AJ‘C JMAH LIJ N NO’ES' A AH Hnec' dimensmrs c'e m m'\\me(er5 Dwmens'amnq cnd tu‘ercwcmg per ASME VM 5M 1994, Tm drawer ‘5 sumac: :0 change wnrau: Home, Budy \evvgih Cues m m ca mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS Ww.ti.com
LAND PATTERN DATA PW (R7PDSOmGZO) PLAST‘C SMALL OUTLINE Exam ‘9 Board LG I“ F W Based on o stencii thickness oi .127mm (.oosinen). -—iiiiii‘fli*m -—iiiifi°fi°’i”ii ——U/,'Efli‘iiiiii -—HHHH1QXQBQHJH« A , Pad Geometry “\ 0,07 /’ ‘ ‘AH Arourig/ 421128475/6 08/15 NOTES: A. AH iineor dimensions are in miiiimeters. B. Inis drawing is subject to change without notice. c. Publication iPcr735i is recommended for aitemate design. D Laser cutting apertures witn trapezoidoi wuHs and oiso rounding earners wiii oiier aetter paste reieose. Customers should contact tneir board assembiy site (or stencii design recommendations. Reier to iPc—7525 (or otner stencii recommendations. E. Cusmmers shuuid Contact ‘heir hoard fubr‘icufiun site for solder musk tolerances beLween and nruund signal pads. {I} Tums INSTRUMENTS www.li.com
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VQFN - 1 mm max heightRGY 20
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
4225264/A
4‘ I - MW D , D1 E 1 Aw 7 7 fmccgcc@:L 7 7 , \ 7 m7 7 iU 7 fl 7 fl ‘7 ‘‘‘‘‘‘‘ fi m 7V6 7 m 7 33:35:33 L 7 7 7 7 D A4 LE7? vi 7
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PACKAGE OUTLINE
C
20X 0.30
0.18
2.05 0.1
20X 0.5
0.3
1.0
0.8
(0.2) TYP
0.05
0.00
14X 0.5
2X
3.5
2X 1.5
3.05 0.1
A3.65
3.35 B
4.65
4.35
VQFN - 1 mm max heightRGY0020A
PLASTIC QUAD FLATPACK - NO LEAD
4225320/A 09/2019
PIN 1 INDEX AREA
0.08 C
SEATING PLANE
1
912
10 11
20
19
PIN 1 ID 0.1 C A B
0.05
EXPOSED
THERMAL PAD
21
SYMM
SYMM
2
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
20X (0.6)
20X (0.24)
14X (0.5)
(2.05)
(3.05)
(4.3)
(0.75) TYP
(1.275)
(3.3)
(0.775)
(R0.05) TYP
( 0.2) TYP
VIA
VQFN - 1 mm max heightRGY0020A
PLASTIC QUAD FLATPACK - NO LEAD
4225320/A 09/2019
SYMM
1
9
10 11
12
2
19
20
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
21
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
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EXAMPLE STENCIL DESIGN
20X (0.6)
20X (0.24)
14X (0.5)
(3.3)
(4.3)
4X (0.92)
(0.77)
(0.75)
TYP
(R0.05) TYP
4X
(1.33)
(0.56)
VQFN - 1 mm max heightRGY0020A
PLASTIC QUAD FLATPACK - NO LEAD
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
21
1
9
10 11
12
2
19
20
SYMM
TYP
METAL
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
IMPORTANT NOTICE AND DISCLAIMER
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Copyright © 2020, Texas Instruments Incorporated

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