HMC1119 Datasheet by Analog Devices Inc.

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ANALOG DEVICES HMCIHS RRRRR emrudbu
0.25 dB LSB, 7-Bit, Silicon Digital
Attenuator, 0.1 GHz to 6.0 GHz
Data Sheet
HMC1119
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©20162018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Attenuation range: 0.25 dB LSB steps to 31.75 dB
Low insertion loss:
1.1 dB at 1.0 GHz
1.3 dB at 2.0 GHz
Typical step error: less than ±0.1 dB
Excellent attenuation accuracy: less than ±0.2 dB
Low phase shift error: 6° phase shift at 1.0 GHz
Safe state transitions
High linearity
1 dB compression (P1dB): 31 dBm typical
Input third-order intercept (IP3): 54 dBm typical
RF settling time (0.05 dB final RF output): 250 ns
Single supply operation: 3.3 V to 5.0 V
ESD rating: Class 2 (2 kV human body model (HBM))
24-lead, 4 mm × 4 mm LFCSP package: 16 mm2
APPLICATIONS
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
IF and RF designs
FUNCTIONAL BLOCK DIAGRAM
24 23 22 21 20 19
7 8 9 10 11 12
1
2
3
4
5
6
18
17
16
15
14
13
D0
V
DD
P/S
GND
ATTNIN
GND
SERNIN
CLK
LE
GND
ATTNOUT
PACKAGE
BASE
GND
GND
GND
GND
GND
GND
GND
GND
D6
D5
D4
D3
D2
D1
12962-001
SERIAL/
PARALLEL
CONTROL
7-BIT
DIGITAL
ATTENUATOR
Figure 1.
GENERAL DESCRIPTION
The HMC1119 is a broadband, highly accurate, 7-bit digital
attenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dB
attenuation control range in 0.25 dB steps.
The HMC1119 is implemented in a silicon process, offering
very fast settling time, low power consumption, and high ESD
robustness. The device features safe state transitions and is
optimized for excellent step accuracy and high linearity over
frequency and temperature range. The RF input and output are
internally matched to 50 Ω and do not require any external
matching components. The design is bidirectional; therefore,
the RF input and output are interchangeable.
The HMC1119 has an on-chip regulator that can support a wide
supply operating range from 3.3 V to 5.0 V with no performance
change in electrical characteristics. The HMC1119 incorporates a
driver that supports serial (3-wire) and parallel controls of the
attenuator.
The HMC1119 comes in a RoHS-compliant, compact, 4 mm ×
4 mm LFCSP package.
A fully populated evaluation board is available.
HMC1119 Data Sheet
Rev. C | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ....................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics..................................................................... 7
Typical Performance Characteristics ............................................. 8
Insertion Loss, Return Loss, State Error, Step Error, and
Relative Phase ................................................................................8
Input Power Compression and Third-Order Intercept ......... 10
Theory of Operation ...................................................................... 11
Serial Control Interface ............................................................. 11
RF Input Output ......................................................................... 11
Parallel Control Interface .......................................................... 12
Power-Up Sequence ................................................................... 12
Applications Information .............................................................. 13
Evaluation Printed Circuit Board ............................................ 13
Packaging and Ordering Information ......................................... 15
Outline Dimensions ................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
4/2018—Rev. B to Rev C
Changes to Figure 23 ...................................................................... 12
Change to PCB Description, Table 7 ............................................ 13
Updated Outline Dimensions ....................................................... 15
9/2017—Rev. A to Rev. B
Changed CP-24-16 to HCP-24-3 ................................. Throughout
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
8/2017—Re v. 0 to Rev. A
Added Timing Specifications Section ............................................. 4
Move d Table 2 .................................................................................... 4
Changes to Figure 5 and Figure 6 .................................................... 7
Changes to Serial Control Interface Section ............................... 11
Moved Figure 22 and Table 6 ........................................................ 11
Changes to Figure 23 ...................................................................... 12
Moved Parallel Control Interface Section, Direct Parallel Mode
Section, Latched Parallel Mode Section, Power-Up Sequence
Section, and Power-Up States Section ......................................... 12
Updated Outline Dimensions ....................................................... 15
9/2016—Revision 0: Initial Version
Data Sheet HMC1119
Rev. C | Page 3 of 15
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V to 5.0 V, TA = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.1 6.0 GHz
INSERTION LOSS 0.1 GHz to 1.0 GHz 1.1 1.8 dB
0.1 GHz to 2.0 GHz 1.3 2.0 dB
0.1 GHz to 4.0 GHz 1.6 2.3 dB
0.1 GHz to 6.0 GHz 2.0 2.8 dB
ATTENUATION 0.2 GHz to 6.0 GHz
Range Delta between minimum and
maximum attenuation states
31.75 dB
Accuracy Referenced to insertion loss; all
attenuation states
−(0.05 + 4%
of attenuation
setting)
+(0.05 + 4% of
attenuation
setting)
dB
Step Error All attenuation states ±0.1 dB
Overshoot Between all attenuation states ≤0.1 dB
RETURN LOSS All attenuation states
ATTNIN, ATTNOUT 1.0 GHz 23 dBm
2.0 GHz 22 dBm
4.0 GHz
dBm
6.0 GHz 17 dBm
RELATIVE PHASE 1.0 GHz 6 Degrees
2.0 GHz
Degrees
4.0 GHz 38 Degrees
6.0 GHz 58 Degrees
SWITCHING CHARACTERISTICS
tRISE, tFALL 10%/90% RF output 60 ns
tON, tOFF 50% CTL to 10%/90% RF output 150 ns
Settling Time 50% CTL to 0.05 dB final RF output 250 ns
50% CTL to 0.10 dB final RF output 200 ns
INPUT LINEARITY All attenuation states, 0.2 GHz to 6 GHz
0.1 dB Compression (P0.1dB) 30 dBm
1 dB Compression (P1dB) 31 dBm
Input Third-Order Intercept (IP3)
Two-tone input power = 16 dBm/tone,
∆f = 1 MHz
dBm
SUPPLY CURRENT (IDD) VDD = 3.3 V 0.3 mA
V
DD
= 5.0 V
mA
CONTROL VOLTAGE THRESHOLD <1 µA typical
Low VDD = 3.3 V 0 0.5 V
VDD = 5.0 V 0 0.8 V
High VDD = 3.3 V 2.0 3.3 V
VDD = 5.0 V 3.5 5.0 V
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range (VDD) 3.0 5.4 V
Digital Control Voltage Range For P/S, CLK, SERNIN, LE, D0 to D6 pins 0 VDD V
RF Input Power All attenuation states, TCASE = 85°C 24 dBm
Case Temperature (TCASE) −40 +85 °C
HMC1119 Data Sheet
Rev. C | Page 4 of 15
TIMING SPECIFICATIONS
See Figure 23 and Figure 24 for the timing diagrams.
Table 2.
Parameter Description Min Typ Max Unit
tSCK Minimum serial period, see Figure 23 70 ns
tCS Control setup time, see Figure 23 15 ns
tCH Control hold time, see Figure 23 20 ns
tLN LE setup time, see Figure 23 15 ns
tLEW Minimum LE pulse width, see Figure 24 10 ns
t
LES
Minimum LE pulse spacing, see Figure 23
630
ns
tCKN Serial clock hold time from LE, see Figure 23 0 ns
tPH Hold time, see Figure 24 10 ns
tPS Setup time, see Figure 24 2 ns
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Data Sheet HMC1119
Rev. C | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
RF Input Power (T
CASE
= 85°C)
25 dBm
Digital Control Inputs (P/S, CLK,
SERNIN, LE, D0 to D6)
−0.3 V to VDD + 0.5 V
Supply Voltage (VDD) −0.3 V to +5.5 V
Continuous Power Dissipation (PDISS) 0.31 W
Thermal Resistance (at Maximum
Power Dissipation)
156°C/W
Temperature
Channel Temperature 135°C
Storage −65°C to +150°C
Maximum Reflow Temperature 260°C (MSL3 Rating)
ESD Sensitivity (HBM) 2 kV (Class 2)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
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HMC1119 Data Sheet
Rev. C | Page 6 of 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D0
V
DD
P/S
GND
ATTNIN
GND
SERNIN
NOTES
1. THE EXPOSED PAD AND GND PINS MUST BE CONNECTED
TO RF DC GROUND.
CLK
LE
GND
ATTNOUT
GND
GND
GND
GND
GND
GND
GND
D6
D5
D4
D3
D2
D1
24 23 22 21 20 19
7 8 9 10 11 12
1
2
3
4
5
6
18
17
16
15
14
13
12962-002
HMC1119
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 19 to 24 D0, D6 to D1 Parallel Control Voltage Inputs. These pins attain the required attenuation (see Table 6). There is no internal
pull-up or pull-down on these pins; therefore, these pins must always be kept at a valid logic level (VIH or VIL)
and must not be left floating.
2 VDD Supply Voltage Pin.
3 P/S Parallel/Serial Control Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must
always be kept at a valid logic level (VIH or VIL) and must not be left floating. For parallel mode, set Pin 3 to low;
for serial mode, set Pin 3 to high.
4, 6 to 13, 15 GND Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board
(PCB) RF/dc ground. See Figure 4 for the GND interface schematic.
5 ATTNIN Attenuator Input. This pin is dc-coupled and matched to 50 Ω. A blocking capacitor is required. Select the
value of the capacitor based on the lowest frequency of operation. See Figure 5.
14 ATTNOUT Attenuator Output. This pin is dc-coupled and matched to 50 Ω.A blocking capacitor is required. Select the
value of the capacitor based on the lowest frequency of operation. See Figure 5.
16 LE Serial/Parallel Interface Latch Enable Input. There is no internal pull-up or pull-down on this pin; therefore,
this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of
Operation section for more information.
17 CLK Serial Interface Clock Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must
always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section
for more information.
18 SERNIN Serial interface Data Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must
always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section
for more information.
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
TELJmi,
Data Sheet HMC1119
Rev. C | Page 7 of 15
INTERFACE SCHEMATICS
V
DD
D0 TO D5
12962-021
Figure 3. D0 to D6 Interface
GND
12962-022
Figure 4. GND Interface
ATTNIN,
ATTNOUT
12962-023
Figure 5. ATTIN and ATTOUT Interface
V
DD
P/S, LE, CLK, SERNIN
12962-024
Figure 6. P/S, LE, CLK, and SERNIN Interface
f // M / / /// / rf
HMC1119 Data Sheet
Rev. C | Page 8 of 15
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE
–4
–3
–2
–1
0
0123456
+85°C
+25°C
–40°C
INSERTION LOSS (dB)
FREQUENCY (GHz)
12962-003
Figure 7. Insertion Loss vs. Frequency at Various Temperatures
0123456
FREQUENCY (GHz)
–50
–40
–30
–20
–10
0
INPUT RETURN LOSS (dB)
IL
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
12962-004
Figure 8. Input Return Loss (Major States Only)
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
2.0
0 4 32
812 16 20 24 28
STATE ERROR (dB)
ATTENUATION STATE (dB)
100MHz
200MHz
400MHz
500MHz
12962-007
Figure 9. State Error vs. Attentuation State, 0.1 GHz to 0.5 GHz
01234 5 6
FREQUENCY (GHz)
–35
–30
–25
–20
–15
–10
–5
0
NORMALIZED ATTENUATION (dB)
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
12962-005
Figure 10. Normalized Attenuation (Major States Only)
0123456
FREQUENCY (GHz)
–60
–50
–40
–30
–20
–10
0
OUTPUT RETURN LOSS (dB)
IL
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
12962-006
Figure 11. Output Return Loss (Major States Only)
–1
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1
STATE ERROR (dB)
0432
812 16 20 24 28
ATTENUATION STATE (dB)
1GHz
2GHz
3GHz
4GHz
5GHz
6GHz
12962-009
Figure 12. State Error vs. Attentuation State, 1 GHz to 6 GHz
Data Sheet HMC1119
Rev. C | Page 9 of 15
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
STATE ERROR (dB)
0123456
FREQUENCY (GHz)
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
12962-008
Figure 13. State Error vs. Frequency, Major States Only
–60
–40
–20
0
20
40
60
80
RELATIVE PHASE (deg)
FREQUENCY (GHz)
0123456
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
12962-011
Figure 14. Relative Phase vs. Frequency, Major States Only
0123456
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
STEP ERROR (dB)
FREQUENCY (GHz)
0.25dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31.75dB
12962-010
Figure 15. Step Error vs. Frequency, Major States Only
\\
HMC1119 Data Sheet
Rev. C | Page 10 of 15
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
15
20
25
30
35
40
P1dB (dBm)
FREQUENCY (GHz)
+85°C
+25°C
–40°C
00.2 0.4 0.6 0.8 1.0
12962-012
Figure 16. P1dB vs. Frequency at Various Temperatures, Minimum
Attentuation State, 0.05 GHz to 1 GHz
15
20
25
30
35
40
P0.1dB (dBm)
FREQUENCY (GHz)
00.2 0.4 0.6 0.8 1.0
+85°C
+25°C
–40°C
12962-013
Figure 17. P0.1dB vs. Frequency at Various Temperatures, Minimum
Attentuation State, 0.05 GHz to 1 GHz
FREQUENCY (GHz)
30
40
50
60
70
IP3 (dBm)
0.200.4 0.6 0.8 1.0
+85°C
+25°C
–40°C
12962-014
Figure 18. IP3 vs. Frequency at Various Temperatures, Minimum
Attentuation State, 0.1 GHz to 1 GHz
15
20
25
30
35
40
P1dB (dBm)
FREQUENCY (GHz)
01234 5 6
+85°C
+25°C
–40°C
12962-015
Figure 19. P1dB vs. Frequency at Various Temperatures, Minimum
Attentuation State, 0.05 GHz to 6 GHz
15
20
25
30
35
40
P0.1dB (dBm)
FREQUENCY (GHz)
0123456
+85°C
+25°C
–40°C
12962-016
Figure 20. P0.1dB vs. Frequency at Various Temperatures, Minimum
Attentuation State, 0.05 GHz to 6 GHz
FREQUENCY (GHz)
30
40
50
60
70
IP3 (dBm)
012 3 45 6
+85°C
+25°C
–40°C
12962-017
Figure 21. IP3 vs. Frequency at Various Temperatures, Minimum
Attentuation State, 0.1 GHz to 6 GHz
Data Sheet HMC1119
Rev. C | Page 11 of 15
THEORY OF OPERATION
The HMC1119 incorporates a 7-bit fixed attenuator array that
offers an attenuation range of 0.25 dB to 31.75 dB, with 0.25 dB
steps. An integrated driver provides both serial and parallel
mode control of the attenuator array (see Figure 22).
The HMC1119 can be in either serial or parallel mode control
by setting the P/S pin to high or low, respectively (see Table 5). The
7-bit data, loaded in either serial or parallel mode, then latches with
the control signal, LE, to determine the attenuator value.
Table 5. Mode Selection Table1
P/S Pin State
Control Mode
Low Parallel
High
Serial
1 The P/S pin must always be kept at a valid logic level (VIH or VIL) and must not
be left floating.
SERIAL CONTROL INTERFACE
The HMC1119 utilizes a 3-wire serial to parallel (SPI)
configuration, as shown in the serial mode timing diagram (see
Figure 23): serial data input (SERNIN), clock (CLK), and latch
enable (LE). The serial control interface activates when the
P/S pin is set to high.
In serial mode, the 7-bit SERNIN data is clocked MSB first on
rising CLK edges into the shift register; then, LE must be
toggled high to latch the new attenuation state into the device.
The LE must be set low to clock a set of 7-bit data into the shift
register because CLK is masked to prevent the attenuator value
from changing if LE is kept high.
In serial mode operation, both the serial control inputs (LE, CLK,
SERNIN) and the parallel control inputs (D0 to D6) must always be
kept at a valid logic level (VIH or VIL) and must not be left floating. It
is recommended to connect the parallel control inputs to ground
and to use pull-down resistors on all serial control input lines
if the device driving these input lines goes high impedance
during hibernation.
RF INPUT OUTPUT
The attenuator in the HMC1119 is bidirectional; the ATTNIN
and ATTNOUT pins are interchangeable as the RF input and
output ports. The attenuator is internally matched to 50 Ω at both
input and output; therefore, no external matching components
are required. The RF pins are dc-coupled; therefore, dc blocking
capacitors are required on RF lines.
SERNIN
D0
D Q
D1 D2 D3 D4 D5 D6
CLK
P/S SELECT
P/S
LE
RF
INPUT RF
OUTPUT
D Q D Q D Q D Q D Q D Q
7-BIT LATCH
0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB
12962-018
Figure 22. Attenuator Array Functional Block Diagram
Table 6. Truth Table
Digital Control Input1
Attenuation State (dB)
D6 D5 D4 D3 D2 D1 D0
Low Low Low Low Low Low Low 0 (reference)
Low Low Low Low Low Low High 0.25
Low Low Low Low Low High Low 0.5
Low Low Low Low High Low Low 1.0
Low Low Low High Low Low Low 2.0
Low Low High Low Low Low Low 4.0
Low High Low Low Low Low Low 8.0
High Low Low Low Low Low Low 16.0
High High High High High High High 31.75
1 Any combination of the control voltage input states shown in Table 6 provides an attenuation equal to the sum of the bits selected.
HMC1119 Data Sheet
Rev. C | Page 12 of 15
X
X
D6
MSB
[FIRST IN]
t
CS
t
CH
t
SCK
t
LES
t
CKN
t
LEW
t
LN
D5 D4 D3 D2 D1 D0 X
D[6:0]
NEXT WORD
X
LSB
[LAST IN]
12962-019
P/S
SERNIN
CLK
LE
Figure 23. Serial Control Timing Diagram
PARALLEL CONTROL INTERFACE
The parallel control interface has seven digital control input lines
(D6 to D0) to set the attenuation value. D6 is the most significant
bit (MSB) that selects the 16 dB attenuator stage, and D0 is the
least significant bit (LSB) that selects the 0.25 dB attenuator stage
(see Figure 22).
In parallel mode operation, both the serial control inputs (LE, CLK,
SERNIN) and the parallel control inputs (D0 to D6) must always be
kept at a valid logic level (VIH or VIL) and must not be left floating. It
is recommended to connect the serial control inputs to ground and
to use pull-down resistors on all parallel control input lines if
the device driving these input lines goes high impedance during
hibernation.
Setting P/S to low enables parallel mode. There are two modes of
parallel operation: direct parallel mode and latched parallel mode.
Direct Parallel Mode
For direct parallel mode, the latch enable (LE) pin must be kept
high. Change the attenuation state using the control voltage inputs
(D0 to D6) directly. This mode is ideal for manual control of the
attenuator and using hardware, switches, or a jumper.
Latched Parallel Mode
The latch enable (LE) pin must be low when changing the
control voltage inputs (D0 to D6) to set the attenuation state.
When the desired state is set, LE must be toggled high to transfer
the 7-bit data to the bypass switches of the attenuator array, then
toggled low to latch the change into the device (see Figure 24).
LE
D6 TO D0
P/S
XX
X
t
LEW
t
PH
t
PS
D[6:0]
PARALLEL
CONTROL
12962-020
Figure 24. Latched Parallel Mode Timing Diagram
POWER-UP SEQUENCE
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up the digital control inputs (the relative order of
the digital control inputs is not important).
4. Power up the RF input.
For latched parallel mode operation, LE must be toggled. The
relative order of the digital inputs is not important as long as the
inputs are powered up after GND and VDD.
Power-Up States
The logic state of the device is at maximum attenuation when, at
power up, LE is set to low. The attenuator latches in the desired
power-up state approximately 200 ms after power up.
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Data Sheet HMC1119
Rev. C | Page 13 of 15
APPLICATIONS INFORMATION
EVALUATION PRINTED CIRCUIT BOARD
The schematic of the evaluation board, EV2HMC1119LP4M, is
shown in Figure 25. The PCB is four-layer material with a copper
thickness of 0.7 mils on each layer. Each copper layer is separated
with a dielectric material. The top dielectric material is 10-mil
RO4350 with a typical dielectric constant of 3.48. The middle
and bottom dielectric materials are FR-4 material, used for
mechanical strength and to meet the overall board thickness
of approximately 62 mils, which allows SMA connectors to be
slipped in at board edges.
All RF and dc traces are routed on the top copper layer. The RF
transmission lines are designed using coplanar waveguide model
(CPWG) with a width of 18 mils, spacing of 17 mils, and dielectric
thickness of 10 mils to maintain 50 Ω characteristic impedance.
The inner and bottom layers are solid ground planes. For optimal
electrical and thermal performance, an ample number of vias are
populated around the transmission lines and under the package
exposed pad. The evaluation board layout serves as a recommenda-
tion for the optimal performance on both electrical and thermal
aspects.
12962-026
Figure 25. EV2HMC1119LP4M Evaluation PCB
Table 7. Bill of Materials
Item Value1 Description Manufacturer2
J1, J2
PCB mount SMA connector
J3 18-pin dc connector
TP1, TP2 Through hole mount test point
C1, C3 100 pF Capacitor, 0402 package
C6 10 μF Capacitor, 0603 package
C7 1000 pF Capacitor, 0402 package
R1 to R11
0 Ω
Resistor, 0402 package
R12 to R25 100 kΩ Resistor, 0402 package
SW1, SW2 SPDT four-position DIP switch
U1 HMC1119 digital attenuator Analog Devices, Inc.
PCB3 600-01280-00-1 evaluation PCB EV2HMC1119LP4M4 from Analog Devices
1 Blank cells in the Value column indicate that there is no specific value recommendation for the listed component.
2 Blank cells in the Manufacturer column indicate that there is no specific manufacturer recommendation for the listed component.
3 Circuit board material is Arlon 25FR.
4 Reference this number when ordering the full evaluation PCB. See the Ordering Guide section.
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HMC1119 Data Sheet
Rev. C | Page 14 of 15
12962-027
Figure 26. Applications Circuit
ANALOG DEVICES www.analng.num
Data Sheet HMC1119
Rev. C | Page 15 of 15
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
BOTTOM VIEW
TOP VIEW
SIDE VIEW
4.10
4.00 SQ
3.90
0.95
0.85
0.75 0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
12-08-2017-C
0.30
0.25
0.18
0.20 MIN
2.85
2.70 SQ
2.55
EXPOSED
PAD
PKG-04940
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 27. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(HCP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
HMC1119LP4ME 40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] HCP-24-3
HMC1119LP4METR −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] HCP-24-3
EV2HMC1119LP4M Evaluation Board
1 All models are RoHS compliant.
2 See the Absolute Maximum Ratings section.
©20162018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12962-0-4/18(C)

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