DSC1103,23 Datasheet by Microchip Technology

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MICRQICHIP DSC1103/23
2017-2018 Microchip Technology Inc. DS20005745B-page 1
DSC1103/23
Features
Low RMS Phase Jitter: <1 ps (typ.)
High Stability: ±10 ppm, ±20 ppm, ±25 ppm,
±50 ppm
Wide Temperature Range:
- Ext. Industrial –40°C to +105°C
- Industrial –40°C to +85°C
- Ext. Commercial –20°C to +70°C
High Supply Noise Rejection: –50 dBc
Wide Frequency Range:
- 2.3 MHz – 460 MHz
Small Industry Standard Footprints
- 2.5 mm x 2.0 mm
- 3.2 mm x 2.5 mm
- 5.0 mm x 3.2 mm
- 7.0 mm x 5.0 mm
Excellent Shock and Vibration Immunity
- Qualified to MIL-STD-883
High Reliability
- 20x better MTF than quartz-based devices
Low Current Consumption
Supply Range of 2.25V to 3.63V
Standby and Output Enable Functions
Lead Free and RoHS-Compliant
Applications
Storage Area Networks
- SATA, SAS, Fibre Channel
Passive Optical Networks
- EPON, 10G-EPON, GPON, 10G-PON
HD/SD/SDI Video and Surveillance
PCI Express Gen 1/Gen 2/Gen 3
Display Port
General Description
The DSC1103 and DSC1123 series of high
performance oscillators utilizes a proven silicon MEMS
technology to provide excellent jitter and stability over
a wide range of supply voltages and temperatures. By
eliminating the need for quartz or SAW technology,
MEMS oscillators significantly enhance reliability and
accelerate product development, while meeting
stringent clock performance criteria for a variety of
communications, storage, and networking applications.
DSC1103 has a standby feature allowing it to
completely power-down when EN pin is pulled low. For
DSC1123, only the outputs are disabled when EN is
low. Both oscillators are available in industry standard
packages, including the smallest 2.5 mm x 2.0 mm,
and are drop-in replacements for standard 6-pin LVDS
crystal oscillators.
Block Diagram
Pin 6
V
DD
Pin 1
Enable
Pin 4
Output
Pin 3
GND
Divider
Driver
MEMS
Oscillator
PLL
Temp. Sensor &
Compensation
Circuitry
Pin 2
NC
Pin 5
Output
Low-Jitter Precision LVDS Oscillator
DSC1103/23
DS20005745B-page 2 2017-2018 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
Input Voltage .......................................................................................................................................–0.3V to VDD+0.3V
ESD Protection (HBM) ...............................................................................................................................................4 kV
ESD Protection (MM) ................................................................................................................................................400V
ESD Protection (CDM) ............................................................................................................................................1.5 kV
Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Specifications: VDD = 3.3V; TA = +25°C unless otherwise specified.
Parameters Sym. Min. Typ. Max. Units Conditions
Supply Voltage (Note 1)V
DD 2.25 3.63 V —
Supply Current IDD
— 0.095
mA
DSC1103, EN pin low; all
outputs disabled.
—2022 DSC1123, EN pin low; all
outputs disabled.
Frequency Stability f
——±10
ppm
Includes frequency
variations due to initial
tolerance, temp., and power
supply voltage.
——±20
——±25
——±50
Aging - First Year fY1 ±5 ppm One year at +25°C
Aging - After First Year fY2+ <±1 ppm/yr Year two and beyond at
+25°C
Start-up Time (Note 2)t
SU 5 ms T = +25°C
Input Logic Levels VIH 0.75 x VDD —— VInput logic high
VIL 0.25 x VDD Input logic low
Output Disable Time (Note 3)t
DA ——5 ns
Output Enable Time tEN
5 ms DSC1103
20 ns DSC1123
Enable Pull-Up Resistor
(Note 4)RPU —40kPull-up resistor exist.
LVDS Outputs
Supply Current IDD 29 32 mA Output enabled, RL = 100
Output Offset Voltage VOS 1.125 1.4 V R = 100 Differential
Delta Offset Voltage VOS ——50mV
Peak-to-Peak Output Swing VPP 350 mV Single-Ended
Note 1: VDD pin should be filtered with a 0.1 µF capacitor.
2: tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.
3: See the Output Waveform section and the Test Circuit for more information.
4: Output is enabled if pad is floated or not connected.
n5. VDD PER SRMS
2017-2018 Microchip Technology Inc. DS20005745B-page 3
DSC1103/23
Output Transition Rise/Fall
Time (Note 3)tR/tF—200— ps
20% to 80%
RL = 50, CL = 2 pF
Frequency f0
2.3 460 MHz
–20°C to +70°C &
–40°C to +85°C
3.3 460 –40°C to +105°C
Output Duty Cycle SYM 48 52 % Differential
Period Jitter JPER —2.5ps
RMS
Integrated Phase Noise JPH
—0.28
psRMS
200 kHz to 20 MHz
@156.25 MHz
—0.4100 kHz to 20 MHz
@156.25 MHz
—1.72 12 kHz to 20 MHz
@156.25 MHz
ELECTRICAL CHARACTERISTICS (CONTINUED)
Specifications: VDD = 3.3V; TA = +25°C unless otherwise specified.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: VDD pin should be filtered with a 0.1 µF capacitor.
2: tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.
3: See the Output Waveform section and the Test Circuit for more information.
4: Output is enabled if pad is floated or not connected.
DSC1103/23
DS20005745B-page 4 2017-2018 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS (Note 1)
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range
TA–20 +70 °C Ordering Option E
TA–40 +85 °C Ordering Option I
TA–40 +105 °C Ordering Option L
Junction Temperature TJ +150 °C —
Storage Temperature Range TS–55 +150 °C —
Soldering Temperature +260 °C 40 sec. max.
Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature, and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.
2017-2018 Microchip Technology Inc. DS20005745B-page 5
DSC1103/23
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
7x5 with Pad
Pin Number
7x5 w/o Pad
Pin Number
5x3.2
Pin Number
3.2x2.5
Pin Number
2x2.5
Pin
Name Description
1 1111ENEnable
2 2222NCDo not connect
3 3333GNDGround
4 4444OUTLVDS clock output +
5 5555OUTLVDS clock output
6 6666VDDSupply voltage
PAD————PADTie to Ground
TABLE 2-2: OUTPUT ENABLE MODES
EN Pin DSC1103 DSC1123
High Outputs Active Outputs Active
NC Outputs Active Outputs Active
Low Standby Outputs Disabled
FIGURE 3-1: Power Supply Rejection FIGURE 3-2: Phase Jirter (Integrated
DSC1103/23
DS20005745B-page 6 2017-2018 Microchip Technology Inc.
3.0 NOMINAL PERFORMANCE PARAMETERS
Unless otherwise specified, T = +25°C, VDD = 3.3V.
FIGURE 3-1: Power Supply Rejection
Ratio.
FIGURE 3-2: Phase Jitter (Integrated
Phase Noise).
-80
-70
-60
-50
-40
-30
-20
-10
0
0.1 1 10 100 1000 10000
Rejection (dBc)
Supply Noise Frequency (kHz)
50 mV
100 mV
0.0
0.5
1.0
1.5
2.0
2.5
0 200 400 600 800 1000
Phase Jitter (ps RMS)
Low-end of integration BW: x kHz to 20 MHz
156MHz-LVDS
212MHz-LVDS
320MHz-LVDS
410MHz-LVDS
j FIGURE 4-1: Typical Termination Scheme.
2017-2018 Microchip Technology Inc. DS20005745B-page 7
DSC1103/23
4.0 TERMINATION SCHEME
FIGURE 4-1: Typical Termination Scheme.
5.0 OUTPUT WAVEFORM
FIGURE 5-1: Output Waveform.
V
DD
0.1uF
100 100
2
34
5
6
V
IL
1/
f
o
Output
Enable
t
DA
t
EN
t
F
t
R
VIH
80
%
20%
50%
Output
830 mv
350 mV
LVDS 1000 LVDS v0.3 C FIGURE 6-1: Test Cimuit. L d— n‘ (i FIGURE 7-1: DSC1103/23 Recommended Board Layout.
DSC1103/23
DS20005745B-page 8 2017-2018 Microchip Technology Inc.
6.0 TEST CIRCUIT
FIGURE 6-1: Test Circuit.
7.0 RECOMMENDED BOARD LAYOUT
FIGURE 7-1: DSC1103/23 Recommended Board Layout.
1
34
6
5
2
4
2
3
6
1
Via to GND layer
Via to GND layer
Supply bypass
capacitor
2017-2018 Microchip Technology Inc. DS20005745B-page 9
DSC1103/23
8.0 SOLDER REFLOW PROFILE
60-150
Sec
20-40
Sec
60-180
Sec
8 min max
Pre heat
ReŇow
Cool
Time
Temperature (°C)
3
°
C/Sec Max.
6
°
C/Sec Max.
200
°
C
217
°
C
150
°
C
25
°
C
260
°
C
3
°
C/Sec Max.
60-150
Sec
20-40
Sec
60-180
Sec
8 min max
Pre heat
ReŇow
Cool
Time
Temperature (°C)
200
°
C
217
°
C
150
°
C
25
°
C
260
°
C
60-150
Sec
20-40
Sec
60-180
Sec
8 min max
Pre heat
ReŇow
Cool
Time
Temperature (°C)
200
°
C
217
°
C
150
°
C
25
°
C
260
°
C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/sec. max.
Preheat Time 150°C to 200°C 60-180 sec.
Time Maintained above 217°C 60-150 sec.
Peak Temperature 255°C to 260°C
Time within 5°C of Actual Peak 20-40 sec.
Ramp-Down Rate 6°C/sec. max.
Time 25°C to Peak Temperature 8 minutes max.
H J?
DSC1103/23
DS20005745B-page 10 2017-2018 Microchip Technology Inc.
9.0 PACKAGE MARKING INFORMATION
6-Lead VDFN 2.5 mm x 2.0 mm Package Outline and Recommended Land Pattern
RECOMMENDED LAND PATTERN
Dimension Limits
Units
C
Contact Pad Width (X4)
Contact Pad Spacing
Contact Pad Width (X2)
Contact Pitch
X2
X1
0.25
0.65
MILLIMETERS
0.825 BSC
MIN
E
MAX
1.45
Space Between Contacts (X3)
Space Between Contacts (X4)
G2
G1
0.60
0.38
Microchip Technology Drawing C04-3005A
NOM
6-Lead Very Thin Dual Flatpack No-Leads (J7A) - 2.5x2.0 mm Body [VDFN]
12
6
YContact Pad Length (X6) 0.85
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C
E
X1
X2
Y
G1
G2
SILK SCREEN
+i rm? : i \%/76W %// ‘ Elm 1 EEC 171—17 H ¥ SIDEVIEW ECU $ * +‘« L + ~~+w ; \ ! 1 | w» k ? LEM H ®®
2017-2018 Microchip Technology Inc. DS20005745B-page 11
DSC1103/23
B
A
0.05 C
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
1
N
2X TOP VIEW
SIDE VIEW
NOTE 1
0.10 C
0.08 C
Microchip Technology Drawing C04-1005A Sheet 1 of 2
2X
6X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
6-Lead Very Thin Dual Flatpack No-Leads (J7A) - 2.5x2.0 mm Body [VDFN]
D
E
A
A1
0.10 C A B
0.05 C
BOTTOM VIEW
12
N
2X b2
4X b1
5X L1
L2
e
2
DSC1103/23
DS20005745B-page 12 2017-2018 Microchip Technology Inc.
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-1005A Sheet 2 of 2
6-Lead Very Thin Dual Flatpack No-Leads (J7A) - 2.5x2.0 mm Body [VDFN]
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Pitch
Standoff
Units
Dimension Limits
A1
A
b1
e
L2
E
N
0.825 BSC
0.665
0.60
0.80
0.00
0.65
0.765
0.85
0.02
2.00 BSC
MILLIMETERS
MIN NOM
6
0.865
0.70
0.90
0.05
MAX
Overall Length D 2.50 BSC
Terminal Length L1 0.60 0.70 0.80
Terminal Width b2 0.20 0.25 0.30
2017-2018 Microchip Technology Inc. DS20005745B-page 13
DSC1103/23
6-Lead VDFN 3.2 mm x 2.5 mm Package Outline and Recommended Land Pattern
RECOMMENDED LAND PATTERN
Dimension Limits
Units
X1Contact Pad Width (X4)
Contact Pitch
MILLIMETERS
1.05 BSC
MIN
E
MAX
1.00
Contact Pad Length (X6)
Contact Pad Width (X2)
Y
X2
0.85
Microchip Technology Drawing C04-3007A
NOM
6-Lead Very Thin Plastic Dual Flatpack No-Lead (H5A) - 3.2x2.5 mm Body [VDFN]
SILK SCREEN
12
6
CContact Pad Spacing 1.60
Space Between Contacts (X4) G1 0.25
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C
E
X1
Y
X2
G
0.60
W—fl ECEIWWH SIDE VIEW a.07® c AI \ 005® c $ , W k 7: w W fiflimllw i WWW Fflj
DSC1103/23
DS20005745B-page 14 2017-2018 Microchip Technology Inc.
B
A
0.05 C
0.05 C
0.07 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
12
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
12
N
0.10 C
0.08 C
Microchip Technology Drawing C04-1007A Sheet 1 of 2
2X
6X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
6-Lead Very Thin Plastic Dual Flatpack No-Lead (H5A) - 3.2x2.5 mm Body [VDFN]
D
E
e
2X b2
4X b1
L
L1
A
A1
2017-2018 Microchip Technology Inc. DS20005745B-page 15
DSC1103/23
Microchip Technology Drawing C04-1007A Sheet 2 of 2
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
6-Lead Very Thin Plastic Dual Flatpack No-Lead (H5A) - 3.2x2.5 mm Body [VDFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Terminal Width
Pitch
Standoff
Units
Dimension Limits
A1
A
b2
b1
e
L
E
N
1.05 BSC
0.85
0.65
0.45
0.80
0.00
0.50
0.70
0.90
0.85
0.02
2.50 BSC
MILLIMETERS
MIN NOM
6
0.95
0.75
0.55
0.90
0.05
MAX
L1 0.10 REFTerminal Pullback
Overall Length D 3.20 BSC
TITLE 6 LEAD CDFN 5.0x3.2mm COL PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING n | CDFNSO32i6LDiPLi1 | UNIT IMM ”one mm m ehl'—‘ . (on: g fl F e 1 : g i i 3 3 o - mum ,zn nu Top View Bottom View mu m“\” ,, TOE m. Slde Vlew ‘ § m L,,J 110 mu Recommended Land Pattern NOTE- 1. * Pown Supply Decaupung Capacilur i: Icquited in Recon-mended Iannll‘amm. z Gum duukd rechngles nu Recommended Land Panem av: «111k! «mail opening 3. Red circltsinthmnmmdtdLaudPslkmmecnnalVIA. Nole. For me most cunem package drawings. please see the Micrucmp Packaging Specmcanen \ocated at nup /Avww.mmmcmpeom/packagmg.
DSC1103/23
DS20005745B-page 16 2017-2018 Microchip Technology Inc.
6-Lead CDFN 5.0 mm x 3.2 mm Package Outline and Recommended Land Pattern
4 F t 500 000/ ‘7,7 I
2017-2018 Microchip Technology Inc. DS20005745B-page 17
DSC1103/23
6-Lead VDFN 7.0 mm x 5.0 mm Package Outline and Recommended Land Pattern
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
1.90
2.90
MILLIMETERS
2.54 BSC
MIN
E
MAX
Contact Pad Length (X6)
Contact Pad Width (X6)
Y1
X1
1.35
1.50
Microchip Technology Drawing C04-3010A
NOM
6-Lead Very Thin Plastic Quad Flat, No Lead Package (H8A) - 7x5 mm Body [VDFN]
12
6
CContact Pad Spacing 3.70
Contact Pad to Center Pad (X2) G 0.20
Thermal Via Diameter (X6) V
Thermal Via Pitch EV
0.33
1.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
With 2.8x1.8 mm Exposed Pad
C
E
X1
Y1
X2
Y2
EV
EV ØV G
SILK SCREEN
_/; <—d—>r—|:| we; "1* ———— ' BI—fl /// 3 EEE $ I-l g fii SIDE VIEW m D2 9-..- 1 2‘ \ ; $ ® \ NOTE1/_:\§:\l _+_ _ __ $ \ A GXL ‘ T _ t ~\ #34 (9 g I \ BOTTOM VIEW Mmrocmp Tech
DSC1103/23
DS20005745B-page 18 2017-2018 Microchip Technology Inc.
B
A
0.20 C
0.20 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
12
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
12
N
0.10 C A B
0.10 C A B
0.10 C
Microchip Technology Drawing C04-1010A Sheet 1 of 2
2X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
6-Lead Very Thin Plastic Quad Flat, No Lead Package (H8A) - 7x5 mm Body [VDFN]
With 2.8x1.8 mm Exposed Pad
D
E
e
6X b
D2
E2
6X L (K)
A
A1
0.08 C
6X
2017-2018 Microchip Technology Inc. DS20005745B-page 19
DSC1103/23
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E2
e
L
E
N
2.54
1.70
1.00
1.35
0.80
0.00
1.40
1.10
1.80
0.85
0.02
5.00 BSC
MILLIMETERS
MIN NOM
6
1.90
1.20
1.45
0.90
0.05
MAX
K0.20 REF
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Overall Length
Exposed Pad Length
D
D2 2.70
7.00 BSC
2.80 2.90
Microchip Technology Drawing C04-1010A Sheet 2 of 2
6-Lead Very Thin Plastic Quad Flat, No Lead Package (H8A) - 7x5 mm Body [VDFN]
With 2.8x1.8 mm Exposed Pad
TITLE 6 LEAD CDFN 7.0x5.0mm COL PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING I | anmsrsLDrPLA UNIT | MM i pm iii a \ EN 6 ' U E C 3 EM JM mm 1 mm Top View Bottom w p... v1 m an. \ 4:- , i i E ,-'-,..:c.. Limos E Side View 2.51 El 7 7g Recommended [and Pattern NOTE: 1. * Pawn- Supply Bumbag Capacitor is “wed in Recommended Land Panam. 2. am" shadzd «muglcs in kccommuded Lmd Mun at: 501ng namii upcning. 3. Red circlesinkacwmmnndeandPanrmmthcrmleA. Note Forme mgsi cuireni package drawings. piease see the Microchip Packaging Speciiicaiion localed at Nip Him/vwmicruchip cum/packaging.
DSC1103/23
DS20005745B-page 20 2017-2018 Microchip Technology Inc.
6-Lead CDFN 7.0 mm x 5.0 mm Package Outline and Recommended Land Pattern
2017-2018 Microchip Technology Inc. DS20005745B-page 21
DSC1103/23
APPENDIX A: REVISION HISTORY
Revision A (March 2017)
Converted Micrel data sheet DSC1103/23 to
Microchip DS20005745A.
Minor text changes throughout.
Updated Package Marking Information to MCHP-
standard drawings where available.
Revision B (October 2018)
Added ±20 ppm stability references throughout
document.
Added Section 7.0, Recommended Board Layout.
DSC1103/23
DS20005745B-page 22 2017-2018 Microchip Technology Inc.
NOTES:
PART NO. X Dev 44x 4M X 7 xxx.xxxx _'_ be
2017-2018 Microchip Technology Inc. DS20005745B-page 23
DSC1103/23
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
a) DSC1103AE1-125.0000: Low-Jitter Precision LVDS
Oscillator, Enable/Standby,
7x5 VDFN, –20°C to +70°C,
±50ppm, 125MHz, 100/Tube
b) DSC1123BI2-400.0000T: Low-Jitter Precision LVDS
Oscillator, Enable/Disable,
5x3.2 CDFN, –40°C to +85°C,
±25ppm, 400MHz,
1,000/Reel
c) DSC1103CL5-074.2500: Low-Jitter Precision LVDS
Oscillator, Enable/Standby,
3.2x2.5 VDFN,
–40°C to +105°C, ±10 ppm,
74.25 MHz, 100/Tube
d) DSC1123DE1-082.5000T:Low-Jitter Precision LVDS
Oscillator, Enable/Disable,
2.5x2.0 VDFN,
–20°C to +70°C, ±50 ppm,
82.5 MHz, 1,000/Reel
e) DSC1103NI2-056.0000: Low-Jitter Precision LVDS
Oscillator, Enable/Standby,
7x5 CDFN (no center pad),
–40°C to +85°C, ±25 ppm,
56 MHz, 100/Tube
PART NO.
Device
Device: DSC11x3: Low-Jitter Precision LVDS Oscillator
Enable Modes: 0 = Enable/Standby
2 = Enable/Disable
Package: A = 7.0 mm x 5.0 mm VDFN
B = 5.0 mm x 3.2 mm CDFN
C = 3.2 mm x 2.5 mm VDFN
D = 2.5 mm x 2.0 mm VDFN
N = 7.0 mm x 5.0 mm CDFN (no center pad)
Temperature
Range:
E = –20°C to +70°C
I = –40°C to +85°C
L = –40°C to +105°C
Stability: 1=±50ppm
2=±25ppm
3=±20ppm
5=±10ppm
Frequency Code: xxx.xxxx = 2.3 MHz to 460 MHz (user-defined)
Packing: T = 1,000/Reel
(blank) = 100/Tube
X
Enable
xxx.xxxx
Frequency
Modes
X
Package
X
Temp.
X
Stability
X
Packing
Range
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the
Tape and Reel option.
(First 2
Digits)
3
Device
(Last
Digit)
DSC1103/23
DS20005745B-page 24 2017-2018 Microchip Technology Inc.
NOTES:
YSTEM
2017-2018 Microchip Technology Inc. DS20005745B-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017-2018, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-3790-1
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
6‘ ‘MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20005745B-page 26 2017-2018 Microchip Technology Inc.
AMERICAS
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