ATmega256/128/64RFR2 Datasheet by Microchip Technology

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AtmeE AVR Atmel:
1
8393C-MCU Wireless-09/14
ATmega256/128/64RFR2
8-bit
Microcontroller
with Low Power
2.4GHz
Transceiver for
ZigBee and
IEEE 802.15.4
ATmega256RFR2
ATmega128RFR2
ATmega64RFR2
8393C-MCU Wireless-09/14
Features
Network support by hardware assisted Multiple PAN Address Filtering
Advanced Hardware assisted Reduced Power Consumption
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
- 135 Powerful Instructions – Most Single Clock Cycle Execution
- 32x8 General Purpose Working Registers / On-Chip 2-cycle Multiplier
- Up to 16 MIPS Throughput at 16 MHz and 1.8V – Fully Static Operation
Non-volatile Program and Data Memories
- 256K/128K/64K Bytes of In-System Self-Programmable Flash
Endurance: 10’000 Write/Erase Cycles @ 125°C (25’000 Cycles @ 85°C)
- 8K/4K/2K Bytes EEPROM
Endurance: 20’000 Write/Erase Cycles @ 125°C (100’000 Cycles @ 25°C)
- 32K/16K/8K Bytes Internal SRAM
JTAG (IEEE std. 1149.1 compliant) Interface
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug Support
- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface
Peripheral Features
- Multiple Timer/Counter & PWM channels
- Real Time Counter with Separate Oscillator
- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor
- Master/Slave SPI Serial Interface
- Two Programmable Serial USART
- Byte Oriented 2-wire Serial Interface
Advanced Interrupt Handler and Power Save Modes
Watchdog Timer with Separate On-Chip Oscillator
Power-on Reset and Low Current Brown-Out Detector
Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
- High Power Amplifier support by TX spectrum side lobe suppression
- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm
- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
- 32 Bit IEEE 802.15.4 Symbol Counter
- SFD-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation
- Antenna Diversity and TX/RX control / TX/RX 128 Byte Frame Buffer
- Phase measurement support
PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4 GHz ISM Band
Hardware Security (AES, True Random Generator)
Integrated Crystal Oscillators (32.768 kHz & 16 MHz, external crystal needed)
I/O and Package
- 38 Programmable I/O Lines
- 64-pad QFN (RoHS/Fully Green)
Temperature Range: -40°C to 125°C Industrial
Ultra Low Power consumption (1.8 to 3.6V) for AVR & Rx/Tx: 10.1mA/18.6 mA
- CPU Active Mode (16MHz): 4.1 mA
- 2.4GHz Transceiver: RX_ON 6.0 mA / TX 14.5 mA (maximum TX output power)
- Deep Sleep Mode: <700nA @ 25°C
Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V range with integrated voltage regulators
Applications
ZigBee® / IEEE 802.15.4-2011/2006/2003 – Full and Reduced Function Device
General Purpose 2.4GHz ISM Band Transceiver with Microcontroller
RF4CE, SP100, WirelessHART, ISM Applications and IPv6 / 6LoWPAN
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ATmega256/128/64RFR2
1 Pin Configurations
Figure 1-1. Pinout ATmega256/128/64RFR2
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected
to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the
center pad is left unco
nnected, the package might loosen from the board. It is not recommended to
use the exposed paddle as a replacement of the regular AVSS pins.
2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization
results of other AVR microcontrollers and radio transceivers manufactured in a similar
process technology. Minimum and Maximum values will be available after the device is
characterized.
1
[PF3:ADC3:DIG4]
[PF2:ADC2:DIG2]
2
3
[PF5:ADC5:TMS]
[PF4:ADC4:TCK]
4
5
[PF7:ADC7:TDI]
[PF6:ADC6:TDO]
6
7
[RFP]
[AVSS_RFP]
8
9
[AVSS_RFN]
[RFN]
10
11
[RSTN]
[TST]
12
13
14
[RSTON]
[PG0:DIG3]
56
55
54
53
52
51
62
61
60
59
58
57
64
63
ATmega256/128/64RFR2
Exposed paddle: [AVSS]
[DVSS]
[PE0:RXD0:PCINT8]
[PE1:TXD0]
[PE2:XCK0:AIN0]
[CLKI]
[DEVDD]
[DVSS]
[PB0:SSN:PCINT0]
[PB1:SCK:PCINT1]
[PB2:MOSI:PDI:PCINT2]
[PB3:MISO:PDO:PCINT3]
[PB4:OC2A:PCINT4]
[PB5:OC1A:PCINT5]
[PB6:OC1B:PCINT6]
31
32
17
18
19
20
21
23
22
24
25
26
27
0
28
[PD3:TXD1:INT3]
[PD2:RXD1:INT2]
[PD1:SDA:INT1]
[PD0:SCL:INT0]
[DVSS]
[DEVDD]
[DVDD]
[DVDD]
[DVSS:DSVSS]
[PG5:OC0B]
[PG4:TOSC1]
[PG3:TOSC2]
[PD7:T0]
[PD6:T1]
42
41
40
39
38
37
36
35
34
33
48
47
46
45
15
16
[PG1:DIG1]
[PG2:AMR]
[PB7:OC0A:OC1C:PCINT7]
[DEVDD]
44
43
29
0
30
[PD5:XCK1]
[PD4:ICP1]
50
49
Index corner
[DEVDD]
[PE7:ICP3:INT7:CLKO]
[PE6:T3:INT6]
[PE5:O
C3C:INT5]
[PE4:OC3B:INT4]
[PE3:OC3A:AIN1]
[XTAL2]
[DVSS]
[PF1:ADC1]
[PF0:ADC0]
[AREF]
[AVSS]
[AVDD]
[EVDD]
[AVSS:ASVSS]
[XTAL1]
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ATmega256/128/64RFR2
3 Overview
The ATmega256/128/64RFR2 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4
GHz ISM band.
By executing powerful instructions in a single clock cycle, the device achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame
handling, outstanding receiver sensitivity and high transmit output power enabling a
very robust wireless communication.
3.1 Block Diagram
Figure 3-1 Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working
registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two
independent registers can be accessed with one single instruction executed in one
clock cycle. The resulting architecture is very code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers. The system includes
internal voltage regulation and an advanced power management. Distinguished by the
small leakage current it allows an extended operation time from battery.
The radio transceiver is a fully integrated ZigBee solution using a minimum number of
external components. It combines excellent RF performance with low cost, small size
and low current consumption. The radio transceiver includes a crystal stabilized
fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread
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ATmega256/128/64RFR2
Spectrum Signal (DSSS) processing with spreading and despreading. The device is
fully compatible with IEEE802.15.4-2011/2006/2003 and ZigBee standards.
The ATmega256/128/64RFR2 provides the following features: 256K/128K/64K Bytes of
In-System Programmable (ISP) Flash with read-while-write capabilities, 8K/4K/2K Bytes
EEPROM, 32K/16K/8K Bytes SRAM, up to 35 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), 6 flexible Timer/Counters with
compare modes and PWM, a 32 bit Timer/Counter, 2 USART, a byte oriented 2-wire
Serial Interface, a 8 channel, 10 bit analog to digital converter (ADC) with an optional
differential input stage with programmable gain, programmable Watchdog Timer with
Internal Oscillator, a SPI serial port, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the On-chip Debug system and programming and 6 software
selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the RC oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby
mode, both the main RC oscillator and the asynchronous timer continue to run.
Typical supply current of the microcontroller with CPU clock set to 16MHz and the radio
transceiver for the most important states is shown in the Figure 3-2 below.
Figure 3-2 Radio transceiver and microcontroller (16MHz) supply current
16,6mA
4,7mA
4,1mA
250nA
18,6mA
0
5
10
15
20
Deep Sleep SLEEP TRX_OFF RX_ON BUSY_TX
Radio transceiver and microcontroller (16MHz) supply current
I(DEVDD,EVDD) [mA]
1.8V
3.0V
3.6V
The transmit output power is set to maximum. If the radio transceiver is in SLEEP mode
the current is dissipated by the AVR microcontroller only.
In Deep Sleep mode all major digital blocks with no data retention requirements are
disconnected from main supply providing a very small leakage current. Watchdog timer,
MAC symbol counter and 32.768kHz oscillator can be configured to continue to run.
700
nA
RPC enabled 10.1mA
RPC disabled
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ATmega256/128/64RFR2
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
trough an SPI serial interface, by a conventional nonvolatile memory programmer, or by
on on-chip boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory.
Software in the boot Flash section will continue to run while the application Flash
section is updated, providing true Read-While-Write operation. By combining an 8 bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega256/128/64RFR2 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The ATmega256/128/64RFR2 AVR is supported with a full suite of program and system
development tools including: C compiler, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
3.2 Pin Descriptions
3.2.1 EVDD
External analog supply voltage.
3.2.2 DEVDD
External digital supply voltage.
3.2.3 AVDD
Regulated analog supply voltage (internally generated).
3.2.4 DVDD
Regulated digital supply voltage (internally generated).
3.2.5 DVSS
Digital ground.
3.2.6 AVSS
Analog ground.
3.2.7 Port B (PB7...PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.8 Port D (PD7...PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.9 Port E (PE7...PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
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current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.10 Port F (PF7...PF0)
Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port F output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port F pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port F also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.11 Port G (PG5…PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high
sink and source capability. However the driver strength of PG3 and PG4 is reduced
compared to the other port pins. The output voltage drop (VOH, VOL) is higher while the
leakage current is smaller. As inputs, Port G pins that are externally pulled low will
source current if the pull-up resistors are activated. The Port G pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port G also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.12 AVSS_RFP
AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.13 AVSS_RFN
AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.14 RFP
RFP is the positive terminal for the bi-directional, differential RF I/O port.
3.2.15 RFN
RFN is the negative terminal for the bi-directional, differential RF I/O port.
3.2.16 RSTN
Reset input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset.
3.2.17 RSTON
Reset output. A low level on this pin indicates a reset initiated by the internal reset
sources or the pin RSTN.
3.2.18 XTAL1
Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between
XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.
3.2.19 XTAL2
Output of the inverting 16MHz crystal oscillator amplifier.
3.2.20 AREF
Reference voltage output of the A/D Converter. In general this pin is left open.
3.2.21 TST
Programming and test mode enable pin. If pin TST is not used pull it to low.
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3.2.22 CLKI
Input to the clock system. If selected, it provides the operating clock of the
microcontroller.
3.3 Unused Pins
Floating pins can cause power dissipation in the digital input stage. They should be
connected to an appropriate source. In normal operation modes the internal pull-up
resistors can be enabled (in Reset all GPIO are configured as input and the pull-up
resistors are still not enabled).
Bi-directional I/O pins shall not be connected to ground or power supply directly.
The digital input pins TST and CLKI must be connected. If unused pin TST can be
connected to AVSS while CLKI should be connected to DVSS.
Output pins are driven by the device and do not float. Power supply pins respective
ground supply pins are connected together internally.
XTAL1 and XTAL2 shall never be forced to supply voltage at the same time.
3.4 Compatibility to ATmega128RFA1
Backward compatibility of the ATmega256/128/64RFR2 to the ATmega128RFA1 is
provided in most cases. However some incompatibilities may exist.
The ATmega256/128/64RFR2 uses the same package as the ATmega128RFA1.
4 Resources
A comprehensive set of development tools and application notes, and datasheets are
available for download on http://www.atmel.com.
5 About Code Examples
This documentation contains simple code examples that briefly show how to use
various parts of the device. Be aware that not all C compiler vendors include bit
definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
These code examples assume that the part specific header file is included before
compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",
"CBI", and "SBI" instructions must be replaced with instructions that allow access to
extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and
"CBR".
6 Data Retention and Endurance
6.1 Data Retention
The data retention of the non-volatile memories is
over 10 years at 125°C
over 100 years at 2C
6.2 Endurance of the Code Memory (FLASH)
The endurance of the code memory (FLASH) is
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ATmega256/128/64RFR2
125°C – 10,000 Write/Erase cycles
85°C – 25,000 Write/Erase cycles
6.3 Endurance of the Data Memory (EEPROM)
The endurance of the entire data memory (EEPROM) is
125°C – 20,000 Write/Erase cycles
85°C – 50,000 Write/Erase cycles
25°C – 100,000 Write/Erase cycles
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ATmega256/128/64RFR2
7 AVR CPU Core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculation, control peripherals, and handle interrupts.
7.2 Architectural Overview
Figure 7-1.Block Diagram of the AVR Architecture
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
In order to maximize performance and parallelism, the AVR uses a Harvard
architecture – with separate memories and buses for program and data. Instructions in
the program memory are executed with a single level pipelining. While one instruction is
being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The program memory
is In-System Reprogrammable Flash memory.
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The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing enabling efficient address calculations. One of these address
pointers can also be used as an address pointer for look up tables in Flash program
memory. These added function registers are the 16-bit X-, Y-, and Z-register, described
later in this section.
The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU.
After an arithmetic operation, the Status Register is updated to reflect information about
the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and
the Application Program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate
Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance
with their Interrupt Vector position. The lower the Interrupt Vector address, the higher
the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,
the ATmega256/128/64RFR2 has Extended I/O space from 0x60 - 0x1FF in SRAM
where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
7.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories arithmetic, logical, and bit
functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the
“Instruction Set” section for a detailed description.
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7.4 Status Register
The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code. The Status Register is not automatically stored when entering an
interrupt routine and restored when returning from an interrupt. This must be handled by
software.
7.4.1 SREG – Status Register
Bit 7 6 5 4 3 2 1 0
$3F ($5F) I T H S V N Z C SREG
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
Bit 7 – I - Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable bit is cleared (zero), none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware
after an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
Bit 6 – T - Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source
and destination for the operated bit. A bit from a register in the register file can be
copied into T by the BST instruction, and a bit in T can be copied into a bit in a register
in the register file by the BLD instruction.
Bit 5 – H - Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. See the
Instruction Set Description for detailed information.
Bit 4 – S - Sign Bit
The S-bit is always an exclusive or between the negative flag N and the two's
complement overflow flag V. See the Instruction Set Description for detailed
information.
Bit 3 – V - Two's Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetics. See the
Instruction Set Description for detailed information.
Bit 2 – N - Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set Description for detailed information.
Bit 1 – Z - Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations.
See the Instruction Set Description for detailed information.
Bit 0 – C - Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set Description for detailed information. Note that the status register is not automatically
General Purpose Working Reg‘slers Atmet Adm 0x00 0x01 0x02 axoD 0on 0x0 F 0x10 0x11 oxIA OxIB OX‘C 0x1D oxIE 0x1 F Meg-5w Low Byle X-regwster High Byte Vrveglaev Low Byte V-regwster High Byte Z-vegws‘er Low Byle eregis|er ngh Eyle
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ATmega256/128/64RFR2
stored when entering an interrupt routine and restored when returning from an interrupt
routine. This must be handled by software.
7.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 7-1 below shows the structure of the 32 general purpose working registers in the
CPU.
Figure 7-1. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all
registers, and most of them are single cycle instructions.
As shown in Figure 7-1 above each register is also assigned a data memory address,
mapping them directly into the first 32 locations of the user Data Space. Although not
being physically implemented as SRAM locations, this memory organization provides
great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be
set to index any register in the file.
7.5.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 7-2
on page 13.
erqwsfior VrlegwsIev eregwsIer IS xu XL 0 I 7 n I 7 n I R27 40x13) R26 (on A) 15 VH YL o I / u I / uI H29 1mm) mama) Is ZH ZL I I U I ’ I R31 10mm R30 (on E) 13
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ATmega256/128/64RFR2
Figure 7-2. The X-, Y-, Z-registers
In the different addressing modes these address registers have functions as fixed
displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).
7.6 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer
Register always points to the top of the Stack. Note that the Stack is implemented as
growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and
Interrupt Stacks are located. This Stack space in the data SRAM must be defined by
the program before any subroutine calls are executed or interrupts are enabled. The
Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer is
the last address of the internal SRAM.
The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by
two when data is popped from the Stack with return from subroutine RET or return from
interrupt RETI.
When the FLASH memory exceeds 128Kbyte one additional cycle is required. In this
case the Stack Pointer is decremented by three when the return address is pushed onto
the Stack with subroutine call or interrupt and is incremented by three when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
Note: 1. If the Stack Pointer is zero and then decremented the new Stack Pointer value will
be different within the device family: 0xffff (256K Byte FLASH memory),
0x7fff (128 K Byte FLASH memory) and 0x03fff (64 K Byte FLASH memory),
respectively. Useful upper values of the Stack Pointer are defined by the SRAM
size.
7.6.1 SPH – Stack Pointer High
Bit 7 6 5 4 3 2 1 0
$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 1 0 0 0 0 1
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The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O
space. The number of bits actually used is implementation dependent. Note that the
data space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
Bit 7:0 – SP15:8 - Stack Pointer High Byte
7.6.2 SPL – Stack Pointer Low
Bit 7 6 5 4 3 2 1 0
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
Read/Write RW RW RW RW RW RW RW RW
Initial Value 1 1 1 1 1 1 1 1
The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O
space. The number of bits actually used is implementation dependent. Note that the
data space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
Bit 7:0 – SP7:0 - Stack Pointer Low Byte
7.6.3 RAMPZ – Extended Z-pointer Register for ELPM/SPM
Bit 7 6 5 4 3 2 1 0
$3B ($5B) Res5 Res4 Res3 Res2 Res1 Res0 RAMPZ1
RAMPZ0
RAMPZ
Read/Write R R R R R R RW RW
Initial Value 0 0 0 0 0 0 0 0
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL.
Note that LPM is not affected by the RAMPZ setting.
Bit 7:2 – Res5:0 - Reserved
For compatibility with future devices, be sure to write these bits to zero.
Bit 1:0 – RAMPZ1:0 - Extended Z-Pointer Value
Represent the MSB's of the Z-Pointer.
Table 7-2 RAMPZ Register Bits
Register Bits Value Description
RAMPZ1:0 0 Default value of Z-pointer MSB's.
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL,
as shown in Figure 7-3 below. Note that LPM is not affected by the RAMPZ setting.
Figure 7-3. The Z-pointer used by ELPM and SPM
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The actual number of bits is implementation dependent. Unused bits in an
implementation will always read as zero. For compatibility with future devices, be sure
to write these bits to zero.
7.6.4 EIND – Extended Indirect Register
Bit 7 6 5 4 3 2 1 0
$3C ($5C) EIND0 EIND
Read/Write RW
Initial Value 0
Bit 0 – EIND0 - Bit 0
For EICALL/EIJMP instructions.
7.7 Instruction Execution Timing
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Figure 7-5 below shows the internal timing concept for the Register File. In a single
clock cycle an ALU operation using two register operands is executed, and the result is
stored back to the destination register.
Figure 7-5. Single Cycle ALU operation
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
7.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
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interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically
disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section "Memory Programming" on page 504 for details.
The lowest addresses in the program memory space are by default defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on
page 243. The list also determines the priority levels of the different interrupts. The
lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 the External Interrupt Request 0. The Interrupt Vectors can be moved to
the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). Refer to "Interrupts" on page 243 for more information. The Reset Vector
can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see "Memory Programming" on page 504.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested
interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit
is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while
the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if
one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared,
the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition
disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt
routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs
simultaneously with the CLI instruction. The following example shows how this can be
used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
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Assembly Code Example
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
7.8.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is five clock cycles
minimum. After five clock cycles the program vector address for the actual interrupt
handling routine is executed. During these five clock cycle period, the Program Counter
is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by five clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five
clock cycles, the Program Counter (three bytes) is popped back from the Stack, the
Stack Pointer is incremented by three, and the I-bit in SREG is set.
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8 AVR Memories
This section describes the different memories in the ATmega256/128/64RFR2. The
AVR architecture has two main memory spaces, the Data Memory and the Program
Memory space. In addition, the ATmega256/128/64RFR2 features an EEPROM
Memory for data storage. All three memory spaces are linear and regular.
8.1 In-System Reprogrammable Flash Program Memory
The ATmega256/128/64RFR2 contains 256K/128K/64K Bytes On-chip In-System
Reprogrammable Flash memory for program storage, see Figure 8-6 below. Since all
AVR instructions are 16 or 32 bits wide, the Flash is 16 bit wide. For software security,
the Flash Program memory space is divided into two sections, Boot Program section
and Application Program section.
The Flash memory has an endurance of at least 10'000 write/erase cycles. The
ATmega256/128/64RFR2 Program Counter (PC) is 16 bits wide, thus addressing the
required program memory locations. The operation of Boot Program section and
associated Boot Lock bits for software protection are described in detail in "Boot Loader
Support Read-While-Write Self-Programming" on page 487. "Memory Programming"
on page 504 contains a detailed description on Flash data serial downloading using the
SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see
the LPM Load Program Memory instruction description and ELPM Extended Load
Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in "Instruction
Execution Timing" on page 15.
Figure 8-6. Program Flash Memory Map
Boot Flash Section
Program Memory
Application Flash Section $0000
The application section of the Flash memory contains 3 user signature pages. These
pages can be used to store data that should never be modified by an application
program e.g. ID numbers, calibration data etc. For details see section "User Signature
Data" on page 507.
8.2 SRAM Data Memory
Figure 8-7 on page 19 shows how the ATmega256/128/64RFR2 SRAM Memory is
organized. The ATmega256/128/64RFR2 is a complex microcontroller with more
peripheral units than can be supported within the 64 location reserved in the Opcode for
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the IN and OUT instructions. For the Extended I/O space from $060 $1FF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The first Data Memory locations address both the Register File, the I/O Memory,
Extended I/O Memory, and the internal data SRAM. The first 32 locations address the
Register file, the next 64 location the standard I/O Memory, then 416 locations of
Extended I/O memory and the following locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
In the Register file, registers R26 to R31 feature the indirect addressing pointer
registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM
(32K/16K/8K Bytes) in the ATmega256/128/64RFR2 are all accessible through all these
addressing modes. The Register File is described in "General Purpose Register File" on
page 12.
Figure 8-7. Data Memory Map
32 Registers
64 I/O Registers
Internal SRAM
(32K/16K/8K x 8)
$0000 - $001F
$0020 - $005F
$21FF
$41FF
$81FF
$FFFF
$0060 - $01FF
Data Memory
416 Ext I/O Reg.
$0200
8.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
Access to the internal data SRAM is performed in two clkCPU cycles as described in
Figure 8-8 on page 20.
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Figure 8-8. On-Chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Read Write
CPU
Memory Access Instruction
Next Instruction
8.3 EEPROM Data Memory
The ATmega256/128/64RFR2 contains 8K/4K/2K Bytes of data EEPROM memory. It is
organized as a separate data space. Read access is byte-wise. The access between
the EEPROM and the CPU is described in the following, specifying the EEPROM
Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see "Serial Downloading" on page 521, "Programming via the JTAG Interface" on page
525, and "Programming the EEPROM" on page 535 respectively.
8.3.1 EEPROM Read Write Access
The EEPROM Access Registers are accessible in the I/O space, see "EEPROM
Register Description" on page 26.
The write access time for the EEPROM is given in Table 8-3 below. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on power-
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See "Preventing EEPROM
Corruption" on page 26 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be
followed. See the description of the EEPROM Control Register for details on this,
"EEPROM Register Description" on page 26.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The calibrated oscillator is used to time the EEPROM accesses. The following table
lists the typical programming time for EEPROM access from the CPU.
Table 8-3. EEPROM Programming Time
Symbol Typical Programming time
EEPROM write (from CPU) 4.5 ms
EEPROM erase (from CPU) 8.5 ms
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The subsequent code examples show assembly and C functions for programming the
EEPROM with separate and combined (atomic) erase/write operations respectively.
The examples assume that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash Boot Loader is present in the software. If such
code is present, the EEPROM write function must also wait for any ongoing SPM
command to finish.
Assembly Code Example (Single Byte Programming)
EEPROM_write:
; Wait for completion of previous erase/write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write is controlled with r20 and r21
ldi r20, (1<<EEMPE) + (2<<EEPM0)
ldi r21, (1<<EEMPE) + (1<<EEPE) + (2<<EEPM0)
; Start eeprom write
out EECR, r20
out EECR, r21
ret
EEPROM_erase:
; Wait for completion of previous erase/write
sbic EECR,EEPE
rjmp EEPROM_erase
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Set EEDR to 0xff
ser r16
out EEDR,r16
; Erase is controlled with r20 and r21
ldi r20, (1<<EEMPE) + (1<<EEPM0)
ldi r21, (1<<EEMPE) + (1<<EEPE) + (1<<EEPM0)
; Start eeprom erase
out EECR, r20
out EECR, r21
ret
; main program
ldi r17, addr_low
ldi r18, addr_high
call EEPROM_erase
ldi r16, ee_data
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call EEPROM_write
C Code Example (Single Byte Programming)
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous erase/write */
while(EECR & (1<<EEPE))
;
/* Set up address */
EEAR = uiAddress;
EEDR = 255;
/* Write logical one to EEMPE and enable erase only*/
EECR = (1<<EEMPE) + (1<<EEPM0);
/* Start eeprom erase by setting EEPE */
EECR |= (1<<EEPE);
/* Wait for completion of erase */
while(EECR & (1<<EEPE))
;
/* Set up Data Registers */
EEDR = ucData;
/* Write logical one to EEMPE and enable write only */
EECR = (1<<EEMPE) + (2<<EEPM0);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
Although the code for separate erase/write operations is more complex it is
recommended over the atomic operation. The erase operation can be omitted if the
target EEPROM byte already contains the value 255 (e.g. after a chip erase without the
EESAVE fuse set).
Assembly Code Example (Atomic Operation)
EEPROM_atomic_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_atomic_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
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C Code Example (Atomic Operation)
void EEPROM_atomic_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example (EEPROM Read)
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example (EEPROM Read)
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
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The programming time can be reduced if an entire 8 byte EEPROM page is
programmed instead of single bytes. In this case the data has to be loaded into the
page buffer first. The page buffer will auto-erase after a write or erase operation. It is
also erased after a system reset. Note that it is not possible to write more than one time
to each address without erasing the page buffer. The EEPROM page programming is
shown in following example code.
Assembly Code Example (Page Mode Programming)
EEPROM_pageerase:
sbic EECR,EEPE ; wait for completion of previous
rjmp EEPROM_pageerase ; EEPROM erase/write
; Page buffer loading is controlled with r20 and r21
ldi r20, (3<<EEPM0) + (1<<EEMPE)
ldi r21, (3<<EEPM0) + (1<<EEMPE) + (1<<EEPE)
ldi r16, 7 ; EEPROM page has 8 bytes, loop 7 bytes
ser r16
out EEDR,r16 ; set EEDR to 0xff
er_page_load:
out EEARL, r17 ; set up address in page buffer
out EECR, r20
out EECR, r21
er_load_wait:
sbic EECR, EEWE ; wait for load complete
rjmp er_load_wait
dec r17 ; decrement address counter
dec r16 ; decrement loop counter
brne er_page_load ; complete loading of 7 bytes
; Erase is controlled with r20 and r21, load 8th byte
ldi r20, (1<<EEMPE) + (1<<EEPM0)
ldi r21, (1<<EEMPE) + (1<<EEPE) + (1<<EEPM0)
out EEARL, r17 ; set up address, low byte (8th byte)
out EEARH, r18 ; set up address, high byte
out EECR, r20 ; start EEPROM page erase
out EECR, r21
ret
; main program
ldi r17, addr_low
ldi r18, addr_high
call EEPROM_pageerase
C Code Example (Page Mode Programming)(1,2)
void EEPROM_pagewrite(uint16_t uiAddress, uint8_t *ucData)
{
uint8_t byte_cnt = 0;
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while(EECR & (1<<EEPE)); // wait finish of previous erase/write
EEAR = uiAddress; // set up address
EEDR = 255; // data for erase
do {
EECR = (1<<EEMPE) + (3<<EEPM0); // enable buffer load only
EECR |= (1<<EEPE); // start EEPROM loading
while(EECR & (1<<EEPE)); // wait for loading complete
EEARL++; // next address
} while( ++byte_cnt<7 );
EECR = (1<<EEMPE) + (1<<EEPM0); // load last byte, erase only
EECR |= (1<<EEPE); // start EEPROM erase
while(EECR & (1<<EEPE)); // wait for erase complete
EEAR = uiAddress; // set up address
byte_cnt = 0;
do {
EEDR = ucData[byte_cnt]; // load data from SRAM
EECR = (1<<EEMPE) + (3<<EEPM0); // enable buffer load only
EECR |= (1<<EEPE); // start EEPROM loading
while(EECR & (1<<EEPE)); // wait for loading complete
EEARL++; // next address
} while( ++byte_cnt<7 );
EEDR = ucData[byte_cnt]; // set up last data byte
EECR = (1<<EEMPE) + (2<<EEPM0); // load last byte, write only
EECR |= (1<<EEPE); // start EEPROM write
}
int main(void)
{
uint8_t buffer[8];
// load buffer
EEPROM_pagewrite(0x000, &buffer[0] ); // write EEPROM page 0
}
Notes: 1. The example code assumes that the part specific header file is included.
2. See section "About Code Examples" on page 7.
The EEPROM page buffer can be loaded in arbitrary order. The data in the page buffer
can also be overwritten. Loading the last byte and executing the EEPROM
programming is one command. This programming command can be an erase, a write
or a combined atomic erase/write operation just like for single byte programming mode.
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8.3.2 Preventing EEPROM Corruption
During periods of low DEVDD, the EEPROM data can be corrupted because the supply
voltage is too low for the CPU and the EEPROM to operate properly. These issues are
the same as for board level systems using EEPROM, and the same design solutions
should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
DEVDD reset protection circuit can be used. If a reset occurs while a write operation is
in progress, the write operation will be completed provided that the power supply
voltage is sufficient.
8.4 EEPROM Register Description
8.4.1 EEARH – EEPROM Address Register High Byte
Bit 7 6 5 4 3 2 1 0
$22 ($42) Res3 Res2 Res1 Res0 EEAR11
EEAR10
EEAR9 EEAR8 EEARH
Read/Write R R R R RW RW RW RW
Initial Value 0 0 0 0 X X X X
The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in
the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit 7:4 – Res3:0 - Reserved
Bit 3:0 – EEAR11:8 - EEPROM Address
8.4.2 EEARL – EEPROM Address Register Low Byte
Bit 7 6 5 4 3 2 1 0
$21 ($41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
Read/Write RW RW RW RW RW RW RW RW
Initial Value X X X X X X X X
The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in
the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit 7:0 – EEAR7:0 - EEPROM Address
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8.4.3 EEDR – EEPROM Data Register
Bit 7 6 5 4 3 2 1 0
$20 ($40) EEDR7:0 EEDR
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read
operation, the EEDR contains the data read out from the EEPROM at the address given
by EEAR.
Bit 7:0 – EEDR7:0 - EEPROM Data
8.4.4 EECR – EEPROM Control Register
Bit 7 6 5 4 3 2 1 0
$1F ($3F) Res1 Res0 EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
Read/Write R R RW RW RW RW RW RW
Initial Value 0 0 X X 0 0 X 0
Bit 7:6 – Res1:0 - Reserved
Bit 5:4 – EEPM1:0 - EEPROM Programming Mode
The EEPROM Programming mode bit setting defines if a page buffer load or a
programming action will be triggered when writing EEPE. It is possible to program data
in one atomic operation (erase the old value and program the new value) or to split the
Erase and Write operations in two different operations. While EEPE is set, any write to
EEPM1:0 will be ignored. During reset, the EEPM1:0 bits will be reset to 0 unless the
EEPROM is busy programming.
Table 8-4 EEPM Register Bits
Register Bits Value Description
EEPM1:0 0x00 Erase and Write in one operation (Atomic
Operation)
0x01 Erase only
0x02 Write only
0x03 Page buffer load
Bit 3 – EERIE - EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEPE is cleared.
Bit 2 – EEMPE - EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be
written or the page buffer to be loaded. When EEMPE is set, setting EEPE within four
clock cycles will either start programming the EEPROM or load data to the EEPROM
page buffer at the selected address If EEMPE is zero, setting EEPE will have no effect.
When EEMPE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
Bit 1 – EEPE - EEPROM Programming Enable
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The EEPROM Programming Enable Signal EEPE is the write strobe to the EEPROM. It
triggers either the programming or the page buffer loading. When address and data are
correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to
EEPE, otherwise no EEPROM write or load takes place. The following procedure
should be adopted when writing or loading the EEPROM (the order of steps 3 and 4 is
not essential):
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed and the page buffer not be loaded during a CPU
write to the Flash memory. The software must check that the Flash programming is
completed before initiating a new EEPROM write. Step 2 is only relevant if the software
contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never
being updated by the CPU, step 2 can be omitted.
Caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during all steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEPE has been set, the CPU is halted for two cycles before the next instruction is
executed.
Bit 0 – EERE - EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed. The user should poll the
EEPE bit before starting the read operation. If a write operation is in progress, it is
neither possible to read the EEPROM nor to change the EEAR Register.
8.5 I/O Memory
The Input/Output (I/O) space definition of the ATmega256/128/64RFR2 is shown in
"Register Summary" on page 543.
All ATmega256/128/64RFR2 I/Os and peripherals are placed in the I/O space. All I/O
locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions,
transferring data between the 32 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 0x1F are directly bit-accessible using the
SBI and CBI instructions. In these registers, the value of single bits can be checked by
using the SBIS and SBIC instructions. Refer to the AVR instruction set for more details.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 0x3F
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must be used. When addressing I/O Registers as data space using LD and ST
instructions, 0x20 must be added to these addresses. The ATmega256/128/64RFR2 is
a complex microcontroller with more peripheral units than can be supported within the
64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from 0x60 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
For compatibility with future devices, reserved bits may not be modified. Reserved
registers and I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit,
and can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The control registers of I/O and peripherals are explained in later sections.
8.6 General Purpose I/O Registers
The ATmega256/128/64RFR2 contains three General Purpose I/O Registers. These
registers can be used for storing any information, and they are particularly useful for
storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions.
8.6.1 GPIOR0 – General Purpose IO Register 0
Bit 7 6 5 4 3 2 1 0
$1E ($3E) GPIOR07:00 GPIOR0
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The three General Purpose I/O Registers can be used for storing any information.
Bit 7:0 – GPIOR07:00 - General Purpose I/O Register 0 Value
8.6.2 GPIOR1 – General Purpose IO Register 1
Bit 7 6 5 4 3 2 1 0
$2A ($4A) GPIOR17:10 GPIOR1
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The three General Purpose I/O Registers can be used for storing any information.
Bit 7:0 – GPIOR17:10 - General Purpose I/O Register 1 Value
8.6.3 GPIOR2 – General Purpose I/O Register 2
Bit 7 6 5 4 3 2 1 0
$2B ($4B) GPIOR27:20 GPIOR2
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
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The three General Purpose I/O Registers can be used for storing any information.
Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value
8.7 Other Port Registers
The inherited control registers of missing ports located in the I/O space are kept in the
ATmega256/128/64RFR2. They can be used as general purpose I/O registers for
storing any information. Registers placed in the address range 0x00 – 0x1F are directly
bit-accessible using the SBI, CBI, SBIS and SBIC instructions.
8.7.1 PORTA – Port A Data Register
Bit 7 6 5 4 3 2 1 0
$02 ($22) PORTA7:0 PORTA
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The PORTA register can be used as a General Purpose I/O Register for storing any
information.
Bit 7:0 – PORTA7:0 - Port A Data Register Value
8.7.2 DDRA – Port A Data Direction Register
Bit 7 6 5 4 3 2 1 0
$01 ($21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The DDRA register can be used as a General Purpose I/O Register for storing any
information.
Bit 7:0 – DDA7:0 - Port A Data Direction Register Value
8.7.3 PINA – Port A Input Pins Address
Bit 7 6 5 4 3 2 1 0
$00 ($20) PINA7:0 PINA
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The PINA register is reserved for internal use and cannot be used as a General
Purpose I/O Register.
Bit 7:0 – PINA7:0 - Port A Input Pins
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8.7.4 PORTC – Port C Data Register
Bit 7 6 5 4 3 2 1 0
$08 ($28) PORTC7:0 PORTC
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The PORTC register can be used as a General Purpose I/O Register for storing any
information.
Bit 7:0 – PORTC7:0 - Port C Data Register Value
8.7.5 DDRC – Port C Data Direction Register
Bit 7 6 5 4 3 2 1 0
$07 ($27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write RW RW RW RW RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
The DDRC register can be used as a General Purpose I/O Register for storing any
information.
Bit 7:0 – DDC7:0 - Port C Data Direction Register Value
8.7.6 PINC – Port C Input Pins Address
Bit 7 6 5 4 3 2 1 0
$06 ($26) PINC7:0 PINC
Read/Write R R R R R R R R
Initial Value 0 0 0 0 0 0 0 0
The PINC register is reserved for internal use and cannot be used as a General
Purpose I/O Register.
Bit 7:0 – PINC7:0 - Port C Input Pins
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9 Low-Power 2.4 GHz Transceiver
9.1 Features
High performance RF-CMOS 2.4 GHz radio transceiver targeted for IEEE
802.15.4™, ZigBee™, IPv6 / 6LoWPAN, RF4CE, SP100, WirelessHART™ and
ISM applications
Outstanding link budget (103.5 dB):
o Receiver sensitivity -100 dBm
o Programmable output power from -17 dBm up to +3.5 dBm
Ultra-low current consumption:
o TRX_OFF = 0.4 mA
o RX_ON = 12.5 mA
o BUSY_TX = 14.5 mA (at max. transmit power of +3.5 dBm)
Optimized for low BoM cost and ease of production:
o Few external components necessary (crystal, capacitors and
antenna)
o Excellent ESD robustness
Easy to use interface:
o Registers and frame buffer access from software
o Dedicated radio transceiver interrupts
Radio transceiver features:
o 128 byte FIFO (SRAM) for data buffering
o Integrated RX/TX switch
o Fully integrated, fast settling PLL to support frequency hopping
o Battery monitor
o Fast wake-up time < 0.25 ms
Special IEEE 802.15.4 2006 hardware support:
o FCS computation and clear channel assessment (CCA)
o RSSI measurement, energy detection and link quality indication
MAC hardware accelerator:
o Automated acknowledgement, CSMA-CA and frame
retransmission
o Automatic address filtering
o Automated FCS check
Extended Feature Set Hardware Support:
o AES 128 bit hardware accelerator
o RX/TX indication (external RF front-end control)
o RX antenna diversity
o Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s
o True random number generation for security applications
Compliant to IEEE 802.15.4-2006, IEEE 802.15.4-2003 and RF4CE
Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210
4|]:- f HA H $1
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The ATmega256/128/64RFR2 features a low-power 2.4 GHz radio transceiver
designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and
high data rate 2.4 GHz ISM band applications. The radio transceiver is a true peripheral
block of the AVR microcontroller. All RF-critical components except the antenna, crystal
and de-coupling capacitors are integrated on-chip. Therefore, the
ATmega256/128/64RFR2 is particularly suitable for applications like:
2.4 GHz IEEE 802.15.4 and ZigBee systems
6LoWPAN and RF4CE systems
Wireless sensor networks
Industrial control, sensing and automation (SP100, WirelessHART)
Residential and commercial automation
Health care
Consumer electronics
PC peripherals
9.2 General Circuit Description
This radio transceiver is part of a system-on-chip solution with an AVR® microcontroller.
It comprises a complex peripheral component containing the analog radio, digital
modulation and demodulation including time and frequency synchronization and data
buffering. The number of external components for the transceiver operation is
minimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used for
transmission and reception, thus no external antenna switch is needed.
The transceiver block diagram of the ATmega256/128/64RFR2 is shown in Figure 9-9
below.
Figure 9-9. Transceiver Block Diagram
AVREG
LNA
PLL PA
PPF BPF Limiter RX
ADC
AGC
ext. PA and Power
Control
Configuration Registers
µC
Interface
RSSI
Data
Interrupts
Address
Control
DIG3/4
RFP
RFN
TX Data
Control Logic
Antenna Diversity
FTN, BATMON
XOSC
XTAL1
XTAL2
Analog Domain Digital Domain
AES
DIG1/2
AD
RX BBP
Frame
Buffer
TX BBP
DVREG
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The received RF signal at pins RFN and RFP is differentially fed through the low-noise
amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the
integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the
succeeding analog-to-digital converter (RX ADC) and generates a digital RSSI signal.
The RX ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping
and 32-length block coding (spreading) according to [1] on page 110 and [2] on page
110. The modulation signal is generated in the digital transmitter (TX BBP) and applied
to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation
required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to
the power amplifier (PA).
A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.
The two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and
digital 1.8V supply.
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be
transmitted or received.
The configuration of the reading and writing of the Frame Buffer is controlled via the
microcontroller interface.
The transceiver further contains comprehensive hardware-MAC support (Extended
Operating Mode) and a security engine (AES) to improve the overall system power
efficiency and timing. The 128-bit AES engine can be accessed in parallel to all PHY
operational transactions and states using the microcontroller interface, except during
transceiver power down state.
For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radio
transceiver also supports alternative data rates up to 2 Mb/s.
For long-range applications or to improve the reliability of an RF connection the RF
performance can further be improved by using an external RF front-end or Antenna
Diversity. Both operation modes are supported by the radio transceiver with dedicated
control pins without the interaction of the microcontroller.
Additional features of the Extended Feature Set, see section "Radio Transceiver
Extended Feature Set" on page 92, are provided to simplify the interaction between
radio transceiver and microcontroller.
9.3 Transceiver to Microcontroller Interface
This section describes the internal Interface between the transceiver module and the
microcontroller. Unlike all other AVR I/O modules, the transceiver module can operate
asynchronously to the controller. The transceiver requires an accurate 16MHz crystal
clock for operation, but the controller can run at any frequency within its operating limits.
Note that the on-chip debug system (see section "Using the On-chip Debug System" on
page 475) must be disabled for the best RF performance of the radio transceiver.
9.3.1 Transceiver Configuration and Data Access
9.3.1.1 Register Access
All transceiver registers are mapped into I/O space of the controller. Due to the
asynchronous interface a register access can take up to three transceiver clock cycles.
Depending on the controller clock speed, program execution wait cycles are generated.
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That means if the controller runs with about 16MHz or faster, at least three wait cycles
are generated, but if the controller runs with about 4MHz, no wait cycles are inserted. A
register access is only possible, if the transceiver clock is available. Otherwise it returns
0x00 regardless of the current register content. Therefore the transceiver must be
enabled (PRR1 Register) and not in SLEEP state.
9.3.1.2 Frame Buffer Access
The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed
description of the Frame Buffer can be found in section "Frame Buffer" on page 83. An
introduction to the IEEE 802.15.4 frame format can be found in section "Introduction
IEEE 802.15.4-2006 Frame Format" on page 67.
The Frame Buffer is located within the controller I/O address space above of the
transceiver register set. The first byte of the Frame Buffer can be accessed with the
symbolical address TRXFBST and the last byte can be accessed with the symbolical
address TRXFBEND. Random access to single frame bytes is possible with “TRXFBST
+ byte index” or “TRXFBEND byte index”. In contrast to the transceiver register
access, the Frame Buffer allows single cycle read/write operations for all controller
clock speeds.
The content of the Frame Buffer is only overwritten by a new received frame or a Frame
Buffer write access.
The Frame Buffer usage is different between received and transmitted frames.
Therefore it is not possible to retransmit a received frame without modifying the frame
buffer.
On received frames, the frame length byte is not stored in the Frame Buffer, but can be
accessed over the TST_RX_LENGTH register. During frame receive, the Link Quality
Indication (LQI) value (refer to "Link Quality Indication (LQI)" on page 78 ) is appended
to the frame data in the Frame Buffer.
For frame transmission, the first byte of the Frame Buffer must contain the frame length
information followed by the frame data. The TST_RX_LENGTH register does not need
to be written in this case.
A detailed description of the Frame Buffer usage for receive and transmit frames can be
found in Figure 9-32 on page 84.
Notes:
1. The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by
new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no
frame was received in the meanwhile.
2. To avoid overwriting during receive, Dynamic Frame Buffer Protection can be enabled. For
details about this feature refer to section "Dynamic Frame Buffer Protection" on page 99.
3. It is not possible to retransmit received frames without inserting the frame length information at
the beginning of the Frame Buffer. That requires a complete read out of the received frame
and rewriting the modified frame to the Frame Buffer.
4. For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
(TX_ARET) refer to section "TX_ARET_ON Transmit with Automatic Retry and CSMA-CA
Retry" on page 63.
9.3.1.3 Transceiver Pin Register TRXPR
The Transceiver Pin Register TRXPR is located in the Controller clock domain and is
accessible even if the transceiver is in sleep state. This register provides access to the
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pin functionality, known from the Atmel standalone transceiver devices (two chip
solution).
The register (TRXRST) can be used to reset the transceiver without resetting the
controller. After the reset bit was set, it is cleared immediately.
A second configuration bit (SLPTR) is used to control frame transmission or sleep and
wakeup of the transceiver. This bit is not cleared automatically.
The function of the SLPTR bit relates to the current state of the transceiver module and
is summarized in Table 9-1 below. The radio transceiver states are explained in detail in
section "Operating Modes" on page 38.
Table 9-1. SLPTR Multi-functional Configuration bit
Transceiver Status Function SLPTR Bit Description
PLL_ON TX start “0” “1” Starts frame transmission
TX_ARET_ON TX start “0” “1” Starts TX_ARET transaction
TRX_OFF Sleep “0” “1” Takes the radio transceiver into SLEEP state
SLEEP Wakeup “1” “0” Takes the radio transceiver back into TRX_OFF state;
In states PLL_ON and TX_ARET_ON, bit SLPTR is used to initiate a TX transaction.
Here bit SLPTR is sensitive on the transition from “0” to “1” only. The bit should be
cleared before the frame transmission is finished.
After initiating a state change by a “0” to “1” transition at bit SLPTR in radio transceiver
states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new
state as long as the bit is logical “1” and returns to the preceding state if the bit is set to
“0”.
SLEEP state
The SLEEP state is used when radio transceiver functionality is not required, and thus
the receiver module can be powered down to reduce the overall power consumption.
When the radio transceiver is in TRX_OFF state the microcontroller forces the
transceiver to SLEEP by setting SLPTR = “1”. The transceiver awakes when the
microcontroller releases bit SLPTR.
9.3.2 Interrupt Logic
9.3.2.1 Overview
The transceiver module differentiates between eight interrupt events. Internally all
pending interrupts are stored in a separate bit of the interrupt status register
(IRQ_STATUS). Each interrupt is enabled by setting the corresponding bit in the
interrupt mask register (IRQ_MASK). If an IRQ is enabled an interrupt service routine
must be defined to handle the IRQ. A pending IRQ is cleared automatically if an
Interrupt service routine is called. It is also possible to handle IRQs manually by polling
the IRQ_STATUS register. If an IRQ occurred, the appropriate IRQ_STATUS register
bit is set. The IRQ can be cleared by writing ‘1’ to the register bit. It is recommended to
clear the corresponding status bit before enabling an interrupt.
More information about interrupt handling by the controller can be found in section
"Interrupts" on page 243.
The supported interrupts for the Basic Operating Mode are summarized in Table 9-2 on
page 37.
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Table 9-2. Interrupt Description in Basic Operating Mode
IRQ Vector
Number/
Priority (1)
IRQ Name Description Section
64 TRX24_AWAKE Indicates radio transceiver reached TRX_OFF
state RESET, or SLEEP states
"TRX_OFF – Clock State" on page 40
63 TRX24_TX_END Indicates the completion of a frame
transmission
"Frame Transmit Procedure" on page 91
62 TRX24_XAH_AMI Indicates address matching "Frame Filtering" on page 58
61 TRX24_CCA_ED_DONE Indicates the end of a CCA or ED
measurement
"Energy Detection (ED)" on page 74
60 TRX24_RX_END Indicates the completion of a frame reception "Frame Transmit Procedure" on page 91
59 TRX24_RX_START Indicates the start of a PSDU reception. The
TRX_STATE changes to BUSY_RX, the PHR
is ready to be read from Frame Buffer
"Frame Receive Procedure" on page 90
58 TRX24_PLL_UNLOCK Indicates PLL unlock. If the radio transceiver
is in BUSY_TX / BUSY_TX_ARET state, the
PA is turned off immediately, END interrupts
will not happen (see Interrupt Handling on
page 89)
"Interrupt Handling" on page 89
57 TRX24_PLL_LOCK Indicates PLL lock "Interrupt Handling" on page 89
Note: 1. The lowest IRQ Number has the highest priority.
During startup from SLEEP or RESET, the radio transceiver issues an TRX24_AWAKE
interrupt when it enters state TRX_OFF.
If the microcontroller initiates an energy-detect (ED) or clear-channel-assessment
(CCA) measurement, the completion of the measurement is indicated by interrupt
TRX24_CCA_ED_DONE, refer to sections "Energy Detection (ED)" on page 74 and
"Clear Channel Assessment (CCA)" on page 76 for details.
After RESET all interrupts are disabled. During radio transceiver initialization it is
recommended to enable AWAKE to be notified once the TRX_OFF state is entered.
Note that the TRX24_AWAKE interrupt can usually not be seen when the transceiver
enters TRX_OFF state after RESET, because register IRQ_MASK is reset to mask all
interrupts. In this case, state TRX_OFF is normally entered before the microcontroller
could modify the register.
The interrupt handling in Extended Operating Mode is described in section "Interrupt
Handling" on page 65.
9.3.3 Radio Transceiver Identification
The ATmega256/128/64RFR2 Transceiver module can be identified by four registers
(PART_NUM, VERSION_NUM, MAN_ID_0, MAN_ID_1). One register contains a
unique part number and one register the corresponding version number. Two additional
registers contain the JTAG manufacture ID. The transceiver identification registers are
provided for compatibility to the transceiver only device.
A unique device identification is also possible with the three AVR signature bytes. For
details about accessing this information refer to "Signature Bytes" on page 507.
Atmel: 46 u 125 «so 192 1924 wmz Twmefls] mxjmrE PLLioN ausv_tx PLLON \ mm 7 m "WW w ,1 WWW j YyDVNOQSSIHVDeLW H‘ 15;; Numberaloclels ; 1 1 7 m 2 ‘ g i FumeEanM Pvezmb‘e \ SFD \ PHR m MSDU FOL? ' S s
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9.3.4 TX Start Interrupt
When the TRX24 starts a frame transmission a TRX24_TX_START interrupt is issued
when the preamble starts.
Table 9-3. Interrupt Description for TX_START interrupt
IRQ Vector
Number/
Priority
IRQ Name Description enable
72 TRX24_TX_START Indicates the start of a preamble transmission.
set bit TX_START in register IRQ_MASK1
When enabled, the TX_START interrupt is issued in both basic operating modes and
extended operating modes. Thus it also indicates the frame start of a transmitted
acknowledge frame in procedure RX_AACK. In procedure TX_ARET the
TRX24_TX_START interrupt is issued separately for every frame transmission and
frame retransmission.
Figure 9-2. Interrupt timing in with TRX24_TX_START interrupt
The figure above shows the timing of TRX24_TX_START interrupt in basic operation
mode. For a description of other relevant interrupt timings see Interrupt Handling on
page 42.
The timing for extended operating modes are respective.
9.4 Operating Modes
9.4.1 Basic Operating Mode
This section summarizes all states to provide the basic functionality of the 2.4GHz radio
transceiver, such as receiving and transmitting frames, the power up sequence and
radio transceiver sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and
ISM applications; the corresponding radio transceiver states are shown in Figure 9-3 on
page 39.
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Figure 9-3. Basic Operating Mode State Diagram (for timing refer to Table 9-4 on page 46)
2
SLPTR = 1
SLPTR = 0
PLL_ON
R X _ O N
P L L _ O N
T R X _ O F F
(C lo c k S ta te )
X O S C = O N
RX_ON
S L E E P
(S le e p S ta t e )
X O S C = O F F
F O R C E _ T R X _ O F F
(a ll s ta te s e x c e p t S L E E P )
S H R
D e t e c t e d
F r a m e
E n d
F r a m e
E n d B U S Y _ T X
(T r a n s m i t S ta te )
P L L _ O N
(P L L S ta t e )
T X _ S T A R T
o r
TRX_OFF
TRX_OFF
3
4
57
6
8
9
1 1
1 0
1 2 1 3 T R X R S T = 0
F O R C E _ P L L _ O N
(a ll s ta te s e x c e p t S L E E P ,
T R X _ O F F )
1 4
S L P T R = 1
L e g e n d :
B l u e : R e g is te r w r ite to T R X _ S T A T E
R e d : C o n tr o l s ig n a ls v ia R e g is te r T R X P R
G r e e n : E v e n t
B a s ic O p e ra tin g M o d e S ta te s
S t a te tr a n s iti o n n u m b e r
R X _ O N
(R x L i s t e n S ta te )
B U S Y _ R X
(R e c e iv e S ta te )
R E S E T
(fro m a ll s ta te s )
T R X R S T = 1
X
Note: 1. State transition numbers correspond to Table 9-4 on page 46.
9.4.1.1 State Control
The radio transceiver states are controlled either by writing commands to bits
TRX_CMD of register TRX_STATE, or directly by the two control bits SLPTR and
TRXRST of the TRXPR register. A successful state change can be verified by reading
the radio transceiver status from register TRX_STATUS.
If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the radio transceiver
is on a state transition. Do not try to initiate a further state change while the radio
transceiver is in STATE_TRANSITION_IN_PROGRESS.
Bit SLPTR is a multifunctional bit (refer to section "Transceiver Pin Register TRXPR" on
page 35 for more details). Dependent on the radio transceiver state, a “0” to “1”
transition on SLPTR causes the following state transitions:
TRX_OFF SLEEP
PLL_ON BUSY_TX
Whereas resetting bit SLPTR to “0” causes the following state transitions:
SLEEP TRX_OFF
Bit TRXRST causes a reset of all radio transceiver registers and forces the radio
transceiver into TRX_OFF state.
For all states except SLEEP, the state change commands FORCE_TRX_OFF or
TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active
receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these
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active processes, and forces an immediate transition to TRX_OFF. In contrast a
TRX_OFF command is stored until an active state (receiving or transmitting) has been
finished. After that the transition to TRX_OFF is performed.
For a fast transition from receive or active transmit states to PLL_ON state the
command FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this
command does not disable the PLL and the analog voltage regulator AVREG. It is not
available in states SLEEP, and RESET.
The completion of each requested state-change shall always be confirmed by reading
the bits TRX_STATUS of register TRX_STATUS.
9.4.1.2 Basic Operating Mode Description
9.4.1.2.1 SLEEP – Sleep State
In radio transceiver SLEEP state, the entire radio transceiver is disabled. No circuitry is
operating. The radio transceiver’s current consumption is reduced to leakage current
only. This state can only be entered from state TRX_OFF, by setting the bit
SLPTR = “1”.
Setting SLPTR = “0” returns the radio transceiver to the TRX_OFF state. During radio
transceiver SLEEP the register contents remains valid while the content of the Frame
Buffer and the security engine (AES) are cleared.
TRXRST = “1” in SLEEP state returns the radio transceiver to TRX_OFF state and
thereby sets all registers to their reset values.
9.4.1.2.2 TRX_OFF – Clock State
This state is reached immediately after Power On or Reset. In TRX_OFF the crystal
oscillator is running. The digital voltage regulator is enabled, thus the radio transceiver
registers, the Frame Buffer and security engine (AES) are accessible (see section
"Frame Buffer" on page 83 and "Security Module (AES)" on page 99).
SLPTR and TRXRST in register TRXPR can be used for state control (see "State
Control" on page 39 for details). The analog front-end is disabled during TRX_OFF.
Entering the TRX_OFF state from radio transceiver SLEEP, or RESET state is
indicated by the TRX24_AWAKE interrupt.
9.4.1.2.3 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state first enables the analog voltage
regulator (AVREG). After the voltage regulator has been settled the PLL frequency
synthesizer is enabled. When the PLL has been settled at the receive frequency to a
channel defined by bits CHANNEL of register PHY_CC_CCA a successful PLL lock is
indicated by issuing a TRX24_PLL_LOCK interrupt.
If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled.
If the PLL has not been settled before the state change nevertheless takes place. Even
if the register bits TRX_STATUS of register TRX_STATUS indicates RX_ON, actual
frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
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9.4.1.2.4 RX_ON and BUSY_RX – RX Listen and Receive State
In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled.
The receive mode is internally separated into the RX_ON and BUSY_RX states. There
is no difference between these states with respect to the analog radio transceiver
circuitry, which are always turned on. In both states the receiver and the PLL frequency
synthesizer are enabled.
During RX_ON state the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the receiver automatically enters the BUSY_RX state.
The reception of a valid PHY header (PHR) generates an TRX24_RX_START interrupt
and receives and demodulates the PSDU data.
During PSDU reception the frame data are stored continuously in the Frame Buffer until
the last byte was received. The completion of the frame reception is indicated by an
TRX24_RX_END interrupt and the radio transceiver reenters the state RX_ON. At the
same time the bits RX_CRC_VALID of register PHY_RSSI are updated with the result
of the FCS check (see "Frame Check Sequence (FCS)" on page 72).
Received frames are passed to the frame filtering unit, refer to section "Frame Filtering"
on page 58. If the content of the MAC addressing fields of a frame (refer to
IEEE 802.15.4 section 7.2.1) matches to the expected addresses, which is further
dependent on the addressing mode, an address match interrupt (TRX24_XAH_AMI) is
issued, refer to "Interrupt Logic" on page 36. The expected address values are to be
stored in the registers Short-Address, PAN-ID and IEEE-address. Frame filtering is
available in Basic and Extended Operating Mode, refer to section "Frame Filtering" on
page 58.
Leaving state RX_ON is only possible by writing a state change command to bits
TRX_CMD of register TRX_STATE.
9.4.1.2.5 BUSY_TX – Transmit State
A transmission can only be initiated in state PLL_ON. There are two ways to start a
transmission:
Setting Bit SLPTR of register TRXPR to ‘1’. The bit should be cleared before the
frame has been transmitted. This mode is for legacy operation and should be
replaced by the TX_START command below.
TX_START command to bits TRX_CMD of register TRX_STATE.
Either of these causes the radio transceiver into the BUSY_TX state.
During the transition to BUSY_TX state, the PLL frequency shifts to the transmit
frequency. The actual transmission of the first data chip of the SHR starts after 16 µs to
allow PLL settling and PA ramp-up, see Figure 9-7 on page 44. After transmission of
the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame
length of zero, the transmission is aborted.
After the frame transmission has completed, the radio transceiver automatically turns
off the power amplifier, generates a TRX24_TX_END interrupt and returns into PLL_ON
state.
9.4.1.2.6 RESET State
The RESET state is used to set back the state machine and to reset all registers of the
radio transceiver to their default values.
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A reset forces the radio transceiver into the TRX_OFF state.
A reset is initiated by a ATmega256/128/64RFR2 main reset (see "Resetting the AVR"
on page 209) or a radio transceiver reset (see "Transceiver Pin Register TRXPR" on
page 35).
During radio transceiver reset the TRXPR register is not cleared and therefore the
application software has to set the SLPTR bit to “0”.
9.4.1.3 Interrupt Handling
All interrupts provided by the radio transceiver are supported in Basic Operating Mode
(see Table 9-2 on page 37).
Required interrupts must be enabled by writing to register IRQ_MASK and the global
interrupt enable flag must be set. For a general explanation of the interrupt handling
refer to "Reset and Interrupt Handling" on page 15 and "Interrupt Logic" on page 36.
For example, interrupts are provided to observe the status of the RX and TX operations.
On receive the TRX24_RX_START interrupt indicates the detection of a valid PHR, the
TRX24_XAH_AMI interrupt an address match and the TRX24_RX_END interrupt the
completion of the frame reception.
On transmit the TRX24_TX_END interrupt indicates the completion of the frame
transmission.
Figure 9-14 on page 43 shows an example for a transmit/receive transaction between
two devices and the related interrupt events in Basic Operating Mode. Device 1
transmits a frame containing a MAC header (in this example of length 7), payload and
valid FCS. The frame is received by Device 2 which generates the interrupts during the
processing of the incoming frame. The received frame is stored in the Frame Buffer.
If the received frame passes the address filter (refer to section "Frame Filtering" on
page 58) an address match TRX24_XAH_AMI interrupt is issued after the reception of
the MAC header (MHR).
In Basic Operating Mode the TRX24_RX_END interrupt is issued at the end of the
received frame. In Extended Operating Mode (refer to "Extended Operating Mode" on
page 47) the interrupt is only issued if the received frame passes the address filter and
the FCS is valid. Further exceptions are explained in "Extended Operating Mode" on
page 47.
Processing delay tIRQ is a typical value (see chapter "Digital Interface Timing
Characteristics" on page 563).
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Figure 9-14. Timing of TRX24_RX_START, TRX24_XAH_AMI, TRX24_TX_END and TRX24_RX_END Interrupts in
Basic Operating Mode
1 2 8 1 6 0 1 9 20 1 9 2 + ( 9 + m) * 3 2- 1 6 T im e [ µ s ]
RX
(Device 2)
T R X 2 4 _ R X _ S T A R T
tIR Q
R X _ O N R X _ O N
I R Q
T R X _ S T A T E
I n te rr u p t l a te n c y
T R X 2 4 _
R X _ E N D
T R X 2 4 _ X A H _ A M I
tIR Q tIR Q
B U S Y _ R X
T R X 2 4 _ T X _ E N D
TX
(Device1)
P L L _ O N B U S Y _ T X P L L _ O N
I R Q
S L P T R
T R X _ S T A T E
T y p . P r o c e s s in g D e la y 1 6 µ s
Frame
on Air
P r e a m b le S F D P H R M S D U
4 1 1 mN u m b e r o f O c t e ts
F r a m e C o n te n t M H R
7
F C S
2
9.4.1.4 Basic Operating Mode Timing
The following paragraphs depict state transitions and their timing properties. Timing
figures are explained in Table 9-4 on page 46 and section "Digital Interface Timing
Characteristics" on page 563.
9.4.1.4.1 Wake-up Procedure
The wake-up procedure from radio transceiver SLEEP state is shown in Figure 9-15
below. This figure implies, that the microcontroller is already running and hence, the
digital voltage regulator is enabled. If the microcontroller clock source is set to
Transceiver Clock, the crystal oscillator is also running, which reduces the radio
transceiver wake-up time further. For information about the wake-up timing of the
microcontroller, depending on the different clock source options, refer to "System Clock
and Clock Options" on page 176.
In order to calculate the total wake-up delay from microcontroller sleep mode (see
"Power Management and Sleep Modes" on page 185), the microcontroller wake-up
time, including the voltage regulator ramp-up and the radio transceiver wake-up time
has to be added.
Figure 9-15. Wake-up Procedure from Transceiver SLEEP State
0
Event
State
Block
100 400 Time s]
Time tTR2
TRX_OFF
TRX24_AW AKE IRQSLPTR = 0
SLEEP
200
XOSC startup XO SC enabledFTN
The radio transceiver SLEEP state is left by releasing bit SLPTR to “0”. This restarts the
XOSC if it is not already running. After tTR2 = 215 µs + 25 µs = 240 µs (see Table 9-4 on
page 46) the radio transceiver enters TRX_OFF state. If the XOSC is already running,
the radio transceiver enters TRX_OFF state after 25 µs.
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During this wake-up procedure the calibration of the filter-tuning network (FTN) is
performed. Entering TRX_OFF state is signaled by the TRX24_AWAKE interrupt, if
enabled.
9.4.1.4.2 PLL_ON and RX_ON States
The transition from TRX_OFF to PLL_ON and RX_ON mode is shown in Figure 9-16
below.
Figure 9-16. Transition from TRX_OFF to PLL_ON and RX_ON State
0
Event
State
Block
100 Times]
Time tTR4
TRX24_PLL_LOCK IRQ
TRX_OFF
AVREG
Command PLL_ON
PLL RX
PLL_ON
RX_ON
tTR8
RX_ON
Note: 1. If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately,
even if the PLL has not settled.
2. If the AVR ADC module is enabled, the AVREG is already started and thus the
state transition time tTR4 is reduced.
Entering the commands PLL_ON or RX_ON in TRX_OFF state initiates a ramp-up
sequence of the internal 1.8V voltage regulator for the analog domain (AVREG), if
AVREG is not already enabled by the AVR ADC module. RX_ON state can be entered
any time from PLL_ON state regardless whether the PLL has already locked as
indicated by the TRX24_PLL_LOCK interrupt.
9.4.1.4.3 BUSY_TX and RX_ON States
The transition from PLL_ON to BUSY_TX state and subsequent to RX_ON state is
shown in Figure 9-7 below.
Figure 9-7. PLL_ON to BUSY_TX to RX_ON Timing
Tim e s]0 x16 x + 32
Time tTR11
tTR1 0
C om m an d RX_ON
State
Block
PLL_O N RX_ONBUSY_TX
Event SLPTR
PA PLLPA, TX RXPLL
or comm and TX_START
Starting from PLL_ON state it is assumed that the PLL is already locked. A
transmission is initiated either by writing “1” to bit SLPTR or by command TX_START.
The PLL settles to the transmit frequency and the PA is enabled.
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tTR10 = 16 µs after initiating the transmission, the radio transceiver changes into
BUSY_TX state and the internally generated SHR is transmitted. After that the PSDU
data are transmitted from the Frame Buffer.
After completing the frame transmission, indicated by the TRX24_TX_END interrupt,
the PLL settles back to the receive frequency within tTR11 = 32 µs in state PLL_ON.
If during TX_BUSY the radio transmitter is programmed to change to a receive state it
automatically proceeds the state change to RX_ON state after finishing the
transmission.
9.4.1.4.4 Reset Procedure
The radio transceiver reset procedure is shown in Figure 9-18 below.
Figure 9-18. Reset Procedure
x
E v e n t
S ta te
B lo c k
T im e [µ s]
T R X R S T
T R X _ O F F
x + 4 0
[T R X 2 4 _ A W A K E IR Q ]
0
v a ri o u s
T im e 3 x A V R c lo c k tT R 1 3
> t1 1
X O S C , D V R E G e n a b le d X O S C , D V R E G e n a b le d
x + 1 0
FTN
Note: 1. Timing parameter tTR13 = 37 µs refers to Table 9-4 on page 46; t11 refers to "Digital
Interface Timing Characteristics" on page 563.
2. If TRXRST is set during radio transceiver SLEEP state, the XOSC startup delay is
extended by the XOSC startup time.
TRXRST = “1” resets all radio transceiver registers to their default values.
The radio transceiver reset is released automatically after 3 AVR clock cycles and the
wake-up sequence without restarting XOSC and DVREG, nevertheless an FTN
calibration cycle is performed, refer to "Automatic Filter Tuning (FTN)" on page 90. After
that the TRX_OFF state is entered.
Figure 9-18 above illustrates the radio transceiver reset procedure if the radio
transceiver is in any state but not in SLEEP state.
If the radio transceiver was in SLEEP state, the SLPTR bit in the TRXPR register must
be cleared prior to clearing the TRXRST bit in order to enter the TRX_OFF state.
Otherwise the radio transceiver enters the SLEEP state immediately.
If the radio transceiver was in SLEEP state and the Transceiver Clock is not selected as
the microcontroller clock source, the XOSC is enabled before entering TRX_OFF state.
If register TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during
system initialization until the radio transceiver reaches TRX_OFF, do not try to initiate a
further state change while the radio transceiver is in this state.
Note that before accessing the radio transceiver module the TRX24_AWAKE event
should be checked.
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9.4.1.4.5 State Transition Timing Summary
The transition numbers correspond to Table 9-4 below. See measurement setup in
"Basic Application Schematic" on page 540.
Table 9-4. Radio Transceiver State Transition Timing
No Symbol
Transition Time [µs], (typ) Comments
1 tTR2 SLEEP TRX_OFF 240 Depends on crystal oscillator setup (CL = 10 pf)
TRX_OFF state indicated by TRX24_AWAKE interrupt
2 tTR3 TRX_OFF SLEEP 35 · 1 / fCLKM For fCLKM > 250 kHz
3 tTR4 TRX_OFF PLL_ON 110 Depends on external capacitor at AVDD (1 µF nom)
4 tTR5 PLL_ON TRX_OFF 1
5 tTR6 TRX_OFF RX_ON 110 Depends on external capacitor at AVDD (1 µF nom)
6 tTR7 RX_ON TRX_OFF 1
7 tTR8 PLL_ON RX_ON 1
8 tTR9 RX_ON PLL_ON 1 Transition time is also valid for TX_ARET_ON, RX_AACK_ON
9 tTR10 PLL_ON BUSY_TX 16
When setting bit SLPTR or TRX_CMD = TX_START, the first
symbol transmission is delayed by 16 µs (PLL settling and
PA ramp up).
10 tTR11 BUSY_TX PLL_ON 32 PLL settling time from TX_BUSY to PLL_ON state
11 tTR12 All modes TRX_OFF 1
Using TRX_CMD = FORCE_TRX_OFF (see register
TRX_STATE),
Not valid for SLEEP state
12 tTR13 RESET TRX_OFF 37 Not valid for SLEEP state
13 tTR14 Various
states PLL_ON 1
Using TRX_CMD = FORCE_PLL_ON (see register
TRX_STATE),
Not valid for SLEEP, RESET and TRX_OFF
The state transition timing is calculated based on the timing of the individual blocks
shown in Table 9-9 on page 55. The worst case values include maximum operating
temperature, minimum supply voltage, and device parameter variations.
Table 9-9. Analog Block Initialization and Settling Time
No Symbol
Block Time [µs], (typ) Time [µs], (max)
Comments
15 tTR15 XOSC 215 1000 Leaving SLEEP state, depends on crystal Q factor and load
capacitor
16 tTR16 FTN 25 FTN tuning time, fixed
17 tTR17 DVREG 60 1000 Depends on external bypass capacitor at DVDD
(CB3 = 1 µF nom., 10 µF worst case), depends on VDEVDD
18 tTR18 AVREG 60 1000 Depends on external bypass capacitor at AVDD
(CB1 = 1 µF nom., 10 µF worst case) , depends on VEVDD
19 tTR19 PLL, initial 110 155 PLL settling time TRX_OFF PLL_ON, including 60 µs
AVREG settling time
20 tTR20 PLL, settling 11 24 Settling time between channel switch
21 tTR21 PLL, CF cal 35 PLL center frequency calibration, refer to "Calibration
Loops" on page 89
22 tTR22 PLL, DCU cal 6 PLL DCU calibration, refer to "Calibration Loops" on
page 89
23 tTR23 PLL, RX TX
16 Maximum PLL settling time RX TX
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No Symbol
Block Time [µs], (typ) Time [µs], (max)
Comments
24 tTR24 PLL, TX RX
32 Maximum PLL settling time TX RX
25 tTR25 RSSI, update 2 RSSI update period in receive states, refer to "Reading
RSSI" on page 74
26 tTR26 ED 140 ED measurement period, refer to "Measurement
Description" on page 75
27 tTR27 SHR, sync 96 Typical SHR synchronization period, refer to
"Measurement Description" on page 75
28 tTR28 CCA 140 CCA measurement period, refer to "Configuration and
CCA Request" on page 77
29 tTR29 Random value
1 Random value update period, refer to "Random
Number Generator" on page 92
9.4.2 Extended Operating Mode
The Extended Operating Mode is a hardware MAC accelerator and goes beyond the
basic radio transceiver functionality provided by the Basic Operating Mode. It handles
time critical MAC tasks requested by the IEEE 802.15.4 standard or by hardware such
as automatic acknowledgement, automatic CSMA-CA and retransmission. This results
in a more efficient IEEE 802.15.4 software MAC implementation including reduced code
size and may allow operating at lower microcontroller clock rates.
The Extended Operating Mode is designed to support IEEE 802.15.4-2006 compliant
frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non
IEEE 802.15.4 compliant frames. This mode comprises the following procedures:
Automatic acknowledgement (RX_AACK) divides into the tasks:
Frame reception and automatic FCS check;
Configurable addressing fields check;
Interrupt indicating address match;
Interrupt indicating frame reception, if it passes address filtering and FCS check;
Automatic ACK frame transmission (if the received frame passed the address filter
and FCS check and if an ACK is required by the frame type and ACK request);
Support of slotted acknowledgment using SLPTR bit for frame start.
Automatic CSMA-CA and Retransmission (TX_ARET) divides into the tasks:
CSMA-CA including automatic CCA retry and random back-off;
Frame transmission and automatic FCS field generation;
Reception of ACK frame (if an ACK was requested);
Automatic frame retry if ACK was expected but not received;
Interrupt signaling with transaction status.
Automatic FCS check and generation (refer to "Frame Check Sequence (FCS)" on
page 72) is used by the RX_AACK and TX_ARET modes. In RX_AACK mode an
automatic FCS check is always performed for incoming frames.
An ACK received in TX_ARET mode within the time required by IEEE 802.15.4 is
accepted if the FCS is valid and if the sequence number of the ACK matches the
sequence number of the previously transmitted frame. Dependent on the value of the
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frame pending subfield in the received acknowledgement frame the transaction status is
set according to Table 9-19 on page 64.
The state diagram including the Extended Operating Mode states is shown in Figure 9-
19 below. Yellow marked states represent the Basic Operating Mode; blue marked
states represent the Extended Operating Mode.
Figure 9-19. Extended Operating Mode State Diagram
2
SLPTR = 1
L e g e n d :
B lu e : R e g is te r W rite to T R X _ S T A T E
R e d : C o n tro l s ig n a ls v ia R e g is te r T R X P R
G r e e n : E v e n t
B a s ic O p e ra tin g M o d e S ta te s
E x te n d e d O p e ra tin g M o d e S ta te s
SLPTR = 0
PLL_ON
R X _ O N
P L L _ O N
T R X _ O F F
(C lo c k S ta te )
X O S C = O N
RX_ON
SLEEP
(S le e p S ta t e )
X O S C = O F F
F O R C E _ T R X _ O F F
(a ll m od e s e x c e p t S L E E P )
F ra m e
E n d