MC14538B Datasheet by onsemi

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0N .‘yemilml'uluctor® @ l Q Q H H H H H H H H H H 1" H H l" 1" Fl Unique Site and Control Change Requiremenls: AEC—QIOO 0 Qualified and PPAP Capable l—Il—quuuuu o - These Devices are Pb—Free and are Rel-ls Compliam H H H H H H H H MAXIMUM RATINGS (vdliages Relerenced id Vssl Symbol parameier Value Unit VDD DC Supply Vollage Range 70.5w +120 v ”HR” ‘neflflnnflnfl vm, van. lnpul cr Dulpul vdliage Range 70.5 id VDD i 0.5 v we cr Transienil lin, lam lnpuicrOuipulCulrenl :10 mA ° ' ISIUULILIULIU lac cr Transienl) per Pin H H H H H H i PD Power Dissipalicn, pei Package 500 mW iNcie l) a A e Assembly L TA Opelallng Tempelalure Range 755 to +125 C WL‘ L = Walel Lai Tsig Siorage Temperaiure Range 755 lg +150 no N Y e Year ww w e wdik Week TL Lead Temperaiure 260 no ‘ {BeSecond Solderlng) G 0' ' = “PM“? ‘" Siresses exceedlng lhose iisied m ine Maximum naimgs lable may damage ine device. ii any of inese iimils are exceeded, device luneiidnaliiy should nai be assumed damage may deeui and reliabiliiy may be alleeied, l, Tempelalure Deraimg. “D/DW" Packagesem mW/“C From 55%: T0125°C ORDERING INFORM This device caniains proleciicn clleuiily ic guard againsi damage due to high See Walled Warm and shlpplng mla slalic vdiiages cr eleclrlc llelds. Howeven precauiians musl be laken la avcld d'me"5‘°"559c"°" 0” Page 2 “W5 “ appllcallons of any vciiage nigher inan maximum raled vdliages Io inis highelmpedance eireuii, For prcper cperaiidn, VW and van. should be ecnsliamed ic me range v55 s (vm cr vml s VDD. Unused mpuis musi always he lied to an appmpllale logic vdliage level (e.g., enher v55 cr VDD) Unused duipuls musi be leli cpen, m SemlcunfluclulCnmpcnenls lndusmes. LLC 2m 1 Publica July, 2014 — Rev. ll
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 11 1Publication Order Number:
MC14538B/D
MC14538B
Dual Precision
Retriggerable/Resettable
Monostable Multivibrator
The MC14538B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an accurate output pulse over a wide range of widths, the
duration and accuracy of which are determined by the external timing
components, CX and RX. Output Pulse Width T = RX @ CX (secs)
RX = W
CX = Farads
Features
Unlimited Rise and Fall Time Allowed on the A Trigger Input
Pulse Width Range = 10 ms to 10 s
Latched Trigger Inputs
Separate Latched Reset Inputs
3.0 Vdc to 18 Vdc Operational Limits
Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)
Use the MC54/74HC4538A for Pulse Widths Less Than 10 ms with
Supplies Up to 6 V
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range 0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range
(DC or Transient) 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin ±10 mA
PDPower Dissipation, per Package
(Note 1) 500 mW
TAOperating Temperature Range 55 to +125 °C
Tstg Storage Temperature Range 65 to +150 °C
TLLead Temperature
(8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING DIAGRAMS
SOIC−16WB
DW SUFFIX
CASE 751G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Indicator
SOEIAJ−16
F SUFFIX
CASE 966
MC14538B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
16
14538BG
AWLYYWW
16
1
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
14538BG
AWLYWW
1
16
14
538B
ALYWG
G
1
16
(Note: Microdot may be in either location)
SOIC−16WB
SOEIAJ−16
SOIC−16
TSSOP−16
MC14538B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
AB
RESET B
CX/RXB
VSS
VDD
QB
QB
BB
AA
RESET A
CX/RXA
VSS
VSS
QA
QA
BA
BLOCK DIAGRAM
VDD
VDD
6
7
10
9
12
11
5
4A
B
CXRX
12
Q1
Q1
RESET
3
CXRX
15 14
Q2
Q2
RESET
13
A
B
RX AND CX ARE EXTERNAL COMPONENTS.
VDD = PIN 16
VSS = PIN 8, PIN 1, PIN 15
ONE−SHOT SELECTION GUIDE
100 ns
MC14528B
MC14536B
MC14538B
MC14541B
MC4538A*
1 ms 10 ms100 ms1 ms 10 ms 100 ms 1 s 10 s
*LIMITED OPERATING VOLTAGE (2 - 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
23 HR
5 MIN.
ORDERING INFORMATION
Device Package Shipping
MC14538BDG SOIC−16
(Pb−Free) 48 Units / Rail
NLV14538BDG* SOIC−16
(Pb−Free) 48 Units / Rail
MC14538BDR2G SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
NLV14538BDR2G* SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
MC14538BDTR2G TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
NLV14538BDTR2G* TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
MC14538BDWG SOIC−16 WB
(Pb−Free) 47 Units / Rail
NLV14538BDWG* SOIC−16 WB
(Pb−Free) 47 Units / Rail
MC14538BDWR2G SOIC−16 WB
(Pb−Free) 1000 Units / Tape & Reel
NLV14538BDWR2G* SOIC−16 WB
(Pb−Free) 1000 Units / Tape & Reel
MC14538BFG SOEIAJ−16
(Pb−Free) 50 Units / Rail
MC14538BFELG SOEIAJ−16
(Pb−Free) 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14538B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbo
l
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
VOL 5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
–1.7
–0.36
–0.9
–2.4
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current, Pin 2 or 14 Iin 15 ±0.05 ±0.00001 ±0.05 − ±0.5 mAdc
Input Current, Other Inputs Iin 15 ±0.1 ±0.00001 ±0.1 ±1.0 mAdc
Input Capacitance, Pin 2 or 14 Cin − − − − 25 − − − pF
Input Capacitance, Other Inputs
(Vin = 0)
Cin − − − − 5.0 7.5 − − pF
Quiescent Current
(Per Package)
Q = Low, Q = High
IDD 5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
mAdc
Quiescent Current, Active State
(Both) (Per Package)
Q = High, Q = Low
IDD 5.0
10
15
2.0
2.0
2.0
0.04
0.08
0.13
0.20
0.45
0.70
2.0
2.0
2.0
mAdc
Total Supply Current at an external
load capacitance (CL) and at
external timing network (RX, CX)
(Note 3)
IT5.0
10
IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf
IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf
IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf
where: IT in mA (one monostable switching only),
where: CX in mF, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
OPERATING CONDITIONS
External Timing Resistance RX 5.0 (Note 4) kW
External Timing Capacitance CX 0 No Limit
(Note 5)
mF
4. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board
layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MW..
5. If CX > 15 mF, use discharge protection diode per Fig. 11.
MC14538B
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SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD
Vdc
All Types
Unit
Min Typ
(Note 7) Max
Output Rise Time
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH 5.0
10
15
100
50
40
200
100
80
ns
Output Fall Time
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL 5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
A or B to Q or Q
tPLH, tPHL = (0.90 ns/pF) CL + 255 ns
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns
tPLH, tPHL = (0.26 ns/pF) CL + 87 ns
tPLH,
tPHL 5.0
10
15
300
150
100
600
300
220
ns
Reset to Q or Q
tPLH, tPHL = (0.90 ns/pF) CL + 205 ns
tPLH, tPHL = (0.36 ns/pF) CL + 107 ns
tPLH, tPHL = (0.26 ns/pF) CL + 82 ns
5.0
10
15
250
125
95
500
250
190
ns
Input Rise and Fall Times
Reset
tr, tf5
10
15
15
5
4
ms
B Input 5
10
15
300
1.2
0.4
1.0
0.1
0.05
ms
A Input 5
10
15
No Limit
Input Pulse Width
A, B, or Reset
tWH,
tWL
5.0
10
15
170
90
80
85
45
40
ns
Retrigger Time trr 5.0
10
15
0
0
0
ns
Output Pulse Width — Q or Q
Refer to Figures 8 and 9
CX = 0.002 mF, RX = 100 kW
T
5.0
10
15
198
200
202
210
212
214
230
232
234
ms
CX = 0.1 mF, RX = 100 kW5.0
10
15
9.3
9.4
9.5
9.86
10
10.14
10.5
10.6
10.7
ms
CX = 10 mF, RX = 100 kW5.0
10
15
0.91
0.92
0.93
0.965
0.98
0.99
1.03
1.04
1.06
s
Pulse Width Match between circuits in
the same package.
CX = 0.1 mF, RX = 100 kW
100
[(T1 – T2)/T1]
5.0
10
15
±1.0
±1.0
±1.0
±5.0
±5.0
±5.0
%
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figu
MC14538B
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Figure 1. Logic Diagram
(1/2 of DevIce Shown)
NOTE: Pins 1, 8 and 15 must
be externally grounded
-
+
-
+
VDD VDD
P1
RX
CX
2
1
(14)
(15)
4 (12)
5(11)
3 (13)
A
B
RESET
VSS
N1
Vref1
C1 C2
ENABLE
Vref2
ENABLE
CONTROL
SRESET LATCH
QRQR
RS
R
S
Q
Q
6(10)
7(9)
OUTPUT
LATCH
Figure 2. Power Dissipation Test Circuit and Waveforms
500 pF
VDD
0.1 mF
CERAMIC
RXRX
CXVSS
CX
VSS
Vin CX/RX
A
B
RESET
A
B
RESET
Q
Q
Q
Q
VSS
CL
CL
CL
CL20 ns 20 ns
VDD
0 V
90%
10%
Vin
ID
INPUT CONNECTIONS
Characteristics Reset A B
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD PG1 VDD
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD VSS PG2
tPLH(R), tPHL(R),
tWH, tWL
PG3 PG1 PG2
Figure 3. Switching Test Circuit
*Includes capacitance of probes,
wiring, and fixture parasitic.
NOTE: Switching test waveforms
for PG1, PG2, PG3 are shown
In Figure 4.
VDD
RXRX
VSS
CX
CX/RX
A
B
RESET
A
B
RESET
Q
Q
Q
Q
CL
CX
CL
CL
CL
VSS
PULSE
GENERATOR
PULSE
GENERATOR
PULSE
GENERATOR
VSS
*CL = 50 pF
PG1 =
PG2 =
PG3 =
:mu megso pF 777 ONE MONOSTABLE SWITCH‘NG ONLY Kl pp a: ‘ VDD:15\I xf
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Figure 4. Switching Test Waveforms
RESET
A
B
tPLH
Q
Q
50%
tWH
90%
10%
tTLH tTHL
tWL
tTHL tPHL
tTHL
90%
10%
50%
T
50% 50% 50% 90%
10%
tPLH tTHL tTLH tPHL
tWL
50%
90%
10%
tPHL tPHL
tTLH tTHL tPLH
50% 50% 90%
10% 50%
50%
50%
trr
50% VDD
VDD
VDD
tTLH
Figure 5. Typical Normalized Distribution
of Units for Output Pulse Width Figure 6. Typical Pulse Width Variation as
a Function of Supply Voltage VDD
0
0.2
0.4
0.6
0.8
1.0
-4 -2 0 2 4
T, OUTPUT PULSE WIDTH (%)
RELATIVE FREQUENCY OF OCCURRENCE
2
1
0
1
2
15141312111098765
VDD, SUPPLY VOLTAGE (VOLTS)
NORMALIZED PULSE WIDTH CHANGE
WITH RESPECT TO VALUE AT VDD = 10 V (%)
TA = 25°C
RX = 100 kW
CX = 0.1 mF
0% POINT PULSE WIDTH
VDD = 5.0 V, T = 9.8 ms
VDD = 10 V, T = 10 ms
VDD = 15 V, T = 10.2 ms
RX = 100 kW
CX = 0.1 mF
Figure 7. Typical Total Supply Current
versus Output Duty Cycle
TOTAL SUPPLY CURRENT ( A)μ
1000
100
10
1.0
0.1
0.001 0.1 1.0 10 100
OUTPUT DUTY CYCLE (%)
RX = 100 kW, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY
VDD = 15 V
10 V
5.0 V
FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H L Not Triggered
H H Not Triggered
HL, H, HNot Triggered
H L L, H, Not Triggered
L X X L H
X X Not Triggered
:IOV1%) : IoV1%)
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Figure 8. Typical Error of Pulse Width
Equation versus Temperature Figure 9. Typical Error of Pulse Width
Equation versus Temperature
-2
-1
0
1
2
-60 -40 -20 0 20 40 60 80 100 120 140
TA, AMBIENT TEMPERATURE (°C)
TYPICAL NORMALIZED ERROR
WITH RESPECT TO 25 DD = 10 V (%
)
°C VALUE AT V
RX = 100 kW
CX = 0.1 mFVDD = 15 V
VDD = 10 V
VDD = 5 V
-2.0
-1.0
0
1.0
2.0
3.0
-3.0
-60 -40 -20 0 20 40 60 80 100 120 140
TA, AMBIENT TEMPERATURE (°C)
RX = 100 kW
CX = .002 mF
VDD = 15 V
VDD = 10 V
VDD = 5.0 V
TYPICAL NORMALIZED ERROR
WITH RESPECT TO 25 DD = 10 V (%
)
°C VALUE AT V
THEORY OF OPERATION
2
Figure 10. Timing Operation
Positive edge re−trigger (pulse lengthening)Positive edge trigger
1
2
3 4
5
1
3
4
5
RESET
A
B
CX/RX
Q
Vref1 Vref1 Vref1 Vref1
Vref2 Vref2 Vref2 Vref2
T T T
Negative edge trigger
Positive edge trigger
Positive edge re−trigger (pulse lengthening)
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TRIGGER OPERATION
The block diagram of the MC14538B is shown in
Figure 1, with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
to VDD. When the trigger input A goes from VSS to VDD
(while inputs B and Reset are held to VDD) a valid trigger is
recognized, which turns on comparator C1 and N−channel
transistor N1 . At the same time the output latch is set. With
transistor N1 on, the capacitor CX rapidly discharges toward
VSS until Vref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
comparator C2 turns on. With transistor N1 off, the capacitor
CX begins to charge through the timing resistor, RX, toward
VDD. When the voltage across CX equals Vref 2, comparator
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 . This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
In the quiescent state, CX is fully charged to VDD causing
the current through resistor RX to be zero. Both comparators
are “off” with total device current due only to reverse
junction leakages. An added feature of the MC14538B is
that the output latch is set via the input trigger without regard
to the capacitor voltage. Thus, propagation delay from
trigger to Q is independent of the value of CX, RX, or the duty
cycle of the input waveform.
RETRIGGER OPERATION
The MC14538B is retriggered if a valid trigger occurs
followed by another valid trigger before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Vref 1, but has not yet reached Vref 2, will cause an increase
in output pulse width T. When a valid retrigger is initiated
, the voltage at CX/RX will again drop to Vref 1 before
progressing along the RC charging curve toward VDD. The
Q output will remain high until time T, after the last valid
retrigger.
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor P1 . When the
voltage on the capacitor reaches Vref 2, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level
is detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width
specification.
POWER−DOWN CONSIDERATIONS
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
discharge from VDD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
VDD supply must not be faster than (VDD). (C)/(10 mA).
For example, if VDD = 10 V and CX = 10 mF, the VDD supply
should discharge no faster than (10 V) x (10 mF)/(10 mA)
= 10 ms. This is normally not a problem since power
supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of VDD to zero volts occurs,
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11.
Figure 11. Use of a Diode to Limit
Power Down Current Surge
VSS
Dx
VDD
VDD
Rx
Cx
Q
Q
RESET
3% ‘H %\ H? ?
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Figure 12. Retriggerable
Monostables Circuitry Figure 13. Non−Retriggerable
Monostables Circuitry
CXRX
VDD
Q
Q
RESET = VDD
B = VDD
A
B
RISING-EDGE
TRIGGER
CXRX
VDD
Q
Q
RESET = VDD
B
A = VSS
FALLING-EDGE
TRIGGER
CXRX
VDD
Q
Q
A
B
RESET = VDD
CXRX
VDD
Q
Q
RESET = VDD
A
B
FALLING-EDGE
TRIGGER
RISING-EDGE
TRIGGER
NC
NC
NC
VDD
VDD
A
B
Figure 14. Connection of Unused Sections
Q
Q
CD
TYPICAL APPLICATIONS
r—\ HiHiHifiiHiFI’H 7’ '5 7 a) n F 69 O 0 Hit ItHiHiHiHJii, g L fim§EEE§§%EJ ilrng IEIEE DDDDMDDD fifilifi MDHDT Eggu +4
MC14538B
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10
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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11
PACKAGE DIMENSIONS
SOIC−16 WB
DW SUFFIX
CASE 751G−03
ISSUE D
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
eT
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
11.00
16X 0.58
16X
1.62 1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
m SECTION N-N PIM 1 mam. JHHHHHHE A |:| im Q mu {u 004) _T— SEAN“: mu: D7 T4 L764 % WWW EH DETAIL E /'\ INIERLEAD ELAsH 0R RRoTRuson INIERLEAD ELAsH 0R RRoTRuson sRALL Not EXCEED a 25 m m n» RER 5qu 5 DW‘ENS‘ON K DOES NOT \NCLUDE DANRAR PRotRuson ALLOWARLE DANRAR PRotRuson SHALL BE 0 03 m any TOIAL \N ExcEss OF IHE K D‘MENS‘ON AT MAXWMuM MATER‘AL coNDmoN s TERM‘NAL NUMBERS ARE SHOWN EoR REEERENcE ONLV 7 DW‘ENS‘ON A AND a ARE TO BE DETERMWED AI DAmM RLANE ,w, MILLIMEYERS mcREs MIN MAX MIN MAX 4 so 5 m a m a 2m 4 so a 5a 0 mg a V 77 L, t 2a m a 047 n as n ‘5 a one a ans n so a 75 a an a 030 n 55 Rsc a was Rsc n m n 23 0 007 a an 9 : Jl Lzmwunmb nus 02a 0004 nuns DETAIL E MHUHHHH http://onsem om l2 J—\ 0L] nus am 0004 was Ms use com um m9 025 mm mm 540 Rsc 0252 Rsc a“ \ a“ a‘ \ a“ :rzx
MC14538B
http://onsemi.com
12
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
mmmmmmmm \\\\1\\\\ T , 77,, + ,77, , <9 ‘="" mmmm="">
MC14538B
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13
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
CASE 966
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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