Spartan-3 FPGA Datasheet

Xilinx Inc.

View All Related Products | Download PDF Datasheet

Datasheet

DS099 June 27, 2013 www.xilinx.com
Product Specification 1
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Module 1:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
• Introduction
•Features
Architectural Overview
Array Sizes and Resources
User I/O Chart
Ordering Information
Module 2: Functional Description
DS099 (v3.1) June 27, 2013
Input/Output Blocks (IOBs)
IOB Overview
SelectIO™ Interface I/O Standards
Configurable Logic Blocks (CLBs)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
• Configuration
Module 3:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
DC Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
DC Characteristics
Switching Characteristics
I/O Timing
Internal Logic Timing
DCM Timing
Configuration and JTAG Timing
Module 4: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Pin Descriptions
Pin Behavior During Configuration
Package Overview
•Pinout Tables
•Footprints
1Spartan-3 FPGA Family
Data Sheet
DS099 June 27, 2013 Product Specification
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 2
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Introduction
The Spartan®-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
5,000,000 system gates, as shown in Ta b l e 1 .
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from the Virtex®-II platform
technology. These Spartan-3 FPGA enhancements,
combined with advanced process technology, deliver more
functionality and bandwidth per dollar than was previously
possible, setting new standards in the programmable logic
industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home
networking, display/projection and digital television
equipment.
The Spartan-3 family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
Densities up to 74,880 logic cells
SelectIO™ interface signaling
Up to 633 I/O pins
622+ Mb/s data transfer rate per I/O
18 single-ended signal standards
8 differential I/O standards including LVDS, RSDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.465V
Double Data Rate (DDR) support
DDR, DDR2 SDRAM support up to 333 Mb/s
Logic resources
Abundant logic cells with shift register capability
Wide, fast multiplexers
Fast look-ahead carry logic
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
SelectRAM™ hierarchical memory
Up to 1,872 Kbits of total block RAM
Up to 520 Kbits of total distributed RAM
Digital Clock Manager (up to four DCMs)
Clock skew elimination
Frequency synthesis
High resolution phase shifting
Eight global clock lines and abundant routing
Fully supported by Xilinx ISE® and WebPACK™ software
development systems
MicroBlaze™ and PicoBlaze™ processor, PCI®,
PCI Express® PIPE Endpoint, and other IP cores
Pb-free packaging options
Automotive Spartan-3 XA Family variant
8Spartan-3 FPGA Family:
Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 Product Specification
Table 1: Summary of Spartan-3 FPGA Attributes
Device System
Gates
Equivalent
Logic Cells(1)
CLB Array
(One CLB = Four Slices) Distributed
RAM Bits
(K=1024)
Block
RAM Bits
(K=1024)
Dedicated
Multipliers DCMs Max.
User I/O
Maximum
Differential
I/O Pairs
Rows Columns Total
CLBs
XC3S50(2) 50K 1,728 16 12 192 12K 72K 4 2 124 56
XC3S200(2) 200K 4,320 24 20 480 30K 216K 12 4 173 76
XC3S400(2) 400K 8,064 32 28 896 56K 288K 16 4 264 116
XC3S1000(2) 1M 17,280 48 40 1,920 120K 432K 24 4 391 175
XC3S1500 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221
XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270
XC3S4000 4M 62,208 96 72 6,912 432K 1,728K 96 4 633 300
XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 633 300
Notes:
1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 3
Architectural Overview
The Spartan-3 family architecture consists of five fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical
functions as well as to store data.
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB
supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight
high-performance differential standards, are available as shown in Ta ble 2 . Double Data-Rate (DDR) registers are
included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board
designs.
Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product.
Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying,
dividing, and phase shifting clock signals.
These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a
single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several
18-Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer
block RAM columns.
The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements,
transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections
to the routing.
Configuration
Spartan-3 FPGAs are programmed by loading configuration data into robust reprogrammable static CMOS configuration
latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA,
configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying
X-Ref Target - Figure 1
Figure 1: Spartan-3 Family Architecture
DS099-1_01_032703
Notes:
1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices
are shown with dashed lines. The XC3S50 has only the block RAM column on the
far left.
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 4
power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit-wide SelectMAP port.
The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which
includes the XCF00S PROMs for serial configuration and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports eighteen single-ended standards and eight differential standards as
listed in Ta b l e 2 . Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal
reflections.
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category Description VCCO (V) Class Symbol
(IOSTANDARD)
DCI
Option
Single-Ended
GTL Gunning Transceiver Logic N/A Terminated GTL Yes
Plus GTLP Yes
HSTL High-Speed Transceiver Logic 1.5 I HSTL_I Yes
III HSTL_III Yes
1.8 I HSTL_I_18 Yes
II HSTL_II_18 Yes
III HSTL_III_18 Yes
LVCMOS Low-Voltage CMOS 1.2 N/A LVCMOS12 No
1.5 N/A LVCMOS15 Yes
1.8 N/A LVCMOS18 Yes
2.5 N/A LVCMOS25 Yes
3.3 N/A LVCMOS33 Yes
LVTTL Low-Voltage Transistor-Transistor Logic 3.3 N/A LVTTL No
PCI Peripheral Component Interconnect 3.0 33 MHz(1) PCI33_3 No
SSTL Stub Series Terminated Logic 1.8 N/A (±6.7 mA) SSTL18_I Yes
N/A (±13.4 mA) SSTL18_II No
2.5 I SSTL2_I Yes
II SSTL2_II Yes
Differential
LDT
(ULVDS)
Lightning Data Transport (HyperTransport™)
Logic
2.5 N/A LDT_25 No
LVDS Low-Voltage Differential Signaling Standard LVDS_25 Yes
Bus BLVDS_25 No
Extended Mode LVDSEXT_25 Yes
LVPECL Low-Voltage Positive Emitter-Coupled Logic 2.5 N/A LVPECL_25 No
RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25 No
HSTL Differential High-Speed Transceiver Logic 1.8 II DIFF_HSTL_II_18 Yes
SSTL Differential Stub Series Terminated Logic 2.5 II DIFF_SSTL2_II Yes
Notes:
1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 5
Ta ble 3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package
combination.
Package Marking
Figure 2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure 3 shows the top marking for
Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the
BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the
ball A1 indicator. Figure 4 shows the top marking for Spartan-3 FPGAs in the CP132 and CPG132 packages.
The “5C” and “4I” part combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C
or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. Some
specifications vary according to mask revision. Mask revision E devices are errata-free. All shipments since 2006 have been
mask revision E.
Table 3: Spartan-3 Device I/O Chart
Available User I/Os and Differential (Diff) I/O Pairs by Package Type
Package VQ100
VQG100
CP132(1)
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG456
FGG456
FG676
FGG676
FG900
FGG900
FG1156(1)
FGG1156
Footprint
(mm) 16x16 8x8 22x22 30.6x30.6 17x17 19x19 23x23 27x27 31x31 35 x 35
Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff
XC3S50 63 29 89(1) 44(1) 97 46 124 56 –––––––––– –
XC3S200 63 29 97 46 141 62 173 76 –––––––– –
XC3S400 ––– 97 46 141 62 173 76 221 100 264 116 – – – –
XC3S1000 ––– – ––– 173 76 221 100 333 149 391 175 – –
XC3S1500 ––– – ––––– 221 100 333 149 487 221 – –
XC3S2000 ––– – ––––––– 333 149 489 221 565 270 – –
XC3S4000 ––– – ––––––––– 489 221 633 300 712(1) 312(1)
XC3S5000 ––– – ––––––––– 489 221 633 300 784(1) 344(1)
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
2. All device options listed in a given package column are pin-compatible.
3. User = Single-ended user I/O pins. Diff = Differential I/O pairs.
X-Ref Target - Figure 2
Figure 2: Spartan-3 FPGA QFP Package Marking Example for Part Number XC3S400-4PQ208C
DS099-1_03_050305
Lot Code
Date Code
Mask Revision Code
Process Technology
XC3S400
TM
PQ208EGQ0525
D1234567A
4C
SPARTAN
Device Type
Package
Speed Grade
Temperature Range
Fabrication Code
Pin P1
R
R
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 6
Ordering Information
Spartan-3 FPGAs are available in both standard (Figure 5) and Pb-free (Figure 6) packaging options for all device/package
combinations. The Pb-free packages include a special ‘G’ character in the ordering code.
For additional information on Pb-free packaging, see XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.
X-Ref Target - Figure 3
Figure 3: Spartan-3 FPGA BGA Package Marking Example for Part Number XC3S1000-4FT256C
X-Ref Target - Figure 4
Figure 4: Spartan-3 FPGA CP132 and CPG132 Package Marking Example for XC3S50-4CP132C
X-Ref Target - Figure 5
Figure 5: Standard Packaging
X-Ref Target - Figure 6
Figure 6: Pb-Free Packaging
DS099-1_04_050305
Lot Code
Date Code
XC3S1000
TM
4C
SPARTAN
Device Type
BGA Ball A1
Package
Speed Grade
Temperature Range
R
R
FT256EGQ0525
D1234567A
Mask Revision Code
Process Code
Fabrication Code
DS099-1_05_092712
Date Code
Temperature Range
Speed Grade
3S50
C5-EGQ 4C
Device Type
Ball A1
Lot Code
Package
C5 = CP132
C6 = CPG132
Mask Revision Code Fabrication Code
F12345 -0525
PHILIPPINES
Process Code
XC3S50 -4 PQ 208 C
Device Type
Speed Grade
Temperature Range:
C = Commercial (Tj = 0°C to 85°C)
I = Industrial (Tj = –40°C to +100°C)
Package Type Number of Pins
Example:
DS099_1_05_020711
XC3S50 -4 PQ G 208 C
Device Type
Speed Grade
Temperature Range:
Package Type Number of Pins
Pb-free
Example:
C = Commercial (Tj = 0°C to 85°C)
I = Industrial (Tj = –40°C to +100°C)
DS099_1_06_020711
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 7
Revision History
Table 4: Example Ordering Information
Device Speed Grade Package Type/Number of Pins Temperature Range (Tj)
XC3S50 -4 Standard Performance VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)
XC3S200 -5 High Performance(1) CP(G)132(2) 132-pin Chip-Scale Package (CSP) I Industrial (–40°C to 100°C)
XC3S400 TQ(G)144 144-pin Thin Quad Flat Pack (TQFP)
XC3S1000 PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP)
XC3S1500 FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
XC3S2000 FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S4000 FG(G)456 456-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S5000 FG(G)676 676-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)900 900-ball Fine-Pitch Ball Grid Array (FBGA)
FG(G)1156(2) 1156-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
2. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Date Version Description
04/11/2003 1.0 Initial Xilinx release.
04/24/2003 1.1 Updated block RAM, DCM, and multiplier counts for the XC3S50.
12/24/2003 1.2 Added the FG320 package.
07/13/2004 1.3 Added information on Pb-free packaging options.
01/17/2005 1.4 Referenced Spartan-3 XA Automotive FPGA families in Ta ble 1 . Added XC3S50CP132,
XC3S2000FG456, XC3S4000FG676 options to Ta b l e 3 . Updated Package Marking to show mask
revision code, fabrication facility code, and process technology code.
08/19/2005 1.5 Added package markings for BGA packages (Figure 3) and CP132/CPG132 packages (Figure 4).
Added differential (complementary single-ended) HSTL and SSTL I/O standards.
04/03/2006 2.0 Increased number of supported single-ended and differential I/O standards.
04/26/2006 2.1 Updated document links.
05/25/2007 2.2 Updated Package Marking to allow for dual-marking.
11/30/2007 2.3 Added XC3S5000 FG(G)676 to Ta bl e 3 . Noted that FG(G)1156 package is being discontinued and
updated max I/O count.
06/25/2008 2.4 Updated max I/O counts based on FG1156 discontinuation. Clarified dual mark in Package Marking.
Updated formatting and links.
12/04/2009 2.5 CP132 and CPG132 packages are being discontinued. Added link to Spartan-3 FPGA customer
notices. Updated Tabl e 3 with package footprint dimensions.
10/29/2012 3.0 Added Notice of Disclaimer section. Per XCN07022, updated the discontinued FG1156 and FGG1156
package discussion throughout document. Per XCN08011, updated the discontinued CP132 and
CPG132 package discussion throughout document. Although the package is discontinued, updated
the marking on Figure 4. This product is not recommended for new designs.
06/27/2013 3.1 Removed banner. This product IS recommended for new designs.
Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 8
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 9
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Spartan-3 FPGA Design Documentation
The functionality of the Spartan®-3 FPGA family is described in the following documents. The topics covered in each guide
are listed.
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-Distributed RAM
-SRL16 Shift Registers
-Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Software Design Tools
•IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
UG332: Spartan-3 Generation Configuration User
Guide
Configuration Overview
-Configuration Pins and Behavior
-Bitstream Sizes
Detailed Descriptions by Mode
-Master Serial Mode using Xilinx Platform Flash
PROM
-Slave Parallel (SelectMAP) using a Processor
-Slave Serial using a Processor
-JTAG Mode
ISE iMPACT Programming Examples
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
Sign Up for Alerts on Xilinx.com
https://secure.xilinx.com/webreg/register.do
?group=myprofile&languageID=1
For specific hardware examples, see the Spartan-3 FPGA
Starter Kit board web page, which has links to various
design examples and the user guide.
Spartan-3 FPGA Starter Kit Board page
http://www.xilinx.com/s3starter
UG130: Spartan-3 FPGA Starter Kit User Guide
57 Spartan-3 FPGA Family:
Functional Description
DS099 (v3.1) June 27, 2013 Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 10
IOBs
For additional information, refer to the chapter entitled “Using I/O Resources” in UG331: Spartan-3 Generation FPGA User
Guide.
IOB Overview
The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal
logic.
A simplified diagram of the IOB’s internal structure appears in Figure 7. There are three main signal paths within the IOB: the
output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or
latches. For more information, see the Storage Element Functions section. The three main signal paths are as follows:
The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay
element directly to the I line. There are alternate routes through a pair of storage elements to the IQ1 and IQ2 lines.
The IOB outputs I, IQ1, and IQ2 all lead to the FPGA’s internal logic. The delay element can be set to ensure a hold
time of zero.
The output path, starting with the O1 and O2 lines, carries data from the FPGA’s internal logic through a multiplexer
and then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to insert
a pair of storage elements.
The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the
FPGA’s internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer provides
the option to insert a pair of storage elements. When the T1 or T2 lines are asserted High, the output driver is
high-impedance (floating, hi-Z). The output driver is active-Low enabled.
All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Any
inverter placed on these paths is automatically absorbed into the IOB.
Storage Element Functions
There are three pairs of storage elements in each IOB, one pair for each of the three paths. It is possible to configure each
of these storage elements as an edge-triggered D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element-pair on either the Output path or the Three-State path can be used together with a special multiplexer
to produce Double-Data-Rate (DDR) transmission. This is accomplished by taking data synchronized to the clock signal’s
rising edge and converting them to bits synchronized on both the rising and the falling edge. The combination of two
registers and a multiplexer is referred to as a Double-Data-Rate D-type flip-flop (FDDR). See Double-Data-Rate
Transmission, page 12 for more information.
The signal paths associated with the storage element are described in Ta bl e 5 .
Tabl e 5 : Storage Element Signal Description
Storage
Element
Signal
Description Function
DData input Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the
input is enabled, data passes directly to the output Q.
QData output The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q will mirror the data at D.
CK Clock input A signal’s active edge on this input with CE asserted, loads data into the storage element.
CE Clock Enable input When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
SR Set/Reset Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The
SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
REV Reverse Used together with SR. Forces storage element into the state opposite from what SR does.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 11
X-Ref Target - Figure 7
Figure 7: Simplified IOB Diagram
D
CE
CK
TFF1
Three-state Path
T
T1
TCE
T2
TFF2
Q
SR
DDR
MUX
REV
D
CE
CK
Q
SR REV
D
CE
CK
OFF1
Output Path
O1
OCE
O2
OFF2
Q
SR
DDR
MUX
Keeper
Latch
VCCO
VREF
Pin
I/O Pin
from
Adjacent
IOB
DS099-2_01_091410
I/O
Pin
Program-
mable
Output
Driver
DCI
ESDPull-Up
Pull-
Down ESD
REV
D
CE
CK
Q
SR REV
OTCLK1
OTCLK2
D
CE
CK
IFF1
Input Path
I
ICE
IFF2
Q
SR
LVCMOS, LVTTL, PCI
Single-ended Standards
using VREF
Differential Standards
REV
D
CE
CK
Q
SR REV
ICLK1
ICLK2
SR
REV
Note: All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
IQ1
IQ2
Fixed
Delay
Fixed
Delay
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 12
According to Figure 7, the clock line OTCLK1 connects the CK inputs of the upper registers on the output and three-state
paths. Similarly, OTCLK2 connects the CK inputs for the lower registers on the output and three-state paths. The upper and
lower registers on the input path have independent clock lines: ICLK1 and ICLK2. The enable line OCE connects the CE
inputs of the upper and lower registers on the output path. Similarly, TCE connects the CE inputs for the register pair on the
three-state path and ICE does the same for the register pair on the input path. The Set/Reset (SR) line entering the IOB is
common to all six registers, as is the Reverse (REV) line.
Each storage element supports numerous options in addition to the control over signal polarity described in the IOB
Overview section. These are described in Ta b l e 6 .
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the technique of synchronizing signals to both the rising and falling edges
of the clock signal. Spartan-3 devices use register-pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path (OFF1 and OFF2), used as registers, combine with a special
multiplexer to form a DDR D-type flip-flop (FDDR). This primitive permits DDR transmission where output data bits are
synchronized to both the rising and falling edges of a clock. It is possible to access this function by placing either an
FDDRRSE or an FDDRCPE component or symbol into the design. DDR operation requires two clock signals (50% duty
cycle), one the inverted form of the other. These signals trigger the two registers in alternating fashion, as shown in Figure 8.
Commonly, the Digital Clock Manager (DCM) generates the two clock signals by mirroring an incoming signal, then shifting
it 180 degrees. This approach ensures minimal skew between the two signals.
The storage-element-pair on the Three-State path (TFF1 and TFF2) can also be combined with a local multiplexer to form
an FDDR primitive. This permits synchronizing the output enable to both the rising and falling edges of a clock. This DDR
operation is realized in the same way as for the output path.
The storage-element-pair on the input path (IFF1 and IFF2) allows an I/O to receive a DDR signal. An incoming DDR clock
signal triggers one register and the inverted clock signal triggers the other register. In this way, the registers take turns
capturing bits of the incoming DDR data signal.
Tabl e 6 : Storage Element Options
Option Switch Function Specificity
FF/Latch Chooses between an edge-sensitive flip-flop or a
level-sensitive latch
Independent for each storage element.
SYNC/ASYNC Determines whether SR is synchronous or
asynchronous
Independent for each storage element.
SRHIGH/SRLOW Determines whether SR acts as a Set, which forces the
storage element to a logic “1" (SRHIGH) or a Reset,
which forces a logic “0” (SRLOW).
Independent for each storage element, except when using
FDDR. In the latter case, the selection for the upper
element (OFF1 or TFF2) applies to both elements.
INIT1/INIT0 In the event of a Global Set/Reset, after configuration
or upon activation of the GSR net, this switch decides
whether to set or reset a storage element. By default,
choosing SRLOW also selects INIT0; choosing
SRHIGH also selects INIT1.
Independent for each storage element, except when using
FDDR. In the latter case, selecting INIT0 for one element
applies to both elements (even though INIT1 is selected
for the other).
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 13
Aside from high bandwidth data transfers, DDR can also be used to reproduce, or “mirror”, a clock signal on the output. This
approach is used to transmit clock and data signals together. A similar approach is used to reproduce a clock signal at
multiple outputs. The advantage for both approaches is that skew across the outputs will be minimal.
Some adjacent I/O blocks (IOBs) share common routing connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock inputs
of both IOBs. These IOB pairs are identified by their differential pair names IO_LxxN_# and IO_LxxP_#, where "xx" is an I/O
pair number and ‘#’ is an I/O bank number. Two adjacent IOBs containing DDR registers must share common clock inputs,
otherwise one or more of the clock signals will be unroutable.
Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. The
pull-up resistor optionally connects each IOB pad to VCCO. A pull-down resistor optionally connects each pad to GND. These
resistors are placed in a design using the PULLUP and PULLDOWN symbols in a schematic, respectively. They can also be
instantiated as components, set as constraints or passed as attributes in HDL code. These resistors can also be selected for
all unused I/O using the Bitstream Generator (BitGen) option UnusedPin. A Low logic level on HSWAP_EN activates the
pull-up resistors on all I/Os during configuration (see The I/Os During Power-On, Configuration, and User Mode, page 21).
The Spartan-3 FPGAs I/O pull-up and pull-down resistors are significantly stronger than the "weak" pull-up/pull-down
resistors used in previous Xilinx FPGA families. See Table 33, page 61 for equivalent resistor strengths.
Keeper Circuit
Each I/O has an optional keeper circuit that retains the last logic level on a line after all drivers have been turned off. This is
useful to keep bus lines from floating when all connected drivers are in a high-impedance state. This function is placed in a
design using the KEEPER symbol. Pull-up and pull-down resistors override the keeper circuit.
X-Ref Target - Figure 8
Figure 8: Clocking the DDR Register
D1
CLK1
DDR MUX
DCM
Q1
FDDR
D2
CLK2
Q2
180˚ 0˚
DS099-2_02_070303
Q
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 14
ESD Protection
Clamp diodes protect all device pads against damage from Electro-Static Discharge (ESD) as well as excessive voltage
transients. Each I/O has two clamp diodes: One diode extends P-to-N from the pad to VCCO and a second diode extends
N-to-P from the pad to GND. During operation, these diodes are normally biased in the off state. These clamp diodes are
always connected to the pad, regardless of the signal standard selected. The presence of diodes limits the ability of
Spartan-3 FPGA I/Os to tolerate high signal voltages. The VIN absolute maximum rating in Table 28, page 58 specifies the
voltage range that I/Os can tolerate.
Slew Rate Control and Drive Strength
Two options, FAST and SLOW, control the output slew rate. The FAST option supports output switching at a high rate. The
SLOW option reduces bus transients. These options are only available when using one of the LVCMOS or LVTTL standards,
which also provide up to seven different levels of current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choosing the
appropriate drive strength level is yet another means to minimize bus transients.
Ta bl e 7 shows the drive strengths that the LVCMOS and LVTTL standards support.
Boundary-Scan Capability
All Spartan-3 FPGA IOBs support boundary-scan testing compatible with IEEE 1149.1 standards. During boundary- scan
operations such as EXTEST and HIGHZ the I/O pull-down resistor is active. For more information, see Boundary-Scan
(JTAG) Mode, page 50, and refer to the “Using Boundary-Scan and BSDL Files” chapter in UG331.
SelectIO Interface Signal Standards
The IOBs support 18 different single-ended signal standards, as listed in Ta b l e 8 . Furthermore, the majority of IOBs can be
used in specific pairs supporting any of eight differential signal standards, as shown in Tab l e 9 .
To define the SelectIO interface signaling standard in a design, set the IOSTANDARD attribute to the appropriate setting.
Xilinx provides a variety of different methods for applying the IOSTANDARD for maximum flexibility. For a full description of
different methods of applying attributes to control IOSTANDARD, refer to the “Using I/O Resources” chapter in UG331.
Together with placing the appropriate I/O symbol, two externally applied voltage levels, VCCO and VREF, select the desired
signal standard. The VCCO lines provide current to the output driver. The voltage on these lines determines the output
voltage swing for all standards except GTL and GTLP.
All single-ended standards except the LVCMOS, LVTTL, and PCI varieties require a Reference Voltage (VREF) to bias the
input-switching threshold. Once a configuration data file is loaded into the FPGA that calls for the I/Os of a given bank to use
such a signal standard, a few specifically reserved I/O pins on the same bank automatically convert to VREF inputs. When
using one of the LVCMOS standards, these pins remain I/Os because the VCCO voltage biases the input-switching
threshold, so there is no need for VREF
. Select the VCCO and VREF levels to suit the desired single-ended standard according
to Ta bl e 8 .
Tabl e 7 : Programmable Output Drive Current
Signal Standard
(IOSTANDARD)
Current Drive (mA)
2468121624
LVTT L ✓✓✓✓✓✓✓
LVC M OS 33 ✓✓✓✓✓✓✓
LVC M OS 25 ✓✓✓✓✓✓✓
LVC M OS 18 ✓✓✓✓✓✓
LVC M OS 15 ✓✓✓✓✓ – –
LVC M OS 12 ✓✓✓ ––––
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 15
Differential standards employ a pair of signals, one the opposite polarity of the other. The noise canceling (e.g.,
Common-Mode Rejection) properties of these standards permit exceptionally high data transfer rates. This section
introduces the differential signaling capabilities of Spartan-3 devices.
Each device-package combination designates specific I/O pairs that are specially optimized to support differential
standards. A unique “L-number”, part of the pin name, identifies the line-pairs associated with each bank (see Figure 40,
page 112). For each pair, the letters ‘P’ and ‘N’ designate the true and inverted lines, respectively. For example, the pin
names IO_L43P_7 and IO_L43N_7 indicate the true and inverted lines comprising the line pair L43 on Bank 7. The VCCO
lines provide current to the outputs. The VCCAUX lines supply power to the differential inputs, making them independent of
the VCCO voltage for an I/O bank. The VREF lines are not used. Select the VCCO level to suit the desired differential standard
according to Ta b l e 9 .
Tabl e 8 : Single-Ended I/O Standards
Signal Standard
(IOSTANDARD)
VCCO (Volts) VREF for Inputs
(Volts)(1) Board Termination
Voltage (VTT ) in Volts
For Outputs For Inputs
GTL Note 2Note 20.8 1.2
GTLP Note 2Note 211.5
HSTL_I 1.5 – 0.75 0.75
HSTL_III 1.5 –0.9 1.5
HSTL_I_18 1.8 –0.9 0.9
HSTL_II_18 1.8 –0.9 0.9
HSTL_III_18 1.8 –1.1 1.8
LVCMOS12 1.2 1.2 – –
LVCMOS15 1.5 1.5 – –
LVCMOS18 1.8 1.8 – –
LVCMOS25 2.5 2.5 – –
LVCMOS33 3.3 3.3 – –
LVTT L 3. 3 3 .3 – –
PCI33_3 3.0 3.0 – –
SSTL18_I 1.8 –0.9 0.9
SSTL18_II 1.8 –0.9 0.9
SSTL2_I 2.5 – 1.25 1.25
SSTL2_II 2.5 – 1.25 1.25
Notes:
1. Banks 4 and 5 of any Spartan-3 device in a VQ100 package do not support signal standards using VREF
.
2. The VCCO level used for the GTL and GTLP standards must be no lower than the termination voltage (VTT), nor can it be lower than the
voltage at the I/O pad.
3. See Table 1 0 for a listing of the single-ended DCI standards.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 16
The need to supply VREF and VCCO imposes constraints on which standards can be used in the same bank. See The
Organization of IOBs into Banks section for additional guidelines concerning the use of the VCCO and VREF lines.
Digitally Controlled Impedance (DCI)
When the round-trip delay of an output signal—i.e., from output to input and back again—exceeds rise and fall times, it is
common practice to add termination resistors to the line carrying the signal. These resistors effectively match the impedance
of a device’s I/O to the characteristic impedance of the transmission line, thereby preventing reflections that adversely affect
signal integrity. However, with the high I/O counts supported by modern devices, adding resistors requires significantly more
components and board area. Furthermore, for some packages—e.g., ball grid arrays—it may not always be possible to
place resistors close to pins.
DCI answers these concerns by providing two kinds of on-chip terminations: Parallel terminations make use of an integrated
resistor network. Series terminations result from controlling the impedance of output drivers. DCI actively adjusts both
parallel and series terminations to accurately match the characteristic impedance of the transmission line. This adjustment
process compensates for differences in I/O impedance that can result from normal variation in the ambient temperature, the
supply voltage and the manufacturing process. When the output driver turns off, the series termination, by definition,
approaches a very high impedance; in contrast, parallel termination resistors remain at the targeted values.
DCI is available only for certain I/O standards, as listed in Ta bl e 1 0 . DCI is selected by applying the appropriate I/O standard
extensions to symbols or components. There are five basic ways to configure terminations, as shown in Ta b le 1 1 . The DCI
I/O standard determines which of these terminations is put into effect.
HSTL_I_DCI-, HSTL_III_DCI-, and SSTL2_I_DCI-type outputs do not require the VRN and VRP reference resistors.
Likewise, LVDCI-type inputs do not require the VRN and VRP reference resistors. In a bank without any DCI I/O or a bank
containing non-DCI I/O and purely HSTL_I_DCI- or HSTL_III_DCI-type outputs, or SSTL2_I_DCI-type outputs or
LVDCI-type inputs, the associated VRN and VRP pins can be used as general-purpose I/O pins.
The HSLVDCI (High-Speed LVDCI) standard is intended for bidirectional use. The driver is identical to LVDCI, while the input
is identical to HSTL. By using a VREF-referenced input, HSLVDCI allows greater input sensitivity at the receiver than when
using a single-ended LVCMOS-type receiver.
Tabl e 9 : Differential I/O Standards
Signal Standard
(IOSTANDARD)
VCCO (Volts) VREF for Inputs (Volts)
For Outputs For Inputs
LDT_25 (ULVDS_25) 2.5 – –
LVDS_25 2.5 – –
BLVDS_25 2.5 – –
LVDSEXT_25 2.5 – –
LVPECL_25 2.5 – –
RSDS_25 2.5 – –
DIFF_HSTL_II_18 1.8 – –
DIFF_SSTL2_II 2.5 – –
Notes:
1. See Table 1 0 for a listing of the differential DCI standards.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 17
Tabl e 1 0 : DCI I/O Standards
Category of Signal
Standard
Signal Standard
(IOSTANDARD)
VCCO (V) VREF for
Inputs (V)
Termination Type
For Outputs For Inputs At Output At Input
Single-Ended
Gunning
Transceiver Logic
GTL_DCI 1.2 1.2 0.8 Single Single
GTLP_DCI 1.5 1.5 1.0
High-Speed
Transceiver Logic
HSTL_I_DCI 1.5 1.5 0.75 None Split
HSTL_III_DCI 1.5 1.5 0.9 None Single
HSTL_I_DCI_18 1.8 1.8 0.9 None
Split
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI 1.8 1.8 0.9 Split
HSTL_III_DCI_18 1.8 1.8 1.1 None Single
Low-Voltage CMOS LVDCI_15 1.5 1.5
Controlled
impedance driver
None
LVDCI_18 1.8 1.8
LVDCI_25 2.5 2.5
LVDCI_33(2) 3.3 3.3
LVDCI_DV2_15 1.5 1.5
Controlled driver
with
half-impedance
LVDCI_DV2_18 1.8 1.8
LVDCI_DV2_25 2.5 2.5
LVDCI_DV2_33 3.3 3.3
Hybrid HSTL Input
and LVCMOS Output
HSLVDCI_15 1.5 1.5 0.75
Controlled
impedance driver None
HSLVDCI_18 1.8 1.8 0.9
HSLVDCI_25 2.5 2.5 1.25
HSLVDCI_33 3.3 3.3 1.65
Stub Series
Terminated Logic(3) SSTL18_I_DCI 1.8 1.8 0.9 25Ω driver
Split
SSTL2_I_DCI 2.5 2.5 1.25 25Ω driver
SSTL2_II_DCI
DIFF_SSTL2_II_DCI 2.5 2.5 1.25 Split with 25Ω driver
Differential
Low-Voltage
Differential Signaling
LVDS_25_DCI N/A 2.5 None Split on each
line of pair
LVDSEXT_25_DCI N/A 2.5
Notes:
1. DCI signal standards are not supported in Bank 5 of any Spartan-3 FPGA packaged in a VQ100, CP132, or TQ144 package.
2. Equivalent to LVTTL DCI.
3. The SSTL18_II signal standard does not have a DCI equivalent.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 18
Tabl e 1 1 : DCI Terminations
Termination Schematic(1) Signal Standards
(IOSTANDARD)
Controlled impedance output driver LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
Controlled output driver with half impedance LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
Single resistor GTL_DCI
GTLP_DCI
HSTL_III_DCI(2)
HSTL_III_DCI_18(2)
Split resistors HSTL_I_DCI(2)
HSTL_I_DCI_18(2)
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
Split resistors with output driver impedance fixed
to 25Ω
SSTL18_I_DCI(3)
SSTL2_I_DCI(3)
SSTL2_II_DCI
Notes:
1. The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of RREF for the
DV2 standards and RREF for all other DCI standards.
2. For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
3. For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
Z0
IOB
ds099_06a_070903
R
Z0
IOB
ds099_06b_070903
R/2
RZ0
VCCO
IOB
ds099_06c_070903
2R
2R Z0
VCCO
IOB
ds099_06d_070903
25Ω
2R
2R Z0
VCCO
IOB
ds099_06e_070903
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 19
The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and
a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using a DCI standard on a given bank
do these two pins function as VRN and VRP. When not using a DCI standard, the two pins function as user I/Os. As shown
in Figure 9, add an external reference resistor to pull the VRN pin up to VCCO and another reference resistor to pull the VRP
pin down to GND. Also see Figure 42, page 116. Both resistors have the same value—commonly 50Ω—with one-percent
tolerance, which is either the characteristic impedance of the line or twice that, depending on the DCI standard in use.
Standards having a symbol name that contains the letters “DV2” use a reference resistor value that is twice the line
impedance. DCI adjusts the output driver impedance to match the reference resistors’ value or half that, according to the
standard. DCI always adjusts the on-chip termination resistors to directly match the reference resistors’ value.
The rules guiding the use of DCI standards on banks are as follows:
No more than one DCI I/O standard with a Single Termination is allowed per bank.
No more than one DCI I/O standard with a Split Termination is allowed per bank.
Single Termination, Split Termination, Controlled- Impedance Driver, and Controlled-Impedance Driver with Half
Impedance can co-exist in the same bank.
See also The Organization of IOBs into Banks, immediately below, and DCI: User I/O or Digitally Controlled Impedance
Resistor Reference Input, page 115.
The Organization of IOBs into Banks
IOBs are allocated among eight banks, so that each side of the device has two banks, as shown in Figure 10. For all
packages, each bank has independent VREF lines. For example, VREF Bank 3 lines are separate from the VREF lines going
to all other banks.
For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine Pitch Ball
Grid Array (FG) packages, each bank has dedicated VCCO lines. For example, the VCCO Bank 7 lines are separate from the
VCCO lines going to all other banks. Thus, Spartan-3 devices in these packages support eight independent VCCO supplies.
X-Ref Target - Figure 9
Figure 9: Connection of Reference Resistors (RREF)
X-Ref Target - Figure 10
Figure 10: Spartan-3 FPGA I/O Banks (Top View)
DS099-2_04_082104
VCCO
VRN
VRP
One of eight
I/O Banks
RREF (1%)
RREF (1%)
DS099-2_03_082104
Bank 0 Bank 1
Bank 5 Bank 4
Bank 7
Bank 6
Bank 2
Bank 3
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 20
In contrast, the 144-pin Thin Quad Flat Pack (TQ144) package and the 132-pin Chip-Scale Package (CP132) tie VCCO
together internally for the pair of banks on each side of the device. For example, the VCCO Bank 0 and the VCCO Bank 1 lines
are tied together. The interconnected bank-pairs are 0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3 devices in the CP132 and
TQ144 packages support four independent VCCO supplies.
Note: The CP132 package is discontinued. See http://www.xilinx.com/support/documentation /spartan-3_customer_notices.htm.
Spartan-3 FPGA Compatibility
Within the Spartan-3 family, all devices are pin-compatible by package. When the need for future logic resources outgrows
the capacity of the Spartan-3 device in current use, a larger device in the same package can serve as a direct replacement.
Larger devices may add extra VREF and VCCO lines to support a greater number of I/Os. In the larger device, more pins can
convert from user I/Os to VREF lines. Also, additional VCCO lines are bonded out to pins that were “not connected” in the
smaller device. Thus, it is important to plan for future upgrades at the time of the board’s initial design by laying out
connections to the extra pins.
The Spartan-3 family is not pin-compatible with any previous Xilinx FPGA family or with other platforms among the
Spartan-3 Generation FPGAs.
Rules Concerning Banks
When assigning I/Os to banks, it is important to follow the following VCCO rules:
Leave no VCCO pins unconnected on the FPGA.
Set all VCCO lines associated with the (interconnected) bank to the same voltage level.
•The V
CCO levels used by all standards assigned to the I/Os of the (interconnected) bank(s) must agree. The Xilinx
development software checks for this. Tables 8, 9, and 10 describe how different standards use the VCCO supply.
Only one of the following standards is allowed on outputs per bank: LVDS, LDT, LVDS_EXT, or RSDS. This restriction is
for the eight banks in each device, even if the VCCO levels are shared across banks, as in the CP132 and TQ144
packages.
If none of the standards assigned to the I/Os of the (interconnected) bank(s) uses VCCO, tie all associated VCCO lines to
2.5V.
In general, apply 2.5V to VCCO Bank 4 from power-on to the end of configuration. Apply the same voltage to VCCO Bank
5 during parallel configuration or a Readback operation. For information on how to program the FPGA using 3.3V
signals and power, see the 3.3V-Tolerant Configuration Interface section.
If any of the standards assigned to the Inputs of the bank use VREF
, then observe the following additional rules:
Connect all VREF pins within the bank to the same voltage level.
•The V
REF levels used by all standards assigned to the Inputs of the bank must agree. The Xilinx development software
checks for this. Tables 8 and 10 describe how different standards use the VREF supply.
If none of the standards assigned to the Inputs of a bank use VREF for biasing input switching thresholds, all associated VREF
pins function as User I/Os.
Exceptions to Banks Supporting I/O Standards
Bank 5 of any Spartan-3 device in a VQ100, CP132, or TQ144 package does not support DCI signal standards. In this case,
bank 5 has neither VRN nor VRP pins.
Furthermore, banks 4 and 5 of any Spartan-3 device in a VQ100 package do not support signal standards using VREF (see
Ta bl e 8 ). In this case, the two banks do not have any VREF pins.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 21
Supply Voltages for the IOBs
Three different supplies power the IOBs:
•The V
CCO supplies, one for each of the FPGA’s I/O banks, power the output drivers, except when using the GTL and
GTLP signal standards. The voltage on the VCCO pins determines the voltage swing of the output signal.
•V
CCINT is the main power supply for the FPGA’s internal logic.
•The V
CCAUX is an auxiliary source of power, primarily to optimize the performance of various FPGA functions such as
I/O switching.
The I/Os During Power-On, Configuration, and User Mode
With no power applied to the FPGA, all I/Os are in a high-impedance state. The VCCINT (1.2V), VCCAUX (2.5V), and VCCO
supplies may be applied in any order. Before power-on can finish, VCCINT
, VCCO Bank 4, and VCCAUX must have reached
their respective minimum recommended operating levels (see Table 29, page 59). At this time, all I/O drivers also will be in
a high-impedance state. VCCO Bank 4, VCCINT
, and VCCAUX serve as inputs to the internal Power-On Reset circuit (POR).
A Low level applied to the HSWAP_EN input enables pull-up resistors on User I/Os from power-on throughout configuration.
A High level on HSWAP_EN disables the pull-up resistors, allowing the I/Os to float. If the HSWAP_EN pin is floating, then
an internal pull-up resistor pulls HSWAP_EN High. As soon as power is applied, the FPGA begins initializing its
configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously
resets all IOB storage elements to a Low state.
Upon the completion of initialization, INIT_B goes High, sampling the M0, M1, and M2 inputs to determine the configuration
mode. At this point, the configuration data is loaded into the FPGA. The I/O drivers remain in a high-impedance state (with
or without pull-up resistors, as determined by the HSWAP_EN input) throughout configuration.
The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the beginning of design
operation in the User mode. At this point, those I/Os to which signals have been assigned go active while all unused I/Os
remain in a high-impedance state. The release of the GSR net, also part of Start-up, leaves the IOB registers in a Low state
by default, unless the loaded design reverses the polarity of their respective RS inputs.
In User mode, all internal pull-up resistors on the I/Os are disabled and HSWAP_EN becomes a “don’t care” input. If it is
desirable to have pull-up or pull-down resistors on I/Os carrying signals, the appropriate symbol—e.g., PULLUP,
PULLDOWN—must be placed at the appropriate pads in the design. The Bitstream Generator (Bitgen) option UnusedPin
available in the Xilinx development software determines whether unused I/Os collectively have pull-up resistors, pull-down
resistors, or no resistors in User mode.
CLB Overview
For more details on the CLBs, refer to the chapter entitled “Using Configurable Logic Blocks” in UG331.
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four interconnected slices, as shown in Figure 11. These slices are grouped in
pairs. Each pair is organized as a column with an independent carry chain.
The nomenclature that the FPGA Editor—part of the Xilinx development software—uses to designate slices is as follows:
The letter ‘X’ followed by a number identifies columns of slices. The ‘X’ number counts up in sequence from the left side of
the die to the right. The letter ‘Y’ followed by a number identifies the position of each slice in a pair as well as indicating the
CLB row. The ‘Y’ number counts slices starting from the bottom of the die according to the sequence: 0, 1, 0, 1 (the first CLB
row); 2, 3, 2, 3 (the second CLB row); etc. Figure 11 shows the CLB located in the lower left-hand corner of the die. Slices
X0Y0 and X0Y1 make up the column-pair on the left where as slices X1Y0 and X1Y1 make up the column-pair on the right.
For each CLB, the term “left-hand” (or SLICEM) indicates the pair of slices labeled with an even ‘X’ number, such as X0, and
the term “right-hand” (or SLICEL) designates the pair of slices with an odd ‘X’ number, e.g., X1.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 22
Elements Within a Slice
All four slices have the following elements in common: two logic function generators, two storage elements, wide-function
multiplexers, carry logic, and arithmetic gates, as shown in Figure 12, page 24. Both the left-hand and right-hand slice pairs
use these elements to provide logic, arithmetic, and ROM functions. Besides these, the left-hand pair supports two
additional functions: storing data using Distributed RAM and shifting data with 16-bit registers. Figure 12 is a diagram of the
left-hand slice; therefore, it represents a superset of the elements and connections to be found in all slices. See Function
Generator, page 25 for more information.
The RAM-based function generator—also known as a Look-Up Table or LUT—is the main resource for implementing logic
functions. Furthermore, the LUTs in each left-hand slice pair can be configured as Distributed RAM or a 16-bit shift register.
For information on the former, refer to the chapter entitled “Using Look-Up Tables as Distributed RAM” in UG331; for
information on the latter, refer to the chapter entitled “Using Look-Up Tables as Shift Registers” in UG331. The function
generators located in the upper and lower portions of the slice are referred to as the "G" and "F", respectively.
The storage element, which is programmable as either a D-type flip-flop or a level-sensitive latch, provides a means for
synchronizing data to a clock signal, among other uses. The storage elements in the upper and lower portions of the slice
are called FFY and FFX, respectively.
Wide-function multiplexers effectively combine LUTs in order to permit more complex logic operations. Each slice has two of
these multiplexers with F5MUX in the lower portion of the slice and FiMUX in the upper portion. Depending on the slice,
FiMUX takes on the name F6MUX, F7MUX, or F8MUX. For more details on the multiplexers, refer to the chapter entitled
“Using Dedicated Multiplexers” in UG331.
The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math
operations. The carry chain enters the slice as CIN and exits as COUT. Five multiplexers control the chain: CYINIT, CY0F,
and CYMUXF in the lower portion as well as CY0G and CYMUXG in the upper portion. The dedicated arithmetic logic
includes the exclusive-OR gates XORG and XORF (upper and lower portions of the slice, respectively) as well as the AND
gates GAND and FAND (upper and lower portions, respectively). For more details on the carry logic, refer to the chapter
entitled “Using Carry and Arithmetic Logic” in UG331.
Main Logic Paths
Central to the operation of each slice are two nearly identical data paths, distinguished using the terms top and bottom. The
description that follows uses names associated with the bottom path. (The top path names appear in parentheses.) The
basic path originates at an interconnect-switch matrix outside the CLB. Four lines, F1 through F4 (or G1 through G4 on the
X-Ref Target - Figure 11
Figure 11: Arrangement of Slices within the CLB
DS099-2_05_082104
Interconnect
to Neighbors
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
CIN
SLICE
X0Y1
SLICE
X0Y0
Switch
Matrix
COUT
CLB
COUT
SHIFTOUT
SHIFTIN
CIN
SLICE
X1Y1
SLICE
X1Y0
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 23
upper path), enter the slice and connect directly to the LUT. Once inside the slice, the lower 4-bit path passes through a
function generator ‘F’ (or ‘G’) that performs logic operations. The function generator’s Data output, ‘D’, offers five possible
paths:
Exit the slice via line ‘X’ (or ‘Y’) and return to interconnect.
Inside the slice, ‘X’ (or ‘Y’) serves as an input to the DXMUX (DYMUX) which feeds the data input, ‘D’, of the FFX (FFY)
storage element. The ‘Q’ output of the storage element drives the line XQ (or YQ) which exits the slice.
Control the CYMUXF (or CYMUXG) multiplexer on the carry chain.
With the carry chain, serve as an input to the XORF (or XORG) exclusive-OR gate that performs arithmetic operations,
producing a result on ‘X’ (or ‘Y’).
Drive the multiplexer F5MUX to implement logic functions wider than four bits. The ‘D’ outputs of both the F-LUT and
G-LUT serve as data inputs to this multiplexer.
In addition to the main logic paths described above, there are two bypass paths that enter the slice as BX and BY. Once
inside the FPGA, BX in the bottom half of the slice (or BY in the top half) can take any of several possible branches:
Bypass both the LUT and the storage element, then exit the slice as BXOUT (or BYOUT) and return to interconnect.
Bypass the LUT, then pass through a storage element via the D input before exiting as XQ (or YQ).
Control the wide function multiplexer F5MUX (or F6MUX).
Via multiplexers, serve as an input to the carry chain.
Drives the DI input of the LUT.
BY can control the REV inputs of both the FFY and FFX storage elements.
Finally, the DIG_MUX multiplexer can switch BY onto the DIG line, which exits the slice.
Other slice signals shown in Figure 12 are discussed in the sections that follow.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 24
X-Ref Target - Figure 12
Figure 12: Simplified Diagram of the Left-Hand SLICEM
WF[4:1]
DS312-2_32_042007
D
DI
DIWS
Notes:
1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.
2. The index i can be 6, 7, or 8, depending on the slice. In this position, the upper right-hand slice has an F8MUX, and the
upper left-hand slice has an F7MUX. The lower right-hand and left-hand slices both have an F6MUX.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 25
Function Generator
Each of the two LUTs (F and G) in a slice have four logic inputs (A1-A4) and a single output (D). This permits any
four-variable Boolean logic operation to be programmed into them. Furthermore, wide function multiplexers can be used to
effectively combine LUTs within the same CLB or across different CLBs, making logic functions with still more input variables
possible.
The LUTs in both the right-hand and left-hand slice-pairs not only support the logic functions described above, but also can
function as ROM that is initialized with data at the time of configuration.
The LUTs in the left-hand slice-pair (even-numbered columns such as X0 in Figure 11) of each CLB support two additional
functions that the right-hand slice-pair (odd-numbered columns such as X1) do not.
First, it is possible to program the “left-hand LUTs” as distributed RAM. This type of memory affords moderate amounts of
data buffering anywhere along a data path. One left-hand LUT stores 16 bits. Multiple left-hand LUTs can be combined in
various ways to store larger amounts of data. A dual port option combines two LUTs so that memory access is possible from
two independent data lines. A Distributed ROM option permits pre-loading the memory with data during FPGA configuration.
Second, it is possible to program each left-hand LUT as a 16-bit shift register. Used in this way, each LUT can delay serial
data anywhere from one to 16 clock cycles. The four left-hand LUTs of a single CLB can be combined to produce delays up
to 64 clock cycles. The SHIFTIN and SHIFTOUT lines cascade LUTs to form larger shift registers. It is also possible to
combine shift registers across more than one CLB. The resulting programmable delays can be used to balance the timing
of data pipelines.
Block RAM Overview
All Spartan-3 devices support block RAM, which is organized as configurable, synchronous 18Kbit blocks. Block RAM stores
relatively large amounts of data more efficiently than the distributed RAM feature described earlier. (The latter is better
suited for buffering small amounts of data anywhere along signal paths.) This section describes basic Block RAM functions.
For more information, refer to the chapter entitled “Using Block RAM” in UG331.
The aspect ratio—i.e., width vs. depth—of each block RAM is configurable. Furthermore, multiple blocks can be cascaded
to create still wider and/or deeper memories.
A choice among primitives determines whether the block RAM functions as dual- or single-port memory. A name of the form
RAMB16_S[wA]_S[wB] calls out the dual-port primitive, where the integers wA and wB specify the total data path width at
ports wA and wB, respectively. Thus, a RAMB16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A and an 18-bit-wide Port
B. A name of the form RAMB16_S[w] identifies the single-port primitive, where the integer w specifies the total data path
width of the lone port. A RAMB16_S18 is a single-port RAM with an 18-bit-wide port. Other memory functions—e.g., FIFOs,
data path width conversion, ROM, etc.—are readily available using the CORE Generator™ software, part of the Xilinx
development software.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 26
Arrangement of RAM Blocks on Die
The XC3S50 has one column of block RAM. The Spartan-3 devices ranging from the XC3S200 to XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 have four columns. The position of the columns on the die is shown
in Figure 1, page 3. For a given device, the total available RAM blocks are distributed equally among the columns. Ta bl e 1 2
shows the number of RAM blocks, the data storage capacity, and the number of columns for each device.
Block RAM and multipliers have interconnects between them that permit simultaneous operation; however, since the
multiplier shares inputs with the upper data bits of block RAM, the maximum data path width of the block RAM is 18 bits in
this case.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical data ports called A and B permit independent access to the
common RAM block, which has a maximum capacity of 18,432 bits—or 16,384 bits when no parity lines are used. Each port
has its own dedicated set of data, control and clock lines for synchronous read and write operations. There are four basic
data paths, as shown in Figure 13: (1) write to and read from Port A, (2) write to and read from Port B, (3) data transfer from
Port A to Port B, and (4) data transfer from Port B to Port A.
Block RAM Port Signal Definitions
Representations of the dual-port primitive RAMB16_S[wA]_S[wB] and the single-port primitive RAMB16_S[w] with their
associated signals are shown in Figure 14. These signals are defined in Ta bl e 1 3 .
Tabl e 1 2 : Number of RAM Blocks by Device
Device Total Number
of RAM Blocks
Total Addressable
Locations (Bits)
Number of
Columns
XC3S50 4 73,728 1
XC3S200 12 221,184 2
XC3S400 16 294,912 2
XC3S1000 24 442,368 2
XC3S1500 32 589,824 2
XC3S2000 40 737,280 2
XC3S4000 96 1,769,472 4
XC3S5000 104 1,916,928 4
X-Ref Target - Figure 13
Figure 13: Block RAM Data Paths
DS099-2_12_030703
Spartan-3
Dual Port
Block RAM
Read 3
Read
Write
Write
Read
Write
Write
Read
Port A
Port B
2
1
4
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 27
X-Ref Target - Figure 14
Figure 14: Block RAM Primitives
Tabl e 1 3 : Block RAM Port Signals
Signal
Description
Port A
Signal Name
Port B
Signal Name Direction Function
Address Bus ADDRA ADDRB Input The Address Bus selects a memory location for read or write
operations. The width (w) of the port’s associated data path determines
the number of available address lines (r).
Whenever a port is enabled (ENA or ENB = High), address transitions
must meet the data sheet setup and hold times with respect to the port
clock (CLKA or CLKB). This requirement must be met, even if the RAM
read output is of no interest.
Data Input Bus DIA DIB Input Data at the DI input bus is written to the addressed memory location
addressed on an enabled active CLK edge.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4,
9, 18, or 36 bits. This selection applies to both the DI and DO paths of
a given port. Each port is independent. For a port assigned a width (w),
the number of addressable locations is 16,384/(w-p) where "p" is the
number of parity bits. Each memory location has a width of "w"
(including parity bits). See the DIP signal description for more
information of parity.
Parity Data
Input(s)
DIPA DIPB Input Parity inputs represent additional bits included in the data input path to
support error detection. The number of parity bits "p" included in the DI
(same as for the DO bus) depends on a port’s total data path width (w).
See Ta b l e 1 4 .
DS099-2_13_112905
WEA
ENA
SSRA
CLKA
ADDRA[rA–1:0]
DIA[wA–1:0]
DIPA[3:0]
DOPA[pA–1:0]
DOA[wA–1:0]
RAMB16_SwA
_SwB
(a) Dual-Port (b) Single-Port
DOPB[pB–1:0]
DOB[wB–1:0]
WEB
ENB
SSRB
CLKB
ADDRB[rB–1:0]
DIB[wB–1:0]
DIPB[3:0]
WE
EN
SSR
CLK
ADDR[r–1:0]
DI[w–1:0]
DIP[p–1:0]
DOP[p–1:0]
DO[w–1:0]
RAMB16_Sw
Notes:
1. wA and wB are integers representing the total data path width (i.e., data bits plus parity bits) at ports A and B, respectively.
2. pA and pB are integers that indicate the number of data path lines serving as parity bits.
3. rA and rB are integers representing the address bus width at ports A and B, respectively.
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 28
Port Aspect Ratios
On a given port, it is possible to select a number of different possible widths (wp) for the DI/DO buses as shown in
Ta bl e 1 4 . These two buses always have the same width. This data bus width selection is independent for each port. If the
data bus width of Port A differs from that of Port B, the Block RAM automatically performs a bus-matching function. When
data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effectively combine
“narrow” words to form “wide” words. Similarly, when data are written into a port with a wide bus, then read from a port with
a narrow bus, the latter port will divide “wide” words to form “narrow” words. When the data bus width is eight bits or greater,
extra parity bits become available. The width of the total data path (w) is the sum of the DI/DO bus width and any parity bits
(p).
The width selection made for the DI/DO bus determines the number of address lines according to the relationship expressed
below:
r = 14 – [log(wp)/log(2)] Equation 1
In turn, the number of address lines delimits the total number (n) of addressable locations or depth according to the following
equation:
n = 2rEquation 2
Data Output Bus DOA DOB Output Basic data access occurs whenever WE is inactive. The DO outputs
mirror the data stored in the addressed memory location.
Data access with WE asserted is also possible if one of the following two
attributes is chosen: WRITE_FIRST and READ_FIRST. WRITE_FIRST
simultaneously presents the new input data on the DO output port and
writes the data to the address RAM location. READ_FIRST presents the
previously stored RAM data on the DO output port while writing new
data to RAM.
A third attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE.
It is possible to configure a port’s total data path width (w) to be 1, 2, 4,
9, 18, or 36 bits. This selection applies to both the DI and DO paths. See
the DI signal description.
Parity Data
Output(s)
DOPA DOPB Output Parity inputs represent additional bits included in the data input path to
support error detection. The number of parity bits "p" included in the DI
(same as for the DO bus) depends on a port’s total data path width (w).
See Ta b l e 1 4 .
Write Enable WEA WEB Input When asserted together with EN, this input enables the writing of data
to the RAM. In this case, the data access attributes WRITE_FIRST,
READ_FIRST or NO_CHANGE determines if and how data is updated
on the DO outputs. See the DO signal description.
When WE is inactive with EN asserted, read operations are still
possible. In this case, a transparent latch passes data from the
addressed memory location to the DO outputs.
Clock Enable ENA ENB Input When asserted, this input enables the CLK signal to synchronize Block
RAM functions as follows: the writing of data to the DI inputs (when WE
is also asserted), the updating of data at the DO outputs as well as the
setting/resetting of the DO output latches.
When de-asserted, the above functions are disabled.
Set/Reset SSRA SSRB Input When asserted, this pin forces the DO output latch to the value that the
SRVAL attribute is set to. A Set/Reset operation on one port has no
effect on the other ports functioning, nor does it disturb the memory’s
data contents. It is synchronized to the CLK signal.
Clock CLKA CLKB Input This input accepts the clock signal to which read and write operations
are synchronized. All associated port inputs are required to meet setup
times with respect to the clock signal’s active edge. The data output bus
responds after a clock-to-out delay referenced to the clock signal’s
active edge.
Tabl e 1 3 : Block RAM Port Signals (Cont’d)
Signal
Description
Port A
Signal Name
Port B
Signal Name Direction Function
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 29
The product of w and n yields the total block RAM capacity. Equation 1 and Equation 2 show that as the data bus width
increases, the number of address lines along with the number of addressable memory locations decreases. Using the
permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown
in Ta b l e 1 4 .
Block RAM Data Operations
Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each
of the two ports.
The waveforms for the write operation are shown in the top half of the Figure 15, Figure 16, and Figure 17. When the WE
and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the
ADDR lines.
There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always
occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines
passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of
Figure 15, Figure 16, and Figure 17 during which WE is Low.
Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different
attributes:
Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and
is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure 15 during which WE is High.
Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that
location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the
portion of Figure 16 during which WE is High.
Tabl e 1 4 : Port Aspect Ratios for Port A or B
DI/DO Bus Width
(w – p Bits)
DIP/DOP
Bus Width (p Bits)
Total Data Path
Width (w Bits)
ADDR Bus Width
(r Bits)
No. of Addressable
Locations (n)
Block RAM
Capacity (Bits)
1 0 1 14 16,384 16,384
2 0 2 13 8,192 16,384
4 0 4 12 4,096 16,384
8 1 9 11 2,048 18,432
16 2 18 10 1,024 18,432
32 4 36 9 512 18,432
X-Ref Target - Figure 15
Figure 15: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
CLK
WE
DI
ADDR
DO
EN
DISABLED READ
XXXX 1111 2222 XXXX
aa bb cc dd
0000 MEM(aa) 1111 2222 MEM(dd)
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
DS099-2_14_091410
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 30
Choosing a third attribute called NO_CHANGE puts the DO outputs in a latched state when asserting WE. Under this
condition, the DO outputs will retain the data driven just before WE was asserted. NO_CHANGE timing is shown in the
portion of Figure 17 during which WE is High.
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. This
section provides an introduction to multipliers. For further details, refer to the chapter entitled “Using Embedded Multipliers
in UG331.
The input buses to the multiplier accept data in twos-complement form (either 18-bit signed or 17-bit unsigned). One such
multiplier is matched to each block RAM on the die. The close physical proximity of the two ensures efficient data handling.
Cascading multipliers permits multiplicands more than three in number as well as wider than 18-bits. The multiplier is placed
in a design using one of two primitives: an asynchronous version called MULT18X18 and a version with a register called
MULT18X18S, as shown in Figure 18. The signals for these primitives are defined in Ta bl e 1 5 .
The CORE Generator system produces multipliers based on these primitives that can be configured to suit a wide range of
requirements.
X-Ref Target - Figure 16
Figure 16: Waveforms of Block RAM Data Operations with READ_FIRST Selected
X-Ref Target - Figure 17
Figure 17: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
CLK
WE
DI
ADDR
DO
EN
DISABLED READ
XXXX 1111 2222 XXXX
aa bb cc dd
0000 MEM(aa) old MEM(bb) old MEM(cc) MEM(dd)
READWRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
DS099-2_15_030403
CLK
WE
DI
ADDR
DO
EN
DISABLED READ
XXXX 1111 2222 XXXX
aa bb cc dd
0000 MEM(aa) MEM(dd)
READWRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
DS099-2_16_030403
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 31
Digital Clock Manager (DCM)
Spartan-3 devices provide flexible, complete control over clock frequency, phase shift and skew through the use of the DCM
feature. To accomplish this, the DCM employs a Delay-Locked Loop (DLL), a fully digital control system that uses feedback
to maintain clock signal characteristics with a high degree of precision despite normal variations in operating temperature
and voltage. This section provides a fundamental description of the DCM. For further information, refer to the chapter
entitled “Using Digital Clock Managers” in UG331.
Each member of the Spartan-3 family has four DCMs, except the smallest, the XC3S50, which has two DCMs. The DCMs
are located at the ends of the outermost Block RAM column(s). See Figure 1, page 3. The Digital Clock Manager is placed
in a design as the “DCM” primitive.
The DCM supports three major functions:
Clock-skew Elimination: Clock skew describes the extent to which clock signals may, under normal circumstances,
deviate from zero-phase alignment. It occurs when slight differences in path delays cause the clock signal to arrive at
different points on the die at different times. This clock skew can increase set-up and hold time requirements as well as
clock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. The
DCM eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that
is fed back. As a result, the two clock signals establish a zero-phase relationship. This effectively cancels out clock
distribution delays that may lie in the signal path leading from the clock output of the DCM to its feedback input.
Frequency Synthesis: Provided with an input clock signal, the DCM can generate a wide range of different output
clock frequencies. This is accomplished by either multiplying and/or dividing the frequency of the input clock signal by
any of several different factors.
X-Ref Target - Figure 18
Figure 18: Embedded Multiplier Primitives
Tabl e 1 5 : Embedded Multiplier Primitives Descriptions
Signal
Name Direction Function
A[17:0] Input Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the
enabled rising edge of CLK.
B[17:0] Input Apply the other 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before
the enabled rising edge of CLK.
P[35:0] Output The output on the P bus is a 36-bit product of the multiplicands A and B. In the case of the MULT18X18S
primitive, an enabled rising CLK edge updates the P bus.
CLK Input(1) CLK is only an input to the MULT18X18S primitive. The clock signal applied to this input, when enabled by
CE, updates the output register that drives the P bus.
CE Input(1) CE is only an input to the MULT18X18S primitive. Enable for the CLK signal. Asserting this input enables the
CLK signal to update the P bus.
RST Input(1) RST is only an input to the MULT18X18S primitive. Asserting this input resets the output register on an
enabled, rising CLK edge, forcing the P bus to all zeroes.
Notes:
1. The control signals CLK, CE and RST have the option of inverted polarity.
DS099-2_17_091510
(a) Asynchronous 18-bit Multiplier (b) 18-bit Multiplier with Register
A[17:0]
B[17:0]
P[35:0]
MULT18X18
A[17:0]
B[17:0]
CLK
CE
RST
P[35:0]
MULT18X18S
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 32
Phase Shifting: The DCM provides the ability to shift the phase of all its output clock signals with respect to its input
clock signal.
The DCM has four functional components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the
Phase Shifter (PS), and the Status Logic. Each component has its associated signals, as shown in Figure 19.
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to eliminate clock skew. The main signal path of the DLL consists of an
input stage, followed by a series of discrete delay elements or taps, which in turn leads to an output stage. This path together
with logic for phase detection and control forms a system complete with feedback as shown in Figure 20.
X-Ref Target - Figure 19
Figure 19: DCM Functional Blocks and Associated Signals
X-Ref Target - Figure 20
Figure 20: Simplified Functional Diagram of DLL
DS099-2_07_040103
PSINCDEC
PSEN
PSCLK
CLKIN
CLKFB
RST
STATUS [7:0]
LOCKED
8
CLKFX180
CLKFX
CLK0
PSDONE
Clock
Distribution
Delay
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Status
Logic
DFS
DLL
Phase
Shifter
Delay Taps
Output Stage
Input Stage
DCM
DS099-2_08_041103
CLKIN Delay
n
CLKFB
RST
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Output Section
Control
Delay
n-1
Phase
Detection
LOCKED
Delay
2
Delay
1
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 33
The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV as described in Ta b l e 1 6 . The clock outputs drive simultaneously; however, the
High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency
Modes, page 35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component,
page 41.
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The
CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either
internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via
a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This
phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the
appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with
the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in
Ta bl e 1 7 . Each attribute is described in detail in the sections that follow:
Tabl e 1 6 : DLL Signals
Signal Direction Description
Mode Support
Low
Frequency
High
Frequency
CLKIN Input Accepts original clock signal. Yes Yes
CLKFB Input Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK
attribute accordingly). Ye s Ye s
CLK0 Output Generates clock signal with same frequency and phase as CLKIN. Yes Yes
CLK90 Output Generates clock signal with same frequency as CLKIN, only phase-shifted 90°. Yes No
CLK180 Output Generates clock signal with same frequency as CLKIN, only phase-shifted 180°. Yes Yes
CLK270 Output Generates clock signal with same frequency as CLKIN, only phase-shifted 270°. Yes No
CLK2X Output Generates clock signal with same phase as CLKIN, only twice the frequency. Yes No
CLK2X180 Output Generates clock signal with twice the frequency of CLKIN, phase-shifted 180°
with respect to CLKIN. Ye s No
CLKDV Output Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower
frequency clock signal that is phase-aligned to CLKIN. Ye s Ye s
Tabl e 1 7 : DLL Attributes
Attribute Description Values
CLK_FEEDBACK Chooses either the CLK0 or CLK2X output to drive the CLKFB input NONE, 1X, 2X
DLL_FREQUENCY_MODE Chooses between High Frequency and Low Frequency modes LOW, HIGH
CLKIN_DIVIDE_BY_2 Halves the frequency of the CLKIN signal just as it enters the DCM TRUE, FALSE
CLKDV_DIVIDE Selects constant used to divide the CLKIN input frequency to
generate the CLKDV output frequency
1.5, 2, 2.5, 3, 3.5, 4, 4.5,
5, 5.5, 6.0, 6.5, 7.0, 7.5,
8, 9, 10, 11, 12, 13, 14,
15, and 16.
DUTY_CYCLE_CORRECTION Enables 50% duty cycle correction for the CLK0, CLK90, CLK180,
and CLK270 outputs TRUE, FALSE
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 34
DLL Clock Input Connections
An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the global
clock network or an Input Buffer (IBUF). Clock signals within the FPGA drive a global clock net using a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net connects directly to the CLKIN input. The internal and external
connections are shown in the [a] and [c] sections, respectively, of Figure 21. A differential clock (e.g., LVDS) can serve as an
input to CLKIN.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simultaneously drive the four BUFGMUX buffers on the same die edge
(top or bottom). All DCM clock outputs can simultaneously drive general routing resources, including interconnect leading to
OBUF buffers.
The feedback loop is essential for DLL operation and is established by driving the CLKFB input with either the CLK0 or the
CLK2X signal so that any undesirable clock distribution delay is included in the loop. It is possible to use either of these two
signals for synchronizing any of the seven DLL outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X, or CLK2X180.
The value assigned to the CLK_FEEDBACK attribute must agree with the physical feedback connection: a value of 1X for
the CLK0 case, 2X for the CLK2X case. If the DCM is used in an application that does not require the DLL—i.e., only the
DFS is used—then there is no feedback loop so CLK_FEEDBACK is set to NONE.
CLK2X feedback is only supported on all mask revision ‘E’ and later devices (see Mask and Fab Revisions, page 58), on
devices with the "GQ" fabrication code, and on all versions of the XC3S50 and XC3S1000.
There are two basic cases that determine how to connect the DLL clock outputs and feedback connections: on-chip
synchronization and off-chip synchronization, which are illustrated in Figure 21.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 35
In the on-chip synchronization case (the [a] and [b] sections of Figure 21), it is possible to connect any of the DLLs seven
output clock signals through general routing resources to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG)
or a BUFGMUX affords access to the global clock network. As shown in the [a] section of Figure 21, the feedback loop is
created by routing CLK0 (or CLK2X, in the [b] section) to a global clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case (the [c] and [d] sections of Figure 21), CLK0 (or CLK2X) plus any of the DLLs other
output clock signals exit the FPGA using output buffers (OBUF) to drive an external clock network plus registers on the
board. As shown in the [c] section of Figure 21, the feedback loop is formed by feeding CLK0 (or CLK2X, in the [d] section)
back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global clock net
is connected directly to the CLKFB input.
DLL Frequency Modes
The DLL supports two distinct operating modes, High Frequency and Low Frequency, with each specified over a different
clock frequency range. The DLL_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set
to LOW, the Low Frequency mode permits all seven DLL clock outputs to operate over a low-to-moderate frequency range.
When the attribute is set to HIGH, the High Frequency mode allows the CLK0, CLK180 and CLKDV outputs to operate at the
highest possible frequencies. The remaining DLL clock outputs are not available for use in High Frequency mode.
Accommodating High Input Frequencies
If the frequency of the CLKIN signal is high such that it exceeds the maximum permitted, divide it down to an acceptable
value using the CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to TRUE, the CLKIN frequency is divided by a
factor of two just as it enters the DCM.
X-Ref Target - Figure 21
Figure 21: Input Clock, Output Clock, and Feedback Connections for the DLL
DS099-2_09_082104
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLK0
CLK0
Clock
Net Delay
BUFGMUX
BUFGMUX
BUFG
FPGA
(a) On-Chip with CLK0 Feedback
CLKIN
DCM
CLKFB
CLK90
CLK180
CLK270
CLKDV
CLK2X
CLK2X180
CLK0
CLK0
Clock
Net Delay
IBUFG
IBUFG
FPGA
(c) Off-Chip with CLK0 Feedback
CLKIN
DCM
CLKFB
OBUF
OBUF
CLK2X
CLK2X
IBUFG
IBUFG
FPGA
(d) Off-Chip with CLK2X Feedback
CLKIN
DCM
CLKFB
OBUF
OBUF
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X180
CLK2X
CLK2X
Clock
Net Delay
Clock
Net Delay
BUFGMUX
BUFGMUX
BUFG
FPGA
(b) On-Chip with CLK2X Feedback
CLKIN
DCM
CLKFB
CLK0
CLK90
CLK180
CLK270
CLKDV
CLK2X180
Notes:
1. In the Low Frequency mode, all seven DLL outputs are available. In the High Frequency mode, only the CLK0, CLK180, and
CLKDV outputs are available.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 36
Coarse Phase Shift Outputs of the DLL Component
In addition to CLK0 for zero-phase alignment to the CLKIN signal, the DLL also provides the CLK90, CLK180 and CLK270
outputs for 90°, 180° and 270° phase-shifted signals, respectively. These signals are described in Table 16, page 33. Their
relative timing in the Low Frequency Mode is shown in Figure 22, page 37. The CLK90, CLK180 and CLK270 outputs are
not available when operating in the High Frequency mode. (See the description of the DLL_FREQUENCY_MODE attribute
in Table 17, page 33.) For control in finer increments than 90°, see Phase Shifter (PS), page 39.
Basic Frequency Synthesis Outputs of the DLL Component
The DLL component provides basic options for frequency multiplication and division in addition to the more flexible synthesis
capability of the DFS component, described in a later section. These operations result in output clock signals with
frequencies that are either a fraction (for division) or a multiple (for multiplication) of the incoming clock frequency. The
CLK2X output produces an in-phase signal that is twice the frequency of CLKIN. The CLK2X180 output also doubles the
frequency, but is 180° out-of-phase with respect to CLKIN. The CLKDIV output generates a clock frequency that is a
predetermined fraction of the CLKIN frequency. The CLKDV_DIVIDE attribute determines the factor used to divide the
CLKIN frequency. The attribute can be set to various values as described in Ta b le 1 7 . The basic frequency synthesis outputs
are described in Ta b l e 1 6 . Their relative timing in the Low Frequency Mode is shown in Figure 22.
The CLK2X and CLK2X180 outputs are not available when operating in the High Frequency mode. See the description of
the DLL_FREQUENCY_MODE attribute in Tab l e 1 8 .
Duty Cycle Correction of DLL Clock Outputs
The CLK2X(1), CLK2X180, and CLKDV(2) output signals ordinarily exhibit a 50% duty cycle—even if the incoming CLKIN
signal has a different duty cycle. A 50% duty cycle means that the High and Low times of each clock cycle are equal. The
DUTY_CYCLE_CORRECTION attribute determines whether or not duty cycle correction is applied to the CLK0, CLK90,
CLK180 and CLK270 outputs. If DUTY_CYCLE_CORRECTION is set to TRUE, then the duty cycle of these four outputs is
corrected to 50%. If DUTY_CYCLE_CORRECTION is set to FALSE, then these outputs exhibit the same duty cycle as the
CLKIN signal. Figure 22 compares the characteristics of the DLLs output signals to those of the CLKIN signal.
1. The CLK2X output generates a 25% duty cycle clock at the same frequency as the CLKIN signal until the DLL has achieved lock.
2. The duty cycle of the CLKDV outputs may differ somewhat from 50% (i.e., the signal will be High for less than 50% of the period) when the
CLKDV_DIVIDE attribute is set to a non-integer value and the DLL is operating in the High Frequency mode.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 37
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input
and a ratio of two user-determined integers. Because of the wide range of possible output frequencies such a ratio permits,
the DFS feature provides still further flexibility than the DLLs basic synthesis options as described in the preceding section.
The DFS component’s two dedicated outputs, CLKFX and CLKFX180, are defined in Ta bl e 1 9 .
The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit a 50%
duty cycle. This is true even when the CLKIN signal does not. These DFS clock outputs are driven at the same time as the
DLLs seven clock outputs.
The numerator of the ratio is the integer value assigned to the attribute CLKFX_MULTIPLY and the denominator is the
integer value assigned to the attribute CLKFX_DIVIDE. These attributes are described in Ta bl e 1 8 .
X-Ref Target - Figure 22
Figure 22: Characteristics of the DLL Clock Outputs
Output Signal - Duty Cycle is Always Corrected
Output Signal - Attribute Corrects Duty Cycle
Phase:
Input Signal (40% Duty Cycle)
0o90o180o270o0o90o180o270o0o
DUTY_CYCLE_CORRECTION = FALSE
DUTY_CYCLE_CORRECTION = TRUE
DS099-2_10_051907
CLK2X
CLK2X180
CLKIN
CLKDV(1)
CLK0
CLK90
CLK180
CLK270
CLK0
CLK90
CLK180
CLK270
t
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 38
The output frequency (fCLKFX) can be expressed as a function of the incoming clock frequency (fCLKIN) as follows:
fCLKFX = fCLKIN(CLKFX_MULTIPLY/CLKFX_DIVIDE) Equation 3
Regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met:
The two values fall within their corresponding ranges, as specified in Ta bl e 1 8 .
•The f
CLKFX frequency calculated from the above expression accords with the DCM’s operating frequency
specifications.
For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, then the frequency of the output clock signal would be 5/3
that of the input clock signal.
DFS Frequency Modes
The DFS supports two operating modes, High Frequency and Low Frequency, with each specified over a different clock
frequency range. The DFS_FREQUENCY_MODE attribute chooses between the two modes. When the attribute is set to
LOW, the Low Frequency mode permits the two DFS outputs to operate over a low-to-moderate frequency range. When the
attribute is set to HIGH, the High Frequency mode allows both these outputs to operate at the highest possible frequencies.
DFS With or Without the DLL
The DFS component can be used with or without the DLL component:
Without the DLL, the DFS component multiplies or divides the CLKIN signal frequency according to the respective
CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating a clock with the new target frequency on the CLKFX and
CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS
component. This case does not employ feedback loop; therefore, it cannot correct for clock distribution delay.
With the DLL, the DFS operates as described in the preceding case, only with the additional benefit of eliminating the clock
distribution delay. In this case, a feedback loop from the CLK0 output to the CLKFB input must be present.
The DLL and DFS components work together to achieve this phase correction as follows: Given values for the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL selects the delay element for which the output clock edge
coincides with the input clock edge whenever mathematically possible. For example, when CLKFX_MULTIPLY = 5 and
CLKFX_DIVIDE = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to
five output periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values achieve faster lock times. With no factors common to the two
attributes, alignment will occur once with every number of cycles equal to the CLKFX_DIVIDE value. Therefore, it is
recommended that the user reduce these values by factoring wherever possible. For example, given CLKFX_MULTIPLY = 9
and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. While both
value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the DLL to lock more
quickly.
Tabl e 1 8 : DFS Attributes
Attribute Description Values
DFS_FREQUENCY_MODE Chooses between High Frequency and Low Frequency modes Low, High
CLKFX_MULTIPLY Frequency multiplier constant Integer from 2 to 32
CLKFX_DIVIDE Frequency divisor constant Integer from 1 to 32
Tabl e 1 9 : DFS Signals
Signal Direction Description
CLKFX Output Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/CLKFX_DIVIDE) to
generate a clock signal with a new target frequency.
CLKFX180 Output Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 39
DFS Clock Output Connections
There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illustrated
in sections [a] and [c], respectively, of Figure 21. This is similar to what has already been described for the DLL component.
See DLL Clock Output and Feedback Connections, page 34.
In the on-chip case, it is possible to connect either of the DFS’s two output clock signals through general routing resources
to the FPGA’s internal registers. Either a Global Clock Buffer (BUFG) or a BUFGMUX affords access to the global clock
network. The optional feedback loop is formed in this way, routing CLK0 to a global clock net, which in turn drives the CLKFB
input.
In the off-chip case, the DFS’s two output clock signals, plus CLK0 for an optional feedback loop, can exit the FPGA using
output buffers (OBUF) to drive a clock network plus registers on the board. The feedback loop is formed by feeding the CLK0
signal back into the FPGA using an IBUFG, which directly accesses the global clock network, or an IBUF. Then, the global
clock net is connected directly to the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase of a DCM clock output signal relative to the CLKIN signal: First,
there are nine clock outputs that employ the DLL to achieve a desired phase relationship: CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, CLKDV CLKFX, and CLKFX180. These outputs afford “coarse” phase control.
The second approach uses the PS component described in this section to provide a still finer degree of control. The PS
component is only available when the DLL is operating in its low-frequency mode. The PS component phase shifts the DCM
output clocks by introducing a "fine phase shift" (TPS) between the CLKFB and CLKIN signals inside the DLL component.
The user can control this fine phase shift down to a resolution of 1/256 of a CLKIN cycle or one tap delay (DCM_TAP),
whichever is greater. When in use, the PS component shifts the phase of all nine DCM clock output signals together. If the
PS component is used together with a DCM clock output such as the CLK90, CLK180, CLK270, CLK2X180 and CLKFX180,
then the fine phase shift of the former gets added to the coarse phase shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS component for use in addition to selecting between two operating
modes. As described in Ta bl e 2 0 , this attribute has three possible values: NONE, FIXED and VARIABLE. When
CLKOUT_PHASE_SHIFT is set to NONE, the PS component is disabled and its inputs, PSEN, PSCLK, and PSINCDEC,
must be tied to GND. The set of waveforms in section [a] of Figure 22 shows the disabled case, where the DLL maintains a
zero-phase alignment of signals CLKFB and CLKIN upon which the PS component has no effect. The PS component is
enabled by setting the attribute to either the FIXED or VARIABLE values, which select the Fixed Phase mode and the
Variable Phase mode, respectively. These two modes are described in the sections that follow
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to CLKIN by setting and/or adjusting the value of the PHASE_SHIFT
attribute. This value must be an integer ranging from –255 to +255. The PS component uses this value to calculate the
desired fine phase shift (TPS) as a fraction of the CLKIN period (TCLKIN). Given values for PHASE-SHIFT and TCLKIN, it is
possible to calculate TPS as follows:
TPS = TCLKIN(PHASE_SHIFT/256) Equation 4
Both the Fixed Phase and Variable Phase operating modes employ this calculation. If the PHASE_SHIFT value is zero, then
CLKFB and CLKIN will be in phase, the same as when the PS component is disabled. When the PHASE_SHIFT value is
positive, the CLKFB signal will be shifted later in time with respect to CLKIN. If the attribute value is negative, the CLKFB
signal will be shifted earlier in time with respect to CLKIN.
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of the TCLKIN, as determined by Equation 4 and its user-selected
PHASE_SHIFT value P. The set of waveforms insection [b] of Figure 22 illustrates the relationship between CLKFB and
CLKIN in the Fixed Phase mode. In the Fixed Phase mode, the PSEN, PSCLK and PSINCDEC inputs are not used and
must be tied to GND. Fixed phase shift requires ISE software version 10.1.03 or later.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 40
The Variable Phase Mode
The “Variable Phase” mode dynamically adjusts the fine phase shift over time using three inputs to the PS component,
namely PSEN, PSCLK and PSINCDEC, as defined in Ta b le 2 1 .
After device configuration, the PS component initially determines TPS by evaluating Equation (4) for the value assigned to
the PHASE_SHIFT attribute. Then to dynamically adjust that phase shift, use the three PS inputs to increase or decrease
the fine phase shift.
PSINCDEC is synchronized to the PSCLK clock signal, which is enabled by asserting PSEN. It is possible to drive the
PSCLK input with the CLKIN signal or any other clock signal. A request for phase adjustment is entered as follows: For each
PSCLK cycle that PSINCDEC is High, the PS component adds 1/256 of a CLKIN cycle to TPS. Similarly, for each enabled
PSCLK cycle that PSINCDEC is Low, the PS component subtracts 1/256 of a CLKIN cycle from TPS. The phase adjustment
may require as many as 100 CLKIN cycles plus three PSCLK cycles to take effect, at which point the output PSDONE goes
High for one PSCLK cycle. This pulse indicates that the PS component has finished the present adjustment and is now
ready for the next request. Asserting the Reset (RST) input, returns TPS to its original shift time, as determined by the
PHASE_SHIFT attribute value. The set of waveforms in section [c] of Figure 23, page 41 illustrates the relationship between
CLKFB and CLKIN in the Variable Phase mode.
Tabl e 2 0 : PS Attributes
Attribute Description Values
CLKOUT_PHASE_SHIFT Disables PS component or chooses between Fixed Phase and
Variable Phase modes. NONE, FIXED, VARIABLE
PHASE_SHIFT Determines size and direction of initial fine phase shift. Integers from –255 to +255(1)
Notes:
1. The practical range of values will be less when TCLKIN > FINE_SHIFT_RANGE in the Fixed Phase mode, also when TCLKIN >
(FINE_SHIFT_RANGE)/2 in the Variable Phase mode. the FINE_SHIFT_RANGE represents the sum total delay of all taps.
Tabl e 2 1 : Signals for Variable Phase Mode
Signal Direction Description
PSEN(1) Input Enables PSCLK for variable phase adjustment.
PSCLK(1) Input Clock to synchronize phase shift adjustment.
PSINCDEC(1) Input Chooses between increment and decrement for phase adjustment. It is synchronized to the PSCLK
signal.
PSDONE Output Goes High to indicate that present phase adjustment is complete and PS component is ready for next
phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1. It is possible to program this input for either a true or inverted polarity
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 41
The Status Logic Component
The Status Logic component not only reports on the state of the DCM but also provides a means of resetting the DCM to an
initial known state. The signals associated with the Status Logic component are described in Ta b l e 2 2 .
As a rule, the Reset (RST) input is asserted only upon configuring the device or changing the CLKIN frequency. A DCM reset
does not affect attribute values (e.g., CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST must be tied to GND.
The eight bits of the STATUS bus are defined in Tab l e 2 3 .
X-Ref Target - Figure 23
Figure 23: Phase Shifter Waveforms
DS099-2_11_031303
CLKIN
CLKFB
* TCLKIN
P
256
b. CLKOUT_PHASE_SHIFT = FIXED
* TCLKIN
P
256
Shift Range over all P Values: –255 +255
Shift Range over all P Values: 0
0
–255 +255
Shift Range over all N Values: 0–255 +255
CLKIN
CLKFB before
Decrement
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKFB after
Decrement
* TCLKIN
N
256
CLKIN
CLKFB
a. CLKOUT_PHASE_SHIFT = NONE
Notes:
1. P represents the integer value ranging from –255 to +255 to which the PHASE_SHIFT attribute is assigned.
2. N is an integer value ranging from –255 to +255 that represents the net phase shift effect from a series of increment
and/or decrement operations.
N = {Total number of increments} – {Total number of decrements}
A positive value for N indicates a net increment; a negative value indicates a net decrement.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 42
Stabilizing DCM Clocks Before User Mode
It is possible to delay the completion of device configuration until after the DLL has achieved a lock condition using the
STARTUP_WAIT attribute described in Ta b l e 2 4 . This option ensures that the FPGA does not enter user mode—i.e., begin
functional operation—until all system clocks generated by the DCM are stable. In order to achieve the delay, it is necessary
to set the attribute to TRUE as well as set the BitGen option LCK_cycle to one of the six cycles making up the Startup phase
of configuration. The selected cycle defines the point at which configuration will halt until the LOCKED output goes High.
Global Clock Network
Spartan-3 devices have eight Global Clock inputs called GCLK0 - GCLK7. These inputs provide access to a
low-capacitance, low-skew network that is well-suited to carrying high-frequency signals. The Spartan-3 FPGAs clock
network is shown in Figure 23. GCLK0 through GCLK3 are located in the center of the bottom edge. GCLK4 through GCLK7
are located in the center of the top edge.
Eight Global Clock Multiplexers (also called BUFGMUX elements) are provided that accept signals from Global Clock inputs
and route them to the internal clock network as well as DCMs. Four BUFGMUX elements are located in the center of the
bottom edge, just above the GCLK0 - GCLK3 inputs. The remaining four BUFGMUX elements are located in the center of
the top edge, just below the GCLK4 - GCLK7 inputs.
Pairs of BUFGMUX elements share global inputs, as shown in Figure 24. For example, the GCLK4 and GCLK5 inputs both
potentially connect to BUFGMUX4 and BUFGMUX5 located in the upper right center. A differential clock input uses a pair of
GCLK inputs to connect to a single BUFGMUX element.
Tabl e 2 2 : Status Logic Signals
Signal Direction Description
RST Input A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of zero.
Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0] Output The bit values on the STATUS bus provide information regarding the state of DLL and PS operation
LOCKED Output Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are
out-of-phase when Low.
Tabl e 2 3 : DCM STATUS Bus
Bit Name Description
0 Phase Shift Overflow
A value of 1 indicates a phase shift overflow when one of two conditions occurs:
Incrementing (or decrementing) TPS beyond 255/256 of a CLKIN cycle.
The DLL is producing its maximum possible phase shift (i.e., all delay taps are active).(1)
1CLKIN Input Stopped
Toggling
A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling. This
bit functions only when the CLKFB input is connected.(2)
2
CLKFX/CLKFX180
Output Stopped
Toggling
A value of 1 indicates that the CLKFX or CLKFX180 output signals are not toggling. A value of 0
indicates toggling. This bit functions only when using the Digital Frequency Synthesizer (DFS).
3:7 Reserved
Notes:
1. The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE.
2. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit will not go High when the CLKIN signal stops.
Tabl e 2 4 : Status Attributes
Attribute Description Values
STARTUP_WAIT Delays transition from configuration to user mode until lock condition is achieved. TRUE, FALSE
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 43
Each BUFGMUX element, shown in Figure 24, is a 2-to-1 multiplexer that can receive signals from any of the four following
sources:
One of the four Global Clock inputs on the same side of the die—top or bottom—as the BUFGMUX element in use.
Any of four nearby horizontal Double lines.
Any of four outputs from the DCM in the right-hand quadrant that is on the same side of the die as the BUFGMUX
element in use.
Any of four outputs from the DCM in the left-hand quadrant that is on the same side of the die as the BUFGMUX
element in use.
The multiplexer select line, S, chooses which of the two inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Ta b l e 2 5 . The switching from one clock to the other is glitchless, and done in such a way that the output High
and Low times are never shorter than the shortest High or Low time of either input clock.
The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a
short setup time prior to the rising edge of the presently selected clock (I0 or I1). Violating this setup time requirement can
result in an undefined runt pulse output.
The BUFG clock buffer primitive drives a single clock signal onto the clock network and is essentially the same element as
a BUFGMUX, just without the clock select mechanism. Similarly, the BUFGCE primitive creates an enabled clock buffer
using the BUFGMUX select mechanism.
Each BUFGMUX buffers incoming clock signals to two possible destinations:
The vertical spine belonging to the same side of the die—top or bottom—as the BUFGMUX element in use. The two
spines—top and bottom—each comprise four vertical clock lines, each running from one of the BUFGMUX elements
on the same side towards the center of the die. At the center of the die, clock signals reach the eight-line horizontal
spine, which spans the width of the die. In turn, the horizontal spine branches out into a subsidiary clock interconnect
that accesses the CLBs.
The clock input of either DCM on the same side of the die—top or bottom—as the BUFGMUX element in use.
Use either a BUFGMUX element or a BUFG (Global Clock Buffer) element to place a Global input in the design. For the
purpose of minimizing the dynamic power dissipation of the clock network, the Xilinx development software automatically
disables all clock line segments that a design does not use.
A global clock line ideally drives clock inputs on the various clocked elements within the FPGA, such as CLB or IOB flip-flops
or block RAMs. A global clock line also optionally drives combinatorial inputs. However, doing so provides additional loading
on the clock line that might also affect clock jitter. Ideally, drive combinatorial inputs using the signal that also drives the input
to the BUFGMUX or BUFG element.
For more details, refer to the chapter entitled “Using Global Clock Resources” in UG331.
Tabl e 2 5 : BUFGMUX Select Mechanism
S Input O Output
0 I0 Input
1 I1 Input
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 44
X-Ref Target - Figure 24
Figure 24: Spartan-3 FPGAs Clock Network (Top View)
4
4
4
4
4
4
4
8
8
4
4
88
Horizontal Spine
Top SpineBottom Spine
4
DCM DCM
DCM DCM
Array Dependent
Array Dependent
DS099-2_18_091510
4 BUFGMUX
4 BUFGMUX
GCLK1
GCLK0
GCLK3
GCLK2
GCLK5
GCLK4
GCLK7
GCLK6
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 45
Interconnect
Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds
of interconnect: Long lines, Hex lines, Double lines, and Direct lines.
Long lines connect to one out of every six CLBs (see section [a] of Figure 25). Because of their low capacitance, these lines
are well-suited for carrying high-frequency signals with minimal loading effects (e.g. skew). If all eight Global Clock Inputs
are already committed and there remain additional clock signals to be assigned, Long lines serve as a good alternative.
Hex lines connect one out of every three CLBs (see section [b] of Figure 25). These lines fall between Long lines and Double
lines in terms of capability: Hex lines approach the high-frequency characteristics of Long lines at the same time, offering
greater connectivity.
Double lines connect to every other CLB (see section [c] of Figure 25). Compared to the types of lines already discussed,
Double lines provide a higher degree of flexibility when making connections.
Direct lines afford any CLB direct access to neighboring CLBs (see section [d] of Figure 25). These lines are most often used
to conduct a signal from a "source" CLB to a Double, Hex, or Long line and then from the longer interconnect back to a Direct
line accessing a "destination" CLB.
For more details, refer to the “Using Interconnect” chapter in UG331.
X-Ref Target - Figure 25
(a) Long Lines
(b) Hex Lines
(d) Direct Lines
Figure 25: Types of Interconnect
CLB CLB
CLB CLB
CLB CLB
66 666
CLB CLB
CLB CLB
DS099-2_19_040103
CLB CLB CLB CLB CLB CLBCLB
8
DS099-2_20_040103
CLB
2
CLB CLB
DS099-2_21_040103
CLBCLB CLB
CLBCLB CLB
CLBCLB CLB
DS099-2_22_040103
(c) Double Lines
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 46
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory.
Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while
others, indicated by the term "Dual-Purpose", can be re-used as general-purpose User I/Os once configuration is complete.
Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0,
M1, and M2 are Dedicated pins. The mode pin settings are shown in Tab l e 2 6 .
The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the
pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during
configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins
(TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the
HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM,
depending on the package style.
Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an
externally generated clock.
A persist option is available which can be used to force the configuration pins to retain their configuration function even after
device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK,
PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan
related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.
Ta bl e 2 7 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits.
See DS123: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.
The maximum bitstream length that Spartan-3 FPGAs support in serial daisy-chains is 4,294,967,264 bits (4 Gbits), roughly
equivalent to a daisy-chain with 323 XC3S5000 FPGAs. This is a limit only for serial daisy-chains where configuration data
is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains.
Tabl e 2 6 : Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode(1) M0 M1 M2 Synchronizing Clock Data Width Serial DOUT(2)
Master Serial 0 0 0 CCLK Output 1 Yes
Slave Serial 1 1 1 CCLK Input 1 Yes
Master Parallel 1 1 0 CCLK Output 8 No
Slave Parallel 0 1 1 CCLK Input 8 No
JTAG 101 TCK Input 1 No
Notes:
1. The voltage levels on the M0, M1, and M2 pins select the configuration mode.
2. The daisy chain is possible only in the Serial modes when DOUT is used.
Tabl e 2 7 : Spartan-3 FPGA Configuration Data
Device File Sizes Xilinx Platform Flash PROM
Serial Configuration Parallel Configuration
XC3S50 439,264 XCF01S XCF08P
XC3S200 1,047,616 XCF01S XCF08P
XC3S400 1,699,136 XCF02S XCF08P
XC3S1000 3,223,488 XCF04S XCF08P
XC3S1500 5,214,784 XCF08P XCF08P
XC3S2000 7,673,024 XCF08P XCF08P
XC3S4000 11,316,864 XCF16P XCF16P
XC3S5000 13,271,936 XCF16P XCF16P
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 47
The Standard Configuration Interface
Configuration signals belong to one of two different categories: Dedicated or Dual-Purpose. Which category determines
which of the FPGA’s power rails supplies the signal’s driver and, thus, helps describe the electrical characteristics at the pin.
The Dedicated configuration pins include PROG_B, HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE, and M0-M2. These
pins are powered by the VCCAUX supply.
The Dual-Purpose configuration pins comprise INIT_B, DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of these pins,
according to its bank placement, uses the VCCO lines for either Bank 4 (VCCO_4 on most packages, VCCO_BOTTOM on
TQ144 and CP132 packages) or Bank 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4
power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4.
Both the Dedicated signals described above and the Dual-Purpose signals constitute the configuration interface. The
Dedicated pins, powered by the 2.5V VCCAUX supply, always use the LVCMOS25 I/O standard. The Dual-Purpose signals,
however, are powered by the VCCO_4 supply and also by the VCCO_5 supply in the Parallel configuration modes. The
simplest configuration interface uses 2.5V for VCCO_4 and VCCO_5, if required. However, VCCO_4 and, if needed,
VCCO_5 can be voltages other than 2.5V but then the configuration interface will have two voltage levels: 2.5V for VCCAUX
and a separate VCCO supply. The Dual-Purpose signals default to the LVCMOS input and output levels for the associated
VCCO voltage supply.
3.3V-Tolerant Configuration Interface
A 3.3V-tolerant configuration interface simply requires adding a few external resistors as described in detail in XAPP453:
The 3.3V Configuration of Spartan-3 FPGAs.
The 3.3V-tolerance is implemented as follows (a similar approach can be used for other supply voltage levels):
Apply 3.3V to VCCO_4 and, in some configuration modes, to VCCO_5 to power the Dual-Purpose configuration pins. This
scales the output voltages and input thresholds associated with these pins so that they become 3.3V-compatible.
Apply 2.5V to VCCAUX to power the Dedicated configuration pins. For 3.3V-tolerance, the Dedicated inputs require series
resistors to limit the incoming current to 10 mA or less. The Dedicated outputs have reduced noise margin when the FPGA
drives a High logic level into another device’s 3.3V receiver. Choose a power regulator or supply that can tolerate reverse
current on the VCCAUX lines.
Configuration Modes
Spartan-3 FPGAs support the following five configuration modes:
Slave Serial mode
Master Serial mode
Slave Parallel (SelectMAP) mode
Master Parallel (SelectMAP) mode
Boundary-Scan (JTAG) mode (IEEE 1532/IEEE 1149.1)
Slave Serial Mode
In Slave Serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other serial source of
configuration data. The FPGA on the far right of Figure 26 is set for the Slave Serial mode. The CCLK pin on the FPGA is
an input in this mode. The serial bitstream must be set up at the DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured,
the data for the next device is routed internally to the DOUT pin. The data on the DOUT pin changes on the falling edge of
CCLK.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 48
Slave Serial mode is selected by applying <111> to the mode pins (M0, M1, and M2). A pull-up on the mode pins makes
slave serial the default mode if the pins are left unconnected.
Master Serial Mode
In Master Serial mode, the FPGA drives CCLK pin, which behaves as a bidirectional I/O pin. The FPGA in the center of
Figure 26 is set for Master Serial mode and connects to the serial configuration PROM and to the CCLK inputs of any slave
FPGAs in a configuration daisy-chain. The master FPGA drives the configuration clock on the CCLK pin to the Xilinx Serial
PROM, which, in response, provides bit-serial data to the FPGA’s DIN input. The FPGA accepts this data on each rising
CCLK edge. After the master FPGA finishes configuring, it passes data on its DOUT pin to the next FPGA device in a
daisy-chain. The DOUT data appears after the falling CCLK clock edge.
The Master Serial mode interface is identical to Slave Serial except that an internal oscillator generates the configuration
clock (CCLK). A wide range of frequencies can be selected for CCLK, which always starts at a default frequency of 6 MHz.
Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration.
Slave Parallel Mode (SelectMAP)
The Parallel or SelectMAP modes support the fastest configuration. Byte-wide data is written into the FPGA with a BUSY
flag controlling the flow of data. An external source provides 8-bit-wide data, CCLK, an active-Low Chip Select (CS_B) signal
and an active-Low Write signal (RDWR_B). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes
Low. Data can also be read using the Slave Parallel mode. If RDWR_B is asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, it is possible to use any of the Multipurpose pins (DIN/D0-D7, DOUT/BUSY, INIT_B, CS_B, and
RDWR_B) as User I/Os. To do this, simply set the BitGen option Persist to No and assign the desired signals to multipurpose
configuration pins using the Xilinx development software. Alternatively, it is possible to continue using the configuration port
X-Ref Target - Figure 26
Figure 26: Connection Diagram for Master and Slave Serial Configuration
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last
FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE
pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain.
Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up
resistor shown in grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE
synchronously with a long chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g. down
to 330Ω) in order to ensure a rise time within one clock cycle.
2. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.
DOUTDIN
CCLK
DONE
INIT_B
Spartan-3
FPGA
Master
PROG_B
DIN
CCLK
DONE
INIT_B
Spartan-3
FPGA
Slave
PROG_B
DS099_23_112905
D0
CLK
CE
OE/RESET
CF
Platform
Flash PROM
XCF0xS
or
XCFxxP
VCCINT
1.2V
VCCAUX
VCCO Bank 4
2.5V
2.5V
4.7KΩ
All
2.5V
VCCAUX VCCINT
VCCO Bank 4
1.2V
1.8V: XCFxxP
VCCINT VCCJ
VCCO
2.5V
2.5V
M0
M1
M2
M0
M1
M2
GND
GND
GND
3.3V: XCF0xS
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 49
(e.g. all configuration pins taken together) when operating in the User mode. This is accomplished by setting the Persist
option to Ye s .
Multiple FPGAs can be configured using the Slave Parallel mode and can be made to start-up simultaneously. Figure 27
shows the device connections. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B, and
BUSY pins of all the devices in parallel. The individual devices are loaded separately by deasserting the CS_B pin of each
device in turn and writing the appropriate data.
X-Ref Target - Figure 27
Figure 27: Connection Diagram for Slave Parallel Configuration
PROG_B
INIT_B
DONE
Spartan-3
Slave
INIT_B
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROG_B
DONE
CS_B
Spartan-3
Slave
INIT_B
GND
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
D[0:7]
CCLK
RDWR_B
BUSY
PROG_B
DONE
CS_B
DS099_24_041103
2.5V
M1
M2
M0
2.5V
M1
M2
M0
2.5V
VCCAUX
VCCO Banks 4 & 5
VCCINT
1.2V
4.7KΩ4.7KΩ
2.5V
VCCAUX
VCCO Banks 4 & 5
VCCINT
1.2V
2.5V
GND
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA to be
configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE pin to drive High; thus,
no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain. Second, DriveDone can be set to
"No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in grey. In most cases, a value
between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously with a long chain of FPGAs, cumulative
capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise time within one clock cycle.
2. If the FPGAs use different configuration data files, configure them in sequence by first asserting the CS_B of one FPGA then
asserting the CS_B of the other FPGA.
3. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 50
Master Parallel Mode
In this mode, the FPGA configures from byte-wide data, and the FPGA supplies the CCLK configuration clock. In Master
configuration modes, CCLK behaves as a bidirectional I/O pin. Timing is similar to the Slave Parallel mode except that CCLK
is supplied by the FPGA. The device connections are shown in Figure 28.
Boundary-Scan (JTAG) Mode
In Boundary-Scan mode, dedicated pins are used for configuring the FPGA. The configuration is done entirely through the
IEEE 1149.1 Test Access Port (TAP). FPGA configuration using the Boundary-Scan mode is compatible with the IEEE Std
1149.1-1993 standard and IEEE Std 1532 for In-System Configurable (ISC) devices.
Configuration through the boundary-scan port is always available, regardless of the selected configuration mode. In some
cases, however, the mode pin setting may affect proper programming of the device due to various interactions. For example,
if the mode pins are set to Master Serial or Master Parallel mode, and the associated PROM is already programmed with a
valid configuration image, then there is potential for configuration interference between the JTAG and PROM data. Selecting
the Boundary-Scan mode disables the other modes and is the most reliable mode when programming via JTAG.
Configuration Sequence
The configuration of Spartan-3 devices is a three-stage process that occurs after Power-On Reset or the assertion of
PROG_B. POR occurs after the VCCINT
, VCCAUX, and VCCO Bank 4 supplies have reached their respective maximum input
threshold levels (see Table 29, page 59). After POR, the three-stage process begins.
First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is
activated by a start-up process. A flow diagram for the configuration sequence of the Serial and Parallel modes is shown in
Figure 29. The flow diagram for the Boundary-Scan configuration sequence appears in Figure 30.
X-Ref Target - Figure 28
Figure 28: Connection Diagram for Master Parallel Configuration
Spartan-3
Master
D[0:7]
CCLK
PROG_B
DONE
INIT_B
DATA[0:7]
CCLK
RDWR_B
CS_B
CF
CE
OE/RESET
Platform Flash
PROM
DS099_25_112905
2.5V
VCCAUX
VCCO Banks 4 & 5
VCCINT
1.2V
GND
GND
1.8V
VCCINT VCCJ
VCCO
2.5V
XCFxxP
2.5V
All
4.7KΩ
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for
the last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This
enables the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the
remaining FPGAs in the chain. Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines
are open-drain and require the pull-up resistor shown in grey. In most cases, a value between 3.3KΩ to
4.7KΩ is sufficient. However, when using DONE synchronously with a long chain of FPGAs, cumulative
capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise time within
one clock cycle.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 51
X-Ref Target - Figure 29
Figure 29: Configuration Flow Diagram for the Serial and Parallel Modes
Sample mode pins
No
No
No
Yes
Yes
Yes
Clear configuration
memory
Power-On Set PROG_B Low
after Power-On
Yes
No
CRC
correct?
Yes
No Reconfigure?
Load configuration
data frames
INIT_B goes Low.
Abort Start-Up
Start-Up
sequence
User mode
INIT_ B = High?
PROG_B = Low
DS099_26_041103
VCCINT >1V
and VCCAUX > 2V
and VCCO Bank 4 > 1V
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 52
X-Ref Target - Figure 30
Figure 30: Boundary-Scan Configuration Flow Diagram
Sample
mode pins
(JTAG port becomes
available)
Clear
configuration
memory
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Power-On
CRC
correct?
Load CFG_IN
instruction
Shutdown
sequence
Reconfigure?
Load JSTART
instruction
Synchronous
TAP reset
(Clock five 1's
on TMS)
Start-Up
sequence
User mode
INIT_B = High?
PROG_B = Low
Load
JShutdown
instruction
No
DS099_27_041103
Load configuration
data frames
VCCINT >1V
and VCCAUX > 2V
and VCCO Bank 4 > 1V
INIT_B goes Low.
Abort Start-Up
Set PROG_B Low
after Power-On
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 53
Configuration is automatically initiated after power-on unless it is delayed by the user. INIT_B is an open-drain line that the
FPGA holds Low during the clearing of the configuration memory. Extending the time that the pin is Low causes the
configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded.
The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High. At this point, the configuration data is written to the FPGA. The FPGA pulses the
Global Set/Reset (GSR) signal at the end of configuration, resetting all flip-flops. The completion of the entire process is
signaled by the DONE pin going High.
The default start-up sequence, shown in Figure 31, serves as a transition to the User mode. The default start-up sequence
is that one CCLK cycle after DONE goes High, the Global Three-State signal (GTS) is released. This permits device outputs
to which signals have been assigned to become active. One CCLK cycle later, the Global Write Enable (GWE) signal is
released. This permits the internal storage elements to begin changing state in response to the design logic and the user
clock.
The relative timing of configuration events can be changed via the BitGen options in the Xilinx development software. In
addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the
devices to start synchronously. The sequence can also be paused at any stage, until lock has been achieved on any DCM.
Readback
Using Slave Parallel mode, configuration data from the FPGA can be read back. Readback is supported only in the Slave
Parallel and Boundary-Scan modes.
Along with the configuration data, it is possible to read back the contents of all registers, distributed RAM, and block RAM
resources. This capability is used for real-time debugging.
X-Ref Target - Figure 31
Figure 31: Default Start-Up Sequence
Start-Up Clock
Default Cycles
Sync-to-DONE
0123 4567
01
DONE High
23 4567
Phase
Start-Up Clock
Phase
DONE
GTS
GWE
DS099_028_060905
DONE
GTS
GWE
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 54
Additional Configuration Details
Additional details about the Spartan-3 FPGA configuration architecture and command set are available in UG332: Spartan-3
Generation Configuration User Guide and in application note XAPP452: Spartan-3 Advanced Configuration Architecture.
Powering Spartan-3 FPGAs
Voltage Regulators
Various power supply manufacturers offer complete power solutions for Xilinx FPGAs, including some with integrated
multi-rail regulators specifically designed for Spartan-3 FPGAs. The Xilinx Power Corner web page provides links to vendor
solution guides as well as Xilinx power estimation and analysis tools.
Power Distribution System (PDS) Design and Bypass/Decoupling Capacitors
Good power distribution system (PDS) design is important for all FPGA designs, especially for high-performance
applications. Proper design results in better overall performance, lower clock and DCM jitter, and a generally more robust
system. Before designing the printed circuit board (PCB) for the FPGA design, review application note XAPP623: Power
Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors.
Power-On Behavior
Spartan-3 FPGAs have a built-in Power-On Reset (POR) circuit that monitors the three power rails required to successfully
configure the FPGA. At power-up, the POR circuit holds the FPGA in a reset state until the VCCINT
, VCCAUX, and VCCO Bank
4 supplies reach their respective input threshold levels (see Table 29, page 59). After all three supplies reach their respective
threshold, the POR reset is released and the FPGA begins its configuration process.
Because the three supply inputs must be valid to release the POR reset and can be supplied in any order, there are no
specific voltage sequencing requirements. However, applying the FPGA’s VCCAUX supply before the VCCINT supply uses the
least ICCINT current.
Once all three supplies are valid, the minimum current required to power-on the FPGA is equal to the worst-case quiescent
current, as specified in Table 34, page 62. Spartan-3 FPGAs do not require Power-On Surge (POS) current to successfully
configure.
Surplus ICCINT if VCCINT Applied before VCCAUX
If the VCCINT supply is applied before the VCCAUX supply, the FPGA may draw a surplus ICCINT current in addition to the
ICCINT quiescent current levels specified in Ta bl e 3 4 . The momentary additional ICCINT surplus current might be a few
hundred milliamperes under nominal conditions, significantly less than the instantaneous current consumed by the bypass
capacitors at power-on. However, the surplus current immediately disappears when the VCCAUX supply is applied, and, in
response, the FPGA’s ICCINT quiescent current demand drops to the levels specified in Ta b l e 3 4 . The FPGA does not use
nor does it require the surplus current to successfully power-on and configure. If applying VCCINT
- before VCCAUX, ensure
that the regulator does not have a foldback feature that could inadvertently shut down in the presence of the surplus current.
Maximum Allowed VCCINT Ramp Rate on Early Devices, if VVCCINTSupply is Last in Sequence
All devices with a mask revision code ‘E’ or later do not have a VCCINT ramp rate requirement. See Mask and Fab Revisions,
page 58.
Early Spartan-3 FPGAs were produced at a 200 mm wafer production facility and are identified by a fabrication/process
code of "FQ" on the device top marking, as shown in Package Marking, page 5. These "FQ" devices have a maximum
VCCINT ramp rate requirement if and only if VCCINT is the last supply to ramp, after the VCCAUX and VCCO Bank 4 supplies.
This maximum ramp rate appears as TCCINT in Table 30, page 60.
Minimum Allowed VCCO Ramp Rate on Early Devices
Devices shipped since 2006 essentially have no VCCO ramp rate limits, shown in Table 30, page 60. Similarly, all devices
with a mask revision code ‘E’ or later do not have a VCCO ramp rate limit. See Mask and Fab Revisions, page 58.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 55
Initial Spartan-3 FPGA mask revisions have a limit on how fast the VCCO supply can ramp. The minimum allowed VCCO ramp
rate appears as TCCO in Table 30, page 60. The minimum rate is affected by the package inductance. Consequently, the ball
grid array and chip-scale packages (CP132, FT256, FG456, FG676, and FG900) allow a faster ramp rate than the quad-flat
packages (VQ100, TQ144, and PQ208).
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS configuration latches. The data in these latches is retained even
when the voltages drop to the minimum levels necessary to preserve RAM contents. This is specified in Table 31, page 60.
If, after configuration, the VCCAUX or VCCINT supply drops below its data retention voltage, clear the current device
configuration using one of the following methods:
Force the VCCAUX or VCCINT supply voltage below the minimum Power On Reset (POR) voltage threshold Tabl e 2 9 ,
page 59).
Assert PROG_B Low.
The POR circuit does not monitor the VCCO_4 supply after configuration. Consequently, dropping the VCCO_4 voltage
does not reset the device by triggering a Power-On Reset (POR) event.
No Internal Charge Pumps or Free-Running Oscillators
Some system applications are sensitive to sources of analog noise. Spartan-3 FPGA circuitry is fully static and does not
employ internal charge pumps.
The CCLK configuration clock is active during the FPGA configuration process. After configuration completes, the CCLK
oscillator is automatically disabled unless the Bitstream Generator (BitGen) option Persist=Yes. See Module 4: Tabl e 8 0,
page 125.
Spartan-3 FPGAs optionally support a featured called Digitally Controlled Impedance (DCI). When used in an application,
the DCI logic uses an internal oscillator. The DCI logic is only enabled if the FPGA application specifies an I/O standard that
requires DCI (LVDCI_33, LVDCI_25, etc.). If DCI is not used, the associated internal oscillator is also disabled.
In summary, unless an application uses the Persist=Yes option or specifies a DCI I/O standard, an FPGA with no external
switching remains fully static.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 56
Revision History
Date Version No. Description
04/11/2003 1.0 Initial Xilinx release
05/19/2003 1.1 Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
07/11/2003 1.2 Explained the configuration port Persist option in Slave Parallel Mode (SelectMAP) section. Updated
Figure 8 and Double-Data-Rate Transmission section to indicate that DDR clocking for the XC3S50 is the
same as that for all other Spartan-3 devices. Updated description of I/O voltage tolerance in ESD
Protection section. In Ta b le 1 0 , changed input termination type for DCI version of the LVCMOS standard
to None. Added additional flexibility for making DLL connections in Figure 21 and accompanying text. In
the Configuration section, inserted an explanation of how to choose power supplies for the configuration
interface, including guidelines for achieving 3.3V-tolerance.
08/24/2004 1.3 Showed inversion of 3-state signal (Figure 7). Clarified description of pull-up and pull-down resistors
(Ta bl e 6 and page 13). Added information on operating block RAM with multipliers to page 26. Corrected
output buffer name in Figure 21. Corrected description of how DOUT is synchronized to CCLK (page 47).
08/19/2005 1.4 Corrected description of WRITE_FIRST and READ_FIRST in Ta b l e 1 3 . Added note regarding address
setup and hold time requirements whenever a block RAM port is enabled (Ta bl e 1 3 ). Added information
in the maximum length of a Configuration daisy-chain. Added reference to XAPP453 in 3.3V-Tolerant
Configuration Interface section. Added information on the STATUS[2] DCM output (Ta b l e 2 3 ). Added
information on CCLK behavior and termination recommendations to Configuration. Added Additional
Configuration Details section. Added Powering Spartan-3 FPGAs section. Removed GSR from Figure 31
because its timing is not programmable.
04/03/2006 2.0 Updated Figure 7. Updated Figure 14. Updated Ta b l e 1 0 . Updated Figure 22. Corrected Platform Flash
supply voltage name and value in Figure 26 and Figure 28. Added No Internal Charge Pumps or
Free-Running Oscillators. Corrected a few minor typographical errors.
04/26/2006 2.1 Added more information on the pull-up resistors that are active during configuration to Configuration.
Added information to Boundary-Scan (JTAG) Mode about potential interactions when configuring via
JTAG if the mode select pins are set for other than JTAG.
05/25/2007 2.2 Added Spartan-3 FPGA Design Documentation. Noted SSTL2_I_DCI 25-Ohm driver in Ta bl e 1 0 and
Ta bl e 1 1 . Added note that pull-down is active during boundary scan tests.
11/30/2007 2.3 Updated links to documentation on xilinx.com.
06/25/2008 2.4 Added HSLVDCI to Ta b l e 1 0 . Updated formatting and links.
12/04/2009 2.5 Updated HSLVDCI description in Digitally Controlled Impedance (DCI). Updated the low-voltage
differential signaling VCCO values in Ta b l e 1 0 . Noted that the CP132 package is being discontinued in The
Organization of IOBs into Banks. Updated rule 4 in Rules Concerning Banks. Added software version
requirement in The Fixed Phase Mode.
10/29/2012 3.0 Added Notice of Disclaimer. Per XCN07022, updated the discontinued FG1156 and FGG1156 package
discussion throughout document. Per XCN08011, updated the discontinued CP132 and CPG132
package discussion throughout document. This product is not recommended for new designs.
06/27/2013 3.1 Removed banner. This product IS recommended for new designs.
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 57
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 58
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as
follows:
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics
of other families. Values are subject to change. Although speed grades with this designation are considered relatively
stable and conservative, some under-reporting might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characterization. Devices and speed grades with this designation are
intended to give a better indication of the expected performance of production silicon. The probability of under-reported
delays is greatly reduced compared to Advance data. Use as estimates, not for production.
Production: These specifications are approved only after silicon has been characterized over numerous production
lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes.
Parameter values are considered stable with no future changes expected.
Production-quality systems must only use FPGA designs compiled with a Production status speed file. FPGA designs
using a less mature speed file designation should only be used during system prototyping or preproduction qualification.
FPGA designs with speed files designated as Advance or Preliminary should not be used in a production-quality
system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE®
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following
applies unless otherwise noted: The parameter values published in this module apply to all Spartan®-3 devices. AC
and DC characteristics are specified using the same numbers for both commercial and industrial grades. All
parameters representing voltages are measured with respect to GND.
Mask and Fab Revisions
Some specifications list different values for one or more mask or fab revisions, indicated by the device top marking (see
Package Marking, page 5). The revision differences involve the power ramp rates, differential DC specifications, and DCM
characteristics. The most recent revision (mask rev E and GQ fab/geometry code) is errata-free with improved specifications
than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005 (see XCN05009) and has been 100% of Xilinx Spartan-3 device
shipments since 2006. SCD 0974 was provided to ensure the receipt of the rev E silicon, but it is no longer needed. Parts
ordered under the SCD appended “0974” to the standard part number. For example, “XC3S50-4VQ100C” became
“XC3S50-4VQ100C0974”.
106 Spartan-3 FPGA Family:
DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 Product Specification
Tabl e 2 8 : Absolute Maximum Ratings
Symbol Description Conditions Min Max Units
VCCINT Internal supply voltage relative to GND –0.5 1.32 V
VCCAUX Auxiliary supply voltage relative to GND –0.5 3.00 V
VCCO Output driver supply voltage relative to GND –0.5 3.75 V
VREF Input reference voltage relative to GND –0.5 VCCO +0.5 V
VIN Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(2,4)
Driver in a
high-impedance
state
Commercial –0.95 4.4 V
Industrial –0.85 4.3
Voltage applied to all Dedicated pins relative
to GND(3)
All temp. ranges –0.5 VCCAUX + 0.5 V
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 59
IIK Input clamp current per I/O pin –0.5 V < VIN < (VCCO + 0.5 V) ±100 mA
VESD Electrostatic Discharge Voltage pins relative
to GND
Human body model ±2000 V
Charged device model –±500V
Machine model –±200V
TJJunction temperature –125°C
TSOL Soldering temperature(4) –220°C
TSTG Storage temperature –65 150 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
2. All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the VCCO power rail of
the associated bank. Keeping VIN within 500 mV of the associated VCCO rails or ground rail ensures that the internal diode junctions that
exist between each of these pins and the VCCO and GND rails do not turn on. Tabl e 3 2 specifies the VCCO range used to determine the max
limit. Input voltages outside the –0.5V to VCCO+0.5V voltage range are permissible provided that the IIK input clamp diode rating is met and
no more than 100 pins exceed the range simultaneously. Prolonged exposure to such current may compromise device reliability. A sustained
current of 10 mA will not compromise device reliability. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing
Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs for more details. The VIN limits apply to both the DC and AC
components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as achieve PCI
compliance. Refer to the following application notes: XAPP457, Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI
Applications and XAPP659, Virtex®-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines.
3. All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V).
Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX rail do not turn on.
Ta b l e 3 2 specifies the VCCAUX range used to determine the max limit. When VCCAUX is at its maximum recommended operating level
(2.625V), VIN max < 3.125V. As long as the VIN max specification is met, oxide stress is not possible. For information concerning the use of
3.3V signals, see the 3.3V-Tolerant Configuration Interface, page 47. See also XAPP459.
4. For soldering guidelines, see UG112, Device Packaging and Thermal Characteristics and XAPP427, Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
Tabl e 2 9 : Supply Voltage Thresholds for Power-On Reset
Symbol Description Min Max Units
VCCINTT Threshold for the VCCINT supply 0.4 1.0 V
VCCAUXT Threshold for the VCCAUX supply 0.8 2.0 V
VCCO4T Threshold for the VCCO Bank 4 supply 0.4 1.0 V
Notes:
1. VCCINT
, VCCAUX, and VCCO supplies may be applied in any order. When applying VCCINT power before VCCAUX power, the FPGA may draw
a surplus current in addition to the quiescent current levels specified in Tab l e 3 4 . Applying VCCAUX eliminates the surplus current. The FPGA
does not use any of the surplus current for the power-on process. For this power sequence, make sure that regulators with foldback features
will not shut down inadvertently.
2. To ensure successful power-on, VCCINT
, VCCO Bank 4, and VCCAUX supplies must rise through their respective threshold-voltage ranges
with no dips at any point.
3. If a brown-out condition occurs where VCCAUX or VCCINT drops below the retention voltage indicated in Ta bl e 3 1 , then VCCAUX or VCCINT
must drop below the minimum power-on reset voltage in order to clear out the device configuration content.
Tabl e 2 8 : Absolute Maximum Ratings (Cont’d)
Symbol Description Conditions Min Max Units
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 60
Tabl e 3 0 : Power Voltage Ramp Time Requirements
Symbol Description Device Package Min Max Units
TCCO VCCO ramp time for all eight banks All All No limit(4) –N/A
TCCINT VCCINT ramp time, only if VCCINT is last in
three-rail power-on sequence
All All No limit No limit(5) N/A
Notes:
1. If a limit exists, this specification is based on characterization.
2. The ramp time is measured from 10% to 90% of the full nominal voltage swing for all I/O standards.
3. For information on power-on current needs, see Power-On Behavior, page 54
4. For mask revisions earlier than revision E (see Mask and Fab Revisions, page 58), TCCO min is limited to 2.0 ms for the XC3S200 and
XC3S400 devices in QFP packages, and limited to 0.6 ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in the FT and
FG packages.
5. For earlier device versions with the FQ fabrication/process code (see Mask and Fab Revisions, page 58), TCCINT max is limited to 500 µs.
Tabl e 3 1 : Power Voltage Levels Necessary for Preserving RAM Contents
Symbol Description Min Units
VDRINT VCCINT level required to retain RAM data 1.0 V
VDRAUX VCCAUX level required to retain RAM data 2.0 V
Notes:
1. RAM contents include data stored in CMOS configuration latches.
2. The level of the VCCO supply has no effect on data retention.
3. If a brown-out condition occurs where VCCAUX or VCCINT drops below the retention voltage, then VCCAUX or VCCINT must drop below the
minimum power-on reset voltage indicated in Tabl e 2 9 in order to clear out the device configuration content.
Tabl e 3 2 : General Recommended Operating Conditions
Symbol Description Min Nom Max Units
TJJunction temperature Commercial 0 25 85 °C
Industrial –40 25 100 °C
VCCINT Internal supply voltage 1.140 1.200 1.260 V
VCCO(1) Output driver supply voltage 1.140 3.465 V
VCCAUX Auxiliary supply voltage 2.375 2.500 2.625 V
ΔVCCAUX(2) Voltage variance on VCCAUX when using a DCM –10mV/ms
VIN(3) Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(4)(6)
VCCO = 3.3V, IO –0.3 –3.75V
VCCO = 3.3V, IO_Lxxy(7) –0.3 –3.75V
VCCO 2.5V, IO –0.3 –V
CCO +0.3
(4) V
VCCO 2.5V, IO_Lxxy(7) –0.3 –V
CCO +0.3
(4) V
Voltage applied to all Dedicated pins relative to GND(5) –0.3 –V
CCAUX+0.3
(5) V
Notes:
1. The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range
specific to each of the single-ended I/O standards is given in Tabl e 3 5, and that specific to the differential standards is given in Ta bl e 3 7 .
2. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
3. Input voltages outside the recommended range are permissible provided that the IIK input diode clamp diode rating is met. Refer to Ta bl e 2 8 .
4. Each of the User I/O and Dual-Purpose pins is associated with one of the VCCO rails. Meeting the VIN limit ensures that the internal diode
junctions that exist between these pins and their associated VCCO and GND rails do not turn on. The absolute maximum rating is provided
in Ta b l e 2 8 .
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures
that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on.
6. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3
Generation FPGAs.
7. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.3V is supported but can cause increased leakage
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 61
Tabl e 3 3 : General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol Description Test Conditions Min Typ Max Units
IL(2)(4) Leakage current at User I/O,
Dual-Purpose, and Dedicated pins
Driver is Hi-Z, VIN =
0V or VCCO max,
sample-tested
VCCO 3.0V –-±25 μA
VCCO < 3.0V –-±10 μA
IRPU(3) Current through pull-up resistor at User I/O,
Dual-Purpose, and Dedicated pins
VIN = 0V, VCCO = 3.3V –0.84 - –2.35 mA
VIN = 0V, VCCO = 3.0V –0.69 - –1.99 mA
VIN = 0V, VCCO = 2.5V –0.47 - –1.41 mA
VIN = 0V, VCCO = 1.8V –0.21 - –0.69 mA
VIN = 0V, VCCO = 1.5V –0.13 - –0.43 mA
VIN = 0V, VCCO = 1.2V –0.06 - –0.22 mA
RPU(3) Equivalent resistance of pull-up resistor at
User I/O, Dual-Purpose, and Dedicated
pins, derived from IRPU
VCCO = 3.0V to 3.465V 1.27 - 4.11 kΩ
VCCO = 2.3V to 2.7V 1.15 - 3.25 kΩ
VCCO = 1.7V to 1.9V 2.45 - 9.10 kΩ
VCCO = 1.4V to 1.6V 3.25 - 12.10 kΩ
VCCO = 1.14 to 1.26V 5.15 - 21.00 kΩ
IRPD(3) Current through pull-down resistor at User
I/O, Dual-Purpose, and Dedicated pins
VIN = VCCO 0.37 - 1.67 mA
RPD(3) Equivalent resistance of pull-down resistor
at User I/O, Dual-Purpose, and Dedicated
pins, driven from IRPD
VIN = VCCO = 3.0V to 3.465V 1.75 - 9.35 kΩ
VIN = VCCO = 2.3V to 2.7V 1.35 - 7.30 kΩ
VIN = VCCO = 1.7V to 1.9V 1.00 - 5.15 kΩ
VIN = VCCO = 1.4V to 1.6V 0.85 - 4.35 kΩ
VIN = VCCO = 1.14 to 1.26V 0.68 - 3.465 kΩ
RDCI Value of external reference resistor to support DCI I/O standards 20 - 100 Ω
IREF VREF current per pin VCCO 3.0V –-±25 μA
VCCO < 3.0V –-±10 μA
CIN Input capacitance 3 - 10 pF
Notes:
1. The numbers in this table are based on the conditions set forth in Table 3 2.
2. The IL specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute VIN minimum
and maximum values (Ta b l e 2 8 ). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range
before applying VCCO power. Consider applying VCCO power before connecting the signal lines, to avoid turning on the ESD protection
diodes, shown in Module 2: Figure 7, page 11. When the FPGA is completely unpowered, the I/O pins are high impedance, but there is a
path through the upper and lower ESD protection diodes.
3. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD =V
IN /I
RPD.
Spartan-3 family values for both resistances are stronger than they have been for previous FPGA families.
4. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.3V is supported but can cause increased leakage
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 62
Tabl e 3 4 : Quiescent Supply Current Characteristics
Symbol Description Device Typical(1) Commercial
Maximum(1)
Industrial
Maximum(1) Units
ICCINTQ Quiescent VCCINT supply current XC3S50 5 24 31 mA
XC3S200 10 54 80 mA
XC3S400 15 110 157 mA
XC3S1000 35 160 262 mA
XC3S1500 45 260 332 mA
XC3S2000 60 360 470 mA
XC3S4000 100 450 810 mA
XC3S5000 120 600 870 mA
ICCOQ Quiescent VCCO supply current XC3S50 1.5 2.0 2.5 mA
XC3S200 1.5 3.0 3.5 mA
XC3S400 1.5 3.0 3.5 mA
XC3S1000 2.0 4.0 5.0 mA
XC3S1500 2.5 4.0 5.0 mA
XC3S2000 3.0 5.0 6.0 mA
XC3S4000 3.5 5.0 6.0 mA
XC3S5000 3.5 5.0 6.0 mA
ICCAUXQ Quiescent VCCAUX supply current XC3S50 7 20 22 mA
XC3S200 10 30 33 mA
XC3S400 15 40 44 mA
XC3S1000 20 50 55 mA
XC3S1500 35 75 85 mA
XC3S2000 45 90 100 mA
XC3S4000 55 110 125 mA
XC3S5000 70 130 145 mA
Notes:
1. The numbers in this table are based on the conditions set forth in Table 3 2. Quiescent supply current is measured with all I/O drivers in a
high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using devices with
typical processing at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 2.5V). Maximum values are the
production test limits measured for each device at the maximum specified junction temperature and at maximum voltage limits with
VCCINT = 1.26V, VCCO = 3.465V, and VCCAUX = 2.625V. The FPGA is programmed with a "blank" configuration data file (i.e., a design with
no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements, the use
of DCI standards, etc.), measured quiescent current levels may be different than the values in the table. Use the XPower Estimator or
XPower Analyzer for more accurate estimates. See Note 2.
2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3
XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer, part of
the Xilinx ISE development software, uses the FPGA netlist as input to provide more accurate maximum and typical estimates.
3. The maximum numbers in this table also indicate the minimum current each power rail requires in order for the FPGA to power-on
successfully, once all three rails are supplied. If VCCINT is applied before VCCAUX, there may be temporary additional ICCINT current until
VCCAUX is applied. See Surplus ICCINT if VCCINT Applied before VCCAUX, page 54
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 63
Tabl e 3 5 : Recommended Operating Conditions for User I/Os Using Single-Ended Standards
Signal Standard
(IOSTANDARD)
VCCO VREF VIL VIH
Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V)
GTL(3) –– –0.74 0.8 0.86 VREF – 0.05 VREF + 0.05
GTL_DCI 1.2 0.74 0.8 0.86 VREF – 0.05 VREF + 0.05
GTLP(3) –– –0.88 1 1.12 VREF – 0.1 VREF + 0.1
GTLP_DCI 1.5 0.88 1 1.12 VREF – 0.1 VREF + 0.1
HSLVDCI_15 1.4 1.5 1.6 0.75 VREF – 0.1 VREF + 0.1
HSLVDCI_18 1.7 1.8 1.9 0.9 VREF – 0.1 VREF + 0.1
HSLVDCI_25 2.3 2.5 2.7 1.25 VREF – 0.1 VREF + 0.1
HSLVDCI_33 3.0 3.3 3.465 1.65 VREF – 0.1 VREF + 0.1
HSTL_I, HSTL_I_DCI 1.4 1.5 1.6 0.68 0.75 0.9 VREF – 0.1 VREF + 0.1
HSTL_III,
HSTL_III_DCI 1.4 1.5 1.6 0.9 VREF – 0.1 VREF + 0.1
HSTL_I_18,
HSTL_I_DCI_18 1.7 1.8 1.9 0.8 0.9 1.1 VREF – 0.1 VREF + 0.1
HSTL_II_18,
HSTL_II_DCI_18 1.7 1.8 1.9 0.9 VREF – 0.1 VREF + 0.1
HSTL_III_18,
HSTL_III_DCI_18 1.7 1.8 1.9 1.1 VREF – 0.1 VREF + 0.1
LVCMOS12 1.14 1.2 1.3 – – –0.37V
CCO 0.58VCCO
LVC M OS 1 5,
LVDCI_15,
LVDCI_DV2_15
1.4 1.5 1.6 – – –0.30V
CCO 0.70VCCO
LVC M OS 1 8,
LVDCI_18,
LVDCI_DV2_18
1.7 1.8 1.9 – – –0.30V
CCO 0.70VCCO
LVC M OS 2 5(4,5),
LVDCI_25,
LVDCI_DV2_25(4) 2.3 2.5 2.7 – – –0.7 1.7
LVC M OS 3 3,
LVDCI_33,
LVDCI_DV2_33(4) 3.0 3.3 3.465 – – –0.8 2.0
LVTTL 3.0 3.3 3.465 – – –0.8 2.0
PCI33_3(7) 3.0 3.3 3.465 – – –0.30V
CCO 0.50VCCO
SSTL18_I,
SSTL18_I_DCI 1.7 1.8 1.9 0.833 0.900 0.969 VREF – 0.125 VREF + 0.125
SSTL18_II 1.7 1.8 1.9 0.833 0.900 0.969 VREF – 0.125 VREF + 0.125
SSTL2_I,
SSTL2_I_DCI 2.3 2.5 2.7 1.15 1.25 1.35 VREF – 0.15 VREF + 0.15
SSTL2_II,
SSTL2_II_DCI 2.3 2.5 2.7 1.15 1.25 1.35 VREF – 0.15 VREF + 0.15
Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
2. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Tabl e 28.
3. Because the GTL and GTLP standards employ open-drain output buffers, VCCO lines do not supply current to the I/O circuit, rather this current is
provided using an external pull-up resistor connected from the I/O pin to a termination voltage (VTT). Nevertheless, the voltage applied to the
associated VCCO lines must always be at or above VTT and I/O pad voltages.
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS25 or LVCMOS33 standards.
5. All dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS standard and draw power from the
VCCAUX rail (2.5V). The dual-purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) use the LVCMOS standard
before the user mode. For these pins, apply 2.5V to the VCCO Bank 4 and VCCO Bank 5 rails at power-on and throughout configuration. For information
concerning the use of 3.3V signals, see 3.3V-Tolerant Configuration Interface, page 47.
6. The Global Clock Inputs (GCLK0-GCLK7) are dual-purpose pins to which any signal standard can be assigned.
7. For more information, see XAPP457.
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013 www.xilinx.com
Product Specification 64
Tabl e 3 6 : DC Characteristics of User I/Os Using Single-Ended Standards
Signal Standard
(IOSTANDARD) and Current
Drive Attribute (mA)
Test Conditions Logic Level Characteristics
IOL
(mA)
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
GTL 32 – 0.4 –
GTL_DCI Note 3Note 3
GTLP 36 0.6
GTLP_DCI Note 3Note 3
HSLVDCI_15 Note 3Note 30.4 VCCO – 0.4
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I 8 –8 0.4 VCCO – 0.4
HSTL_I_DCI Note 3Note 3
HSTL_III 24 8 0.4 VCCO – 0.4
HSTL_III_DCI Note 3Note 3
HSTL_I_18 8 –8 0.4 VCCO – 0.4
HSTL_I_DCI_18 Note 3Note 3
HSTL_II_18 16 –16 0.4 VCCO – 0.4
HSTL_II_DCI_18 Note 3Note 3
HSTL_III_18 24 8 0.4 VCCO – 0.4