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nRF52832 Specification

Nordic Semiconductor ASA

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2017-10-10
nRF52832 Product Specification v1.4
Key features Applications
Internet of Things (IoT)
Home automation
Sensor networks
Building automation
• Industrial
• Retail
Personal area networks
Health/fitness sensor and monitor devices
Medical devices
Key fobs and wrist watches
Interactive entertainment devices
Remote controls
Gaming controllers
Beacons
A4WP wireless chargers and devices
Remote control toys
Computer peripherals and I/O devices
• Mouse
• Keyboard
Multi-touch trackpad
• Gaming
2.4 GHz transceiver
-96 dBm sensitivity in Bluetooth® low energy mode
Supported data rates: 1 Mbps, 2 Mbps Bluetooth® low energy mode
-20 to +4 dBm TX power, configurable in 4 dB steps
On-chip balun (single-ended RF)
5.3 mA peak current in TX (0 dBm)
5.4 mA peak current in RX
RSSI (1 dB resolution)
• ARM® Cortex®-M4 32-bit processor with FPU, 64 MHz
215 EEMBC CoreMark® score running from flash memory
58 μA/MHz running from flash memory
51.6 μA/MHz running from RAM
Data watchpoint and trace (DWT), embedded trace macrocell (ETM), and
instrumentation trace macrocell (ITM)
Serial wire debug (SWD)
Trace port
Flexible power management
1.7 V–3.6 V supply voltage range
Fully automatic LDO and DC/DC regulator system
Fast wake-up using 64 MHz internal oscillator
0.3 μA at 3 V in System OFF mode
0.7 μA at 3 V in System OFF mode with full 64 kB RAM retention
1.9 μA at 3 V in System ON mode, no RAM retention, wake on RTC
• Memory
512 kB flash/64 kB RAM
256 kB flash/32 kB RAM
Nordic SoftDevice ready
Support for concurrent multi-protocol
Type 2 near field communication (NFC-A) tag with wakeup-on-field and touch-
to-pair capabilities
12-bit, 200 ksps ADC - 8 configurable channels with programmable gain
64 level comparator
15 level low power comparator with wakeup from System OFF mode
Temperature sensor
32 general purpose I/O pins
3x 4-channel pulse width modulator (PWM) unit with EasyDMA
Digital microphone interface (PDM)
5x 32-bit timer with counter mode
Up to 3x SPI master/slave with EasyDMA
Up to 2x I2C compatible 2-wire master/slave
I2S with EasyDMA
UART (CTS/RTS) with EasyDMA
Programmable peripheral interconnect (PPI)
Quadrature decoder (QDEC)
AES HW encryption with EasyDMA
Autonomous peripheral operation without CPU intervention using PPI and
EasyDMA
3x real-time counter (RTC)
Single crystal operation
Package variants
QFN48 package, 6 × 6 mm
WLCSP package, 3.0 × 3.2 mm
Contents
Page 2
Contents
1 Revision history...................................................................................9
2 About this document............................................................................................ 10
2.1 Document naming and status...............................................................................................10
2.2 Peripheral naming and abbreviations................................................................................... 10
2.3 Register tables...................................................................................................................... 10
2.4 Registers............................................................................................................................... 11
3 Block diagram........................................................................................................12
4 Pin assignments....................................................................................................13
4.1 QFN48 pin assignments....................................................................................................... 13
4.2 WLCSP ball assignments..................................................................................................... 15
4.3 GPIO usage restrictions........................................................................................................17
5 Absolute maximum ratings.................................................................................. 19
6 Recommended operating conditions.................................................................. 20
6.1 WLCSP light sensitivity.........................................................................................................20
7 CPU......................................................................................................................... 21
7.1 Floating point interrupt.......................................................................................................... 21
7.2 Electrical specification...........................................................................................................21
7.3 CPU and support module configuration................................................................................22
8 Memory................................................................................................................... 23
8.1 RAM - Random access memory...........................................................................................23
8.2 Flash - Non-volatile memory.................................................................................................24
8.3 Memory map......................................................................................................................... 24
8.4 Instantiation........................................................................................................................... 24
9 AHB multilayer.......................................................................................................26
9.1 AHB multilayer priorities........................................................................................................26
10 EasyDMA.............................................................................................................. 27
10.1 EasyDMA array list............................................................................................................. 28
11 NVMC Non-volatile memory controller.........................................................29
11.1 Writing to Flash...................................................................................................................29
11.2 Erasing a page in Flash..................................................................................................... 29
11.3 Writing to user information configuration registers (UICR)................................................. 29
11.4 Erasing user information configuration registers (UICR).................................................... 29
11.5 Erase all.............................................................................................................................. 30
11.6 Cache.................................................................................................................................. 30
11.7 Registers............................................................................................................................. 30
11.8 Electrical specification.........................................................................................................33
12 BPROT Block protection................................................................................34
12.1 Registers............................................................................................................................. 34
13 FICR Factory information configuration registers.......................................43
13.1 Registers............................................................................................................................. 43
14 UICR User information configuration registers........................................... 54
14.1 Registers............................................................................................................................. 54
15 Peripheral interface.............................................................................................68
15.1 Peripheral ID....................................................................................................................... 68
15.2 Peripherals with shared ID..................................................................................................68
15.3 Peripheral registers.............................................................................................................69
15.4 Bit set and clear..................................................................................................................69
15.5 Tasks...................................................................................................................................69
15.6 Events..................................................................................................................................70
Contents
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15.7 Shortcuts............................................................................................................................. 70
15.8 Interrupts............................................................................................................................. 70
16 Debug and trace.................................................................................................. 72
16.1 DAP - Debug Access Port..................................................................................................72
16.2 CTRL-AP - Control Access Port......................................................................................... 73
16.3 Debug interface mode.........................................................................................................74
16.4 Real-time debug..................................................................................................................74
16.5 Trace................................................................................................................................... 75
17 Power and clock management...........................................................................76
17.1 Current consumption scenarios.......................................................................................... 76
18 POWER Power supply....................................................................................78
18.1 Regulators........................................................................................................................... 78
18.2 System OFF mode..............................................................................................................79
18.3 System ON mode............................................................................................................... 80
18.4 Power supply supervisor.....................................................................................................80
18.5 RAM sections......................................................................................................................82
18.6 Reset................................................................................................................................... 82
18.7 Retained registers...............................................................................................................83
18.8 Reset behavior....................................................................................................................83
18.9 Registers............................................................................................................................. 83
18.10 Electrical specification.......................................................................................................99
19 CLOCK Clock control...................................................................................101
19.1 HFCLK clock controller..................................................................................................... 101
19.2 LFCLK clock controller......................................................................................................103
19.3 Registers........................................................................................................................... 105
19.4 Electrical specification.......................................................................................................109
20 GPIO General purpose input/output........................................................... 111
20.1 Pin configuration............................................................................................................... 111
20.2 GPIO located near the RADIO......................................................................................... 113
20.3 Registers........................................................................................................................... 113
20.4 Electrical specification.......................................................................................................154
21 GPIOTE GPIO tasks and events..................................................................157
21.1 Pin events and tasks........................................................................................................ 157
21.2 Port event..........................................................................................................................158
21.3 Tasks and events pin configuration..................................................................................158
21.4 Registers........................................................................................................................... 158
21.5 Electrical specification.......................................................................................................167
22 PPI Programmable peripheral interconnect...............................................168
22.1 Pre-programmed channels................................................................................................169
22.2 Registers........................................................................................................................... 169
23 RADIO 2.4 GHz Radio.................................................................................. 205
23.1 EasyDMA...........................................................................................................................205
23.2 Packet configuration..........................................................................................................206
23.3 Maximum packet length....................................................................................................207
23.4 Address configuration........................................................................................................207
23.5 Data whitening.................................................................................................................. 207
23.6 CRC...................................................................................................................................208
23.7 Radio states...................................................................................................................... 209
23.8 Transmit sequence............................................................................................................209
23.9 Receive sequence.............................................................................................................211
23.10 Received Signal Strength Indicator (RSSI).....................................................................212
23.11 Interframe spacing...........................................................................................................212
23.12 Device address match.................................................................................................... 213
23.13 Bit counter.......................................................................................................................213
23.14 Registers......................................................................................................................... 214
23.15 Electrical specification.....................................................................................................230
24 TIMER Timer/counter....................................................................................234
Contents
Page 4
24.1 Capture..............................................................................................................................235
24.2 Compare............................................................................................................................235
24.3 Task delays.......................................................................................................................235
24.4 Task priority.......................................................................................................................235
24.5 Registers........................................................................................................................... 235
24.6 Electrical specification.......................................................................................................241
25 RTC Real-time counter.................................................................................242
25.1 Clock source..................................................................................................................... 242
25.2 Resolution versus overflow and the PRESCALER...........................................................242
25.3 COUNTER register............................................................................................................243
25.4 Overflow features..............................................................................................................243
25.5 TICK event........................................................................................................................ 243
25.6 Event control feature.........................................................................................................244
25.7 Compare feature............................................................................................................... 244
25.8 TASK and EVENT jitter/delay...........................................................................................246
25.9 Reading the COUNTER register.......................................................................................248
25.10 Registers......................................................................................................................... 248
25.11 Electrical specification.....................................................................................................254
26 RNG Random number generator................................................................ 255
26.1 Bias correction.................................................................................................................. 255
26.2 Speed................................................................................................................................ 255
26.3 Registers........................................................................................................................... 255
26.4 Electrical specification.......................................................................................................257
27 TEMP Temperature sensor.......................................................................... 258
27.1 Registers........................................................................................................................... 258
27.2 Electrical specification.......................................................................................................263
28 ECB AES electronic codebook mode encryption......................................264
28.1 Shared resources..............................................................................................................264
28.2 EasyDMA...........................................................................................................................264
28.3 ECB data structure............................................................................................................264
28.4 Registers........................................................................................................................... 265
28.5 Electrical specification.......................................................................................................266
29 CCM AES CCM mode encryption................................................................267
29.1 Shared resources..............................................................................................................268
29.2 Encryption..........................................................................................................................268
29.3 Decryption......................................................................................................................... 268
29.4 AES CCM and RADIO concurrent operation....................................................................269
29.5 Encrypting packets on-the-fly in radio transmit mode.......................................................269
29.6 Decrypting packets on-the-fly in radio receive mode........................................................270
29.7 CCM data structure...........................................................................................................271
29.8 EasyDMA and ERROR event...........................................................................................272
29.9 Registers........................................................................................................................... 272
30 AAR Accelerated address resolver.............................................................276
30.1 Shared resources..............................................................................................................276
30.2 EasyDMA...........................................................................................................................276
30.3 Resolving a resolvable address........................................................................................276
30.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................277
30.5 IRK data structure.............................................................................................................277
30.6 Registers........................................................................................................................... 278
30.7 Electrical specification.......................................................................................................280
31 SPIM Serial peripheral interface master with EasyDMA............................281
31.1 Shared resources..............................................................................................................281
31.2 EasyDMA...........................................................................................................................282
31.3 SPI master transaction sequence.....................................................................................283
31.4 Low power.........................................................................................................................284
31.5 Master mode pin configuration......................................................................................... 284
Contents
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31.6 Registers........................................................................................................................... 285
31.7 Electrical specification.......................................................................................................290
32 SPIS Serial peripheral interface slave with EasyDMA...............................292
32.1 Shared resources..............................................................................................................292
32.2 EasyDMA...........................................................................................................................292
32.3 SPI slave operation...........................................................................................................293
32.4 Pin configuration............................................................................................................... 294
32.5 Registers........................................................................................................................... 295
32.6 Electrical specification.......................................................................................................303
33 TWIM — I2C compatible two-wire interface master with EasyDMA...............305
33.1 Shared resources..............................................................................................................306
33.2 EasyDMA...........................................................................................................................306
33.3 Master write sequence......................................................................................................307
33.4 Master read sequence...................................................................................................... 308
33.5 Master repeated start sequence.......................................................................................309
33.6 Low power.........................................................................................................................310
33.7 Master mode pin configuration......................................................................................... 310
33.8 Registers........................................................................................................................... 310
33.9 Electrical specification.......................................................................................................317
34 TWIS I2C compatible two-wire interface slave with EasyDMA..................319
34.1 Shared resources..............................................................................................................321
34.2 EasyDMA...........................................................................................................................321
34.3 TWI slave responding to a read command.......................................................................321
34.4 TWI slave responding to a write command...................................................................... 322
34.5 Master repeated start sequence.......................................................................................323
34.6 Terminating an ongoing TWI transaction..........................................................................324
34.7 Low power.........................................................................................................................324
34.8 Slave mode pin configuration........................................................................................... 324
34.9 Registers........................................................................................................................... 325
34.10 Electrical specification.....................................................................................................331
35 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 333
35.1 Shared resources..............................................................................................................333
35.2 EasyDMA...........................................................................................................................333
35.3 Transmission..................................................................................................................... 334
35.4 Reception.......................................................................................................................... 334
35.5 Error conditions.................................................................................................................336
35.6 Using the UARTE without flow control............................................................................. 336
35.7 Parity configuration............................................................................................................336
35.8 Low power.........................................................................................................................336
35.9 Pin configuration............................................................................................................... 337
35.10 Registers......................................................................................................................... 337
35.11 Electrical specification.....................................................................................................345
36 QDEC Quadrature decoder..........................................................................347
36.1 Sampling and decoding.................................................................................................... 347
36.2 LED output........................................................................................................................ 348
36.3 Debounce filters................................................................................................................ 348
36.4 Accumulators.....................................................................................................................349
36.5 Output/input pins...............................................................................................................349
36.6 Pin configuration............................................................................................................... 349
36.7 Registers........................................................................................................................... 350
36.8 Electrical specification.......................................................................................................356
37 SAADC — Successive approximation analog-to-digital converter...............357
37.1 Shared resources..............................................................................................................357
37.2 Overview............................................................................................................................357
37.3 Digital output..................................................................................................................... 358
37.4 Analog inputs and channels..............................................................................................359
37.5 Operation modes...............................................................................................................359
Contents
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37.6 EasyDMA...........................................................................................................................361
37.7 Resistor ladder..................................................................................................................362
37.8 Reference..........................................................................................................................363
37.9 Acquisition time.................................................................................................................363
37.10 Limits event monitoring...................................................................................................364
37.11 Registers......................................................................................................................... 365
37.12 Electrical specification.....................................................................................................389
37.13 Performance factors........................................................................................................391
38 COMP Comparator........................................................................................392
38.1 Differential mode...............................................................................................................393
38.2 Single-ended mode........................................................................................................... 394
38.3 Registers........................................................................................................................... 396
38.4 Electrical specification.......................................................................................................401
39 LPCOMP Low power comparator................................................................402
39.1 Shared resources..............................................................................................................403
39.2 Pin configuration............................................................................................................... 403
39.3 Registers........................................................................................................................... 404
39.4 Electrical specification.......................................................................................................408
40 WDT Watchdog timer................................................................................... 409
40.1 Reload criteria...................................................................................................................409
40.2 Temporarily pausing the watchdog...................................................................................409
40.3 Watchdog reset.................................................................................................................409
40.4 Registers........................................................................................................................... 410
40.5 Electrical specification.......................................................................................................414
41 SWI Software interrupts...............................................................................415
41.1 Registers........................................................................................................................... 415
42 NFCT Near field communication tag...........................................................416
42.1 Overview............................................................................................................................416
42.2 Pin configuration............................................................................................................... 418
42.3 EasyDMA...........................................................................................................................418
42.4 Collision resolution............................................................................................................419
42.5 Frame timing controller..................................................................................................... 420
42.6 Frame assembler.............................................................................................................. 421
42.7 Frame disassembler..........................................................................................................422
42.8 Antenna interface..............................................................................................................423
42.9 NFCT antenna recommendations.....................................................................................423
42.10 Battery protection............................................................................................................423
42.11 References...................................................................................................................... 424
42.12 Registers......................................................................................................................... 424
42.13 Electrical specification.....................................................................................................435
43 PDM Pulse density modulation interface................................................... 436
43.1 Master clock generator..................................................................................................... 436
43.2 Module operation.............................................................................................................. 436
43.3 Decimation filter................................................................................................................ 437
43.4 EasyDMA...........................................................................................................................437
43.5 Hardware example............................................................................................................438
43.6 Pin configuration............................................................................................................... 438
43.7 Registers........................................................................................................................... 439
43.8 Electrical specification.......................................................................................................443
44 I2S Inter-IC sound interface......................................................................... 445
44.1 Mode..................................................................................................................................445
44.2 Transmitting and receiving................................................................................................445
44.3 Left right clock (LRCK)..................................................................................................... 446
44.4 Serial clock (SCK).............................................................................................................446
44.5 Master clock (MCK).......................................................................................................... 447
44.6 Width, alignment and format.............................................................................................447
44.7 EasyDMA...........................................................................................................................449
Contents
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44.8 Module operation.............................................................................................................. 451
44.9 Pin configuration............................................................................................................... 452
44.10 Registers......................................................................................................................... 453
44.11 Electrical specification.....................................................................................................460
45 MWU Memory watch unit.............................................................................461
45.1 Registers........................................................................................................................... 461
46 EGU Event generator unit............................................................................488
46.1 Registers........................................................................................................................... 488
46.2 Electrical specification.......................................................................................................494
47 PWM Pulse width modulation..................................................................... 495
47.1 Wave counter....................................................................................................................495
47.2 Decoder with EasyDMA....................................................................................................498
47.3 Limitations......................................................................................................................... 503
47.4 Pin configuration............................................................................................................... 503
47.5 Registers........................................................................................................................... 504
47.6 Electrical specification.......................................................................................................512
48 SPI Serial peripheral interface master........................................................513
48.1 Functional description....................................................................................................... 513
48.2 Registers........................................................................................................................... 516
48.3 Electrical specification.......................................................................................................519
49 TWI I2C compatible two-wire interface....................................................... 521
49.1 Functional description....................................................................................................... 521
49.2 Master mode pin configuration......................................................................................... 521
49.3 Shared resources..............................................................................................................522
49.4 Master write sequence......................................................................................................522
49.5 Master read sequence...................................................................................................... 523
49.6 Master repeated start sequence.......................................................................................524
49.7 Low power.........................................................................................................................525
49.8 Registers........................................................................................................................... 525
49.9 Electrical specification.......................................................................................................529
50 UART Universal asynchronous receiver/transmitter.................................531
50.1 Functional description....................................................................................................... 531
50.2 Pin configuration............................................................................................................... 531
50.3 Shared resources..............................................................................................................532
50.4 Transmission..................................................................................................................... 532
50.5 Reception.......................................................................................................................... 532
50.6 Suspending the UART...................................................................................................... 533
50.7 Error conditions.................................................................................................................533
50.8 Using the UART without flow control................................................................................534
50.9 Parity configuration............................................................................................................534
50.10 Registers......................................................................................................................... 534
50.11 Electrical specification.....................................................................................................539
51 Mechanical specifications................................................................................ 540
51.1 QFN48 6 x 6 mm package...............................................................................................540
51.2 WLCSP package...............................................................................................................541
52 Ordering information.........................................................................................542
52.1 IC marking.........................................................................................................................542
52.2 Box labels..........................................................................................................................542
52.3 Order code........................................................................................................................ 543
52.4 Code ranges and values...................................................................................................543
52.5 Product options................................................................................................................. 544
53 Reference circuitry............................................................................................545
53.1 Schematic QFAA and QFAB QFN48 with internal LDO setup......................................... 545
53.2 Schematic QFAA and QFAB QFN48 with DC/DC regulator setup................................... 546
53.3 Schematic QFAA and QFAB QFN48 with DC/DC regulator and NFC setup.................... 547
53.4 Schematic CIAA WLCSP with internal LDO setup........................................................... 548
53.5 Schematic CIAA WLCSP with DC/DC regulator setup.....................................................549
Contents
Page 8
53.6 Schematic CIAA WLCSP with DC/DC regulator and NFC setup......................................550
53.7 PCB guidelines..................................................................................................................550
53.8 PCB layout example......................................................................................................... 551
54 Liability disclaimer............................................................................................ 553
54.1 RoHS and REACH statement...........................................................................................553
54.2 Life support applications................................................................................................... 553
1 Revision history
Page 9
1 Revision history
Date Version Description
October 2017 1.4 The following content has been added or updated:
Recommended operating conditions on page
20: Added WLCSP light sensitivity information.
FICR — Factory information configuration
registers on page 43: Added registers PARTNO,
HWREVISION and PRODUCTIONREVISION.
UICR — User information configuration registers
on page 54: Changed width of PSELRESETn
port fields.
SPIM: Polarity in SPI mode table corrected.
COMP — Comparator on page 392:
Documentation structure improvements/changes.
Liability disclaimer updated: Directive 2011/65/EU
(RoHS 2).
February 2017 1.3 The following content has been added or updated:
RADIO — 2.4 GHz Radio on page 205:
Introduced 2 Mbps Bluetooth® low energy mode.
FICR — Factory information configuration registers
on page 43: Updated INFO.PACKAGE register
(new package added).
UARTE: Corrected the pin configuration table.
PPI — Programmable peripheral interconnect on
page 168: Timing information corrected.
Updated the liability disclaimer.
September 2016 1.2 Updated the following:
Power and clock management, Current
consumption: Ultra-low power on page 77.
Power, Current consumption, sleep on page
99
July 2016 1.1 Added documentation for nRF52832 CIAA WLCSP.
Added or updated the following content:
Cover: Added Key features.
Pin assignments on page 13: Added WLCSP
ball assignments. Moved GPIO usage restrictions
here from GPIO/Notes on usage and restrictions.
Absolute maximum ratings on page 19: Added
environmental information for WLCSP to the
table.
Memory on page 23: Added QFAB and CIAA
information to the table.
FICR — Factory information configuration registers
on page 43: Updated INFO.PACKAGE register.
UICR — User information configuration registers
on page 54: Updated APPROTECT register.
Debug and trace on page 72: Updated DAP -
Debug access port.
POWER — Power supply on page 78: Updated
Pin reset.
CLOCK — Clock control on page 101: Updated
information on external 32 kHz clock support.
GPIO — General purpose input/output on page
111: Added GPIO located near the RADIO.
RADIO — 2.4 GHz Radio on page 205: Updated
Figure 29 and Interframe spacing.
CCM: Updated SCRATCHPTR register.
SPIM: Updated Master mode pin configuration.
UARTE: Added RXDRDY and TXDRDY events.
NFCT: Updated Electrical specifications.
PWM — Pulse width modulation on page 495:
Updated SEQ[1].REFRESH register.
Mechanical specifications on page 540: Added
WLCSP package.
Ordering information on page 542: Updated
with CIAA and QFAB information.
Reference circuitry on page 545: QFAB
information added. CIAA WLCSP schematics
added.
February 2016 1.0 First release.
2 About this document
Page 10
2 About this document
This product specification is organized into chapters based on the modules and peripherals that are available
in this IC.
The peripheral descriptions are divided into separate sections that include the following information:
A detailed functional description of the peripheral
Register configuration for the peripheral
Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 20.
2.1 Document naming and status
Nordic uses three distinct names for this document, which are reflecting the maturity and the status of the
document and its content.
Table 1: Defined document names
Document name Description
Objective Product Specification (OPS) Applies to document versions up to 0.7.
This product specification contains target specifications for product development.
Preliminary Product Specification (PPS) Applies to document versions 0.7 and up to 1.0.
This product specification contains preliminary data. Supplementary data may be
published from Nordic Semiconductor ASA later.
Product Specification (PS) Applies to document versions 1.0 and higher.
This product specification contains final product specifications. Nordic
Semiconductor ASA reserves the right to make changes at any time without notice
in order to improve design and supply the best possible product.
2.2 Peripheral naming and abbreviations
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in the
ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify
the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally
only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in
the CMSIS to identify the peripheral instance.
2.3 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
2.3.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has
enumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to
secure forward compatibility. If a register is divided into more than one field, a unique field name is specified
for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be
substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/off, and so on.
2 About this document
Page 11
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal
values have no prefix.
The Value column can be populated in the following ways:
Individual enumerated values, for example 1, 3, 9.
Range of values, e.g. [0..4], indicating all values from and including 0 and 4.
Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the
first field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.4 Registers
Table 2: Register Overview
Register Offset Description
DUMMY 0x514 Example of a register controlling a dummy feature
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D C C C B A A
Reset 0x00050002 0 0000000000001010000000000000010
Id RW Field Value Id Value Description
A RW FIELD_A Example of a field with several enumerated values
Disabled 0 The example feature is disabled
NormalMode 1 The example feature is enabled in normal mode
ExtendedMode 2 The example feature is enabled along with extra functionality
B RW FIELD_B Example of a deprecated field Deprecated
Disabled 0 The override feature is disabled
Enabled 1 The override feature is enabled
C RW FIELD_C Example of a field with a valid range of values
ValidRange [2..7] Example of allowed values for this field
D RW FIELD_D Example of a field with no restriction on the values
3 Block diagram
Page 12
3 Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
nRF52832
APB0
AHB TO APB
BRIDGE
RADIO
AHB
Multi-Layer
CPU
ARM
CORTEX-M4
ECB
AHB-AP
RNG
TEMP
WDT
NVMC
ANT1
ANT2
POWER
nRESET
RTC [0..2]
PPI
CLOCK
XL2
XL1
XC2
XC1
TIMER [0..4]
NVIC
UICR
RAM3
FICR
RAM1RAM2
RAM0
SW-DP
slave
slave
slave
CCM
Flash
EasyDMA
EasyDMA
EasyDMA master
master
AAR
EasyDMA
master
slave
SPIM [0..2]
QDEC
SAADC
GPIOTE
GPIO P0
(P0.0 – P0.31)
AIN0 AIN7
SCK
MISO
LED
A
BUARTE [0]
TWIM [0..1]
SCL
SDA
RAM4RAM6
RAM5RAM7
slave
slave
slave
SPIS [0..2] MOSI
MISO
CSN
COMP
EasyDMA
slave
RXD
TXD
CTS
RTS
slave
ETM
SysTick
TPIU
TP
master
master
EasyDMA
EasyDMA
EasyDMA
MOSI
LPCOMP
EasyDMA
TWIS [0..1]
SCL
SDA
EasyDMA
master
master
master
master
master
NFCT
NFC1
NFC2
EasyDMA master
master
SWDIO
SWCLK
CTRL-AP
PWM[0..3]
OUT0 – OUT3
I2S
MCK
LRCK
SCL
SDOUT
SDIN
PDM
CLK
DIN
SCK
EasyDMA master
EasyDMA master
EasyDMA master
I-Cache
slave
slave
slave
slave
slave
master
Figure 1: Block diagram
4 Pin assignments
Page 13
4 Pin assignments
Here we cover the pin assignments for each variant of the chip.
4.1 QFN48 pin assignments
DEC1
nRF5102
QFN48
P0.05/AIN3
1
2
3
4
5
6
7
8
9
10
11
12
17
18
19
20
13
14
15
16
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
P0.07
P0.00/XL1
NFC2/P0.10
P0.01/XL2
P0.08
VDD
P0.13
P0.15/TRACEDATA[2]
P0.16/TRACEDATA[1]
P0.19
VDD
DEC3
DEC2
VSS
ANT
P0.23
P0.22
SWDCLK
DEC4
VSS
NC
P0.31/AIN7
P0.25
P0.26
P0.04/AIN2
P0.06
NFC1/P0.09
P0.14/TRACEDATA[3]
P0.17
P0.18/TRACEDATA[0]/SWO
P0.11
SWDIO
P0.27
DCC
VDD
P0.28/AIN4
P0.29/AIN5
exposed die pad
N52832
QFN48
P0.12
XC1
XC2
P0.30/AIN6
P0.21/nRESET
P0.24
P0.02/AIN0
P0.03/AIN1
P0.20/TRACECLK
Figure 2: QFN48 pin assignments, top view
Table 3: QFN48 pin assignments
Pin Name Type Description
Left Side of chip
1 DEC1 Power 0.9 V regulator digital supply decoupling
2 P0.00
XL1
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal (LFXO)
3 P0.01
XL2
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal (LFXO)
4 P0.02
AIN0
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
5 P0.03
AIN1
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
6 P0.04
AIN2
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
7 P0.05
AIN3
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
8 P0.06 Digital I/O General purpose I/O
9 P0.07 Digital I/O General purpose I/O
4 Pin assignments
Page 14
Pin Name Type Description
10 P0.08 Digital I/O General purpose I/O
11 NFC1
P0.09
NFC input
Digital I/O
NFC antenna connection
General purpose I/O1
12 NFC2
P0.10
NFC input
Digital I/O
NFC antenna connection
General purpose I/O1
Bottom side of chip
13 VDD Power Power supply
14 P0.11 Digital I/O General purpose I/O
15 P0.12 Digital I/O General purpose I/O
16 P0.13 Digital I/O General purpose I/O
17 P0.14
TRACEDATA[3]
Digital I/O General purpose I/O
Trace port output
18 P0.15
TRACEDATA[2]
Digital I/O General purpose I/O
Trace port output
19 P0.16
TRACEDATA[1]
Digital I/O General purpose I/O
Trace port output
20 P0.17 Digital I/O General purpose I/O
21 P0.18
TRACEDATA[0] / SWO
Digital I/O General purpose I/O
Single wire output
Trace port output
22 P0.19 Digital I/O General purpose I/O
23 P0.20
TRACECLK
Digital I/O General purpose I/O
Trace port clock output
24 P0.21
nRESET
Digital I/O General purpose I/O
Configurable as pin reset
Right Side of chip
25 SWDCLK Digital input Serial wire debug clock input for debug
and programming
26 SWDIO Digital I/O Serial wire debug I/O for debug and
programming
27 P0.22 Digital I/O General purpose I/O2
28 P0.23 Digital I/O General purpose I/O2
29 P0.24 Digital I/O General purpose I/O2
30 ANT RF Single-ended radio antenna connection
31 VSS Power Ground (Radio supply)
32 DEC2 Power 1.3 V regulator supply decoupling (Radio
supply)
33 DEC3 Power Power supply decoupling
34 XC1 Analog input Connection for 32 MHz crystal
35 XC2 Analog input Connection for 32 MHz crystal
36 VDD Power Power supply
Top side of chip
37 P0.25 Digital I/O General purpose I/O2
38 P0.26 Digital I/O General purpose I/O2
39 P0.27 Digital I/O General purpose I/O2
40 P0.28
AIN4
Digital I/O
Analog input
General purpose I/O2
SAADC/COMP/LPCOMP input
41 P0.29
AIN5
Digital I/O
Analog input
General purpose I/O2
SAADC/COMP/LPCOMP input
42 P0.30
AIN6
Digital I/O
Analog input
General purpose I/O2
SAADC/COMP/LPCOMP input
43 P0.31
AIN7
Digital I/O
Analog input
General purpose I/O pin2
SAADC/COMP/LPCOMP input
4 Pin assignments
Page 15
Pin Name Type Description
44 NC No connect
Leave unconnected
45 VSS Power Ground
46 DEC4 Power 1.3 V regulator supply decoupling
Input from DC/DC regulator
Output from 1.3 V LDO
47 DCC Power DC/DC regulator output
48 VDD Power Power supply
Bottom of chip
Die pad VSS Power Ground pad
Exposed die pad must be connected
to ground (VSS) for proper device
operation.
4.2 WLCSP ball assignments
654321 7
A
B
C
D
E
F
G
H
N52832
CIAAHP
YYWWLL
Figure 3: WLCSP ball assignments, top view
Table 4: WLCSP ball assignments
Ball Name Description
A1 XC2 Analog input Connection for 32 MHz crystal
A2 DEC2 Power 1.3 V regulator supply decoupling (Radio
supply)
A3 P0.28
AIN4
Digital I/O
Analog input
General purpose I/O3
SAADC/COMP/LPCOMP input
A4 P0.29
AIN5
Digital I/O
Analog input
General purpose I/O3
SAADC/COMP/LPCOMP input
A5 P0.30
AIN6
Digital I/O
Analog input
General purpose I/O3
SAADC/COMP/LPCOMP input
A6 DEC4 Power 1.3 V regulator supply decoupling
Input from DC/DC converter. Output
from 1.3 V LDO
A7 VDD Power Power supply
B2 XC1 Analog input Connection for 32 MHz crystal
B3 P0.25 Digital I/O General purpose I/O3
1See GPIO located near the radio on page 17 for more information.
2See NFC antenna pins on page 17 for more information.
4 Pin assignments
Page 16
Ball Name Description
B4 P0.27 Digital I/O General purpose I/O3
B5 P0.31
AIN7
Digital I/O
Analog input
General purpose I/O3
SAADC/COMP/LPCOMP input
B6 DCC Power DC/DC converter output
B7 DEC1 Power 0.9 V regulator digital supply decoupling
C2 DEC3 Power Power supply decoupling
C3 NC N/A Not connected
C4 VSS Power Ground
C5 VSS Power Ground
C6 P0.02
AIN0
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
C7 P0.01
XL2
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal (LFXO)
D1 ANT RF Single-ended radio antenna connection
D2 VSS_PA Power Ground (Radio supply)
D3 P0.26 Digital I/O General purpose I/O 3
D6 P0.03
AIN1
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
D7 P0.00
XL1
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal (LFXO)
E1 P0.24 Digital I/O General purpose I/O3
E2 P0.23 Digital I/O General purpose I/O3
E3 VSS Power Ground
E6 P0.04
AIN2
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
E7 P0.05
AIN3
Digital I/O
Analog input
General purpose I/O
SAADC/COMP/LPCOMP input
F1 SWDCLK Digital input Serial wire debug clock input for debug
and programming
F2 P0.22 Digital I/O General purpose I/O3
F3 P0.19 Digital I/O General purpose I/O
F4 P0.11 Digital I/O General purpose I/O
F5 VSS Power Ground
F6 P0.07 Digital I/O General purpose I/O
F7 P0.06 Digital I/O General purpose I/O
G1 SWDIO Digital I/O Serial wire debug I/O for debug and
programming
G2 P0.20
TRACECLK
Digital I/O General purpose I/O
Trace port clock output
G3 P0.17 Digital I/O General purpose I/O
G4 P0.13 Digital I/O General purpose I/O
G5 NFC2
P0.10
NFC input
Digital I/O
NFC antenna connection
General purpose I/O4
G6 NFC1
P0.09
NFC input
Digital I/O
NFC antenna connection
General purpose I/O4
G7 P0.08 Digital I/O General purpose I/O
H1 P0.21
nRESET
Digital I/O General purpose I/O
Configurable as pin reset
H2 P0.18
TRACEDATA[0]
Digital I/O General purpose I/O
Trace port output
H3 P0.16
TRACEDATA[1]
Digital I/O General purpose I/O
Trace port output
H4 P0.15 Digital I/O General purpose I/O
4 Pin assignments
Page 17
Ball Name Description
TRACEDATA[2] Trace port output
H5 P0.14
TRACEDATA[3]
Digital I/O General purpose I/O
Trace port output
H6 P0.12 Digital I/O General purpose I/O
H7 VDD Power Power supply
4.3 GPIO usage restrictions
4.3.1 GPIO located near the radio
Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large
sink/source current close to the Radio power supply and antenna pins.
Table 5: GPIO recommended usage for QFN48 package on page 17 and Table 6: GPIO recommended
usage for WLCSP package on page 17 identify some GPIO that have recommended usage guidelines to
maximize radio performance in an application.
Table 5: GPIO recommended usage for QFN48 package
Pin GPIO Recommended usage
27 P0.22
28 P0.23
29 P0.24
37 P0.25
38 P0.26
39 P0.27
40 P0.28
41 P0.29
42 P0.30
43 P0.31
Low drive, low frequency I/O only.
Table 6: GPIO recommended usage for WLCSP package
Pin GPIO Recommended usage
F2 P0.22
E2 P0.23
E1 P0.24
B3 P0.25
D3 P0.26
B4 P0.27
A3 P0.28
A4 P0.29
A5 P0.30
B5 P0.31
Low drive, low frequency I/O only.
4.3.2 NFC antenna pins
Two physical pins can be configured either as NFC antenna pins (factory default), or as GPIOs, as shown
below.
Table 7: GPIO pins used by NFC
NFC pad name GPIO
NFC1 P0.09
NFC2 P0.10
When configured as NFC antenna pins, the GPIOs on those pins will automatically be set to DISABLE state
and a protection circuit will be enabled preventing the chip from being damaged in the presence of a strong
NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2
V.
3See GPIO located near the radio on page 17 for more information.
4See NFC antenna pins on page 17 for more information.
4 Pin assignments
Page 18
For information on how to configure these pins as normal GPIOs, see NFCT — Near field communication tag
on page 416 and UICR — User information configuration registers on page 54. Note that the device will
not be protected against strong NFC field damage if the pins are configured as GPIO and an NFC antenna
is connected to the device. The pins will always be configured as NFC pins during power-on reset until the
configuration is set according to the UICR register.
These two pins will have some limitations when configured as GPIO. The pin capacitance will be higher on
these pins, and there is some current leakage between the two pins if they are driven to different logical
values. To avoid leakage between the pins when configured as GPIO, these GPIOs should always be at the
same logical value whenever entering one of the device power saving modes. See Electrical specification.
5 Absolute maximum ratings
Page 19
5 Absolute maximum ratings
Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time
without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may
affect the reliability of the device.
Table 8: Absolute maximum ratings
Min. Max. Unit
Supply voltages
VDD -0.3 +3.9 V
VSS 0 V
I/O pin voltage
VI/O, VDD ≤3.6 V -0.3 VDD + 0.3 V V
VI/O, VDD >3.6 V -0.3 3.9 V V
NFC antenna pin current
INFC1/2 80 mA
Radio
RF input level 10 dBm
Environmental QFN48, 6×6 mm package
Storage temperature -40 +125 °C
MSL (moisture sensitivity level) 2
ESD HBM (human body model) 4 kV
ESD CDM (charged device model) 1000 V
Environmental WLCSP, 3.0×3.2 mm package
Storage temperature -40 +125 °C
MSL 1
ESD HBM 2 kV
ESD CDM 500 V
Flash memory
Endurance 10 000 Write/erase cycles
Retention 10 years at 40°C
6 Recommended operating conditions
Page 20
6 Recommended operating conditions
The operating conditions are the physical parameters that the chip can operate within.
Table 9: Recommended operating conditions
Symbol Parameter Notes Min. Nom. Max. Units
VDD Supply voltage, independent of DCDC enable 1.7 3.0 3.6 V
tR_VDD Supply rise time (0 V to 1.7 V) 60 ms
TA Operating temperature -40 25 85 °C
Important: The on-chip power-on reset circuitry may not function properly for rise times longer than
the specified maximum.
6.1 WLCSP light sensitivity
All WLCSP package variants are sensitive to visible and close-range infrared light. This means that a final
product design must shield the chip properly, either by final product encapsulation or by shielding/coating of
the WLCSP device.
7 CPU
Page 21
7 CPU
The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2
technology) that implements a superset of 16 and 32-bit instructions to maximize code density and
performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing including:
Digital signal processing (DSP) instructions
Single-cycle multiply and accumulate (MAC) instructions
Hardware divide
8 and 16-bit single instruction multiple data (SIMD) instructions
Single-precision floating-point unit (FPU)
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 Series. An instruction cache can be
enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache
on page 30. The section Electrical specification on page 21 shows CPU performance parameters
including wait states in different modes, CPU current and efficiency, and processing power and efficiency
based on the CoreMark® benchmark.
7.1 Floating point interrupt
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow. These
exceptions will trigger the FPU interrupt (see Instantiation on page 24). To clear the IRQ line when an
exception has occurred, the relevant exception bit within the FPSCR register needs to be cleared. For more
information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
7.2 Electrical specification
7.2.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol Description Min. Typ. Max. Units
WFLASH CPU wait states, running from flash, cache disabled 0 2
WFLASHCACHE CPU wait states, running from flash, cache enabled 0 3
WRAM CPU wait states, running from RAM 0
IDDFLASHCACHE CPU current, running from flash, cache enabled, LDO 7.4 mA
IDDFLASHCACHEDCDC CPU current, running from flash, cache enabled, DCDC 3V 3.7 mA
IDDFLASH CPU current, running from flash, cache disabled, LDO 8.0 mA
IDDFLASHDCDC CPU current, running from flash, cache disabled, DCDC 3V 3.9 mA
IDDRAM CPU current, running from RAM, LDO 6.7 mA
IDDRAMDCDC CPU current, running from RAM, DCDC 3V 3.3 mA
IDDFLASH/MHz CPU efficiency, running from flash, cache enabled, LDO 125 µA/
MHz
IDDFLASHDCDC/MHz CPU efficiency, running from flash, cache enabled, DCDC 3V 58 µA/
MHz
7 CPU
Page 22
Symbol Description Min. Typ. Max. Units
CMFLASH CoreMark5, running from flash, cache enabled 215 CoreMark
CMFLASH/MHz CoreMark per MHz, running from flash, cache enabled 3.36 CoreMark/
MHz
CMFLASH/mA CoreMark per mA, running from flash, cache enabled, DCDC 3V 58 CoreMark/
mA
7.3 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
Option / Module Description Implemented
Core options
NVIC Nested Vector Interrupt Controller 37 vectors
PRIORITIES Priority bits 3
WIC Wakeup Interrupt Controller NO
Endianness Memory system endianness Little endian
Bit Banding Bit banded memory NO
DWT Data Watchpoint and Trace YES
SysTick System tick timer YES
Modules
MPU Memory protection unit YES
FPU Floating point unit YES
DAP Debug Access Port YES
ETM Embedded Trace Macrocell YES
ITM Instrumentation Trace Macrocell YES
TPIU Trace Port Interface Unit YES
ETB Embedded Trace Buffer NO
FPB Flash Patch and Breakpoint Unit YES
HTM AHB Trace Macrocell NO
5Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs --no_size_constraints
8 Memory
Page 23
8 Memory
The nRF52832 contains flash and RAM that can be used for code and data storage.
The amount of RAM and flash will vary depending on variant, see Table 10: Memory variants on page 23.
Table 10: Memory variants
Device name RAM Flash Comments
nRF52832-QFAA 64 kB 512 kB
nRF52832-QFAB 32 kB 256 kB
nRF52832-CIAA 64 kB 512 kB
The CPU and the EasyDMA can access memory via the AHB multilayer interconnect. The CPU is also able
to access peripherals via the AHB multilayer interconnect, as illustrated in Figure 4: Memory layout on page
23.
0x2000 0000
0x2100 1000
0x2000 2000
0x2000 3000
0x2000 4000
0x2000 5000
0x2000 6000
0x2000 7000
RAM3
AHB slave
RAM2
AHB slave
RAM1
AHB slave
RAM0
AHB slave
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
0x2000 8000
0x2000 9000
0x2000 A000
0x2000 B000
0x2000 C000
0x2000 D000
0x2000 E000
0x2000 F000
RAM7
AHB slave
RAM6
AHB slave
RAM5
AHB slave
RAM4
AHB slave
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
AHB multilayer interconnect
Data RAM
System
AHB
slave
Page 0
Page 1
Page 2
Page 3..126
Page 127
0x0000 0000
0x0000 2000
0x0000 3000
0x0007 F000
Flash
ICODE/DCODE
AHB
slave
NVMC
ICODE
DCODE
0x0080 0000
0x0080 1000
0x0080 2000
0x0080 3000
0x0080 4000
0x0080 5000
0x0080 6000
0x0080 7000
0x0080 8000
0x0080 9000
0x0080 A000
0x0080 B000
0x0080 C000
0x0080 D000
0x0080 E000
0x0080 F000
Code RAM
ICODE/DCODE
Peripheral
EasyDMA
DMA bus
Peripheral
EasyDMA
DMA bus
CPU
ARM Cortex-M4
System bus
ICODE
DCODE
AHB2APB
AHB
APB
Block 0
Block 1
Block 2..6
Block 7
0x0000 0200
0x0000 0400
0x0000 1000
0x0000 0E00
I-Cache
Figure 4: Memory layout
See AHB multilayer on page 26 and EasyDMA on page 27 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
8.1 RAM - Random access memory
The RAM interface is divided into multiple RAM AHB slaves.
Each RAM AHB slave is connected to two 4-kilobyte RAM sections, see Section 0 and Section 1 in Figure 4:
Memory layout on page 23.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 78).
8 Memory
Page 24
8.2 Flash - Non-volatile memory
The Flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased and also on how it can be written.
Writing to Flash is managed by the Non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 29.
The Flash is divided into multiple pages that can be accessed by the CPU via both the ICODE and DCODE
buses as shown in, Figure 4: Memory layout on page 23. Each page is divided into 8 blocks.
8.3 Memory map
The complete memory map is shown in Figure 5: Memory map on page 24. As described in Memory on
page 23, Code RAM and the Data RAM are the same physical RAM.
Flash 0x2000 0000
0x0000 0000
0x1000 0000
Private Peripheral Bus - Internal
Data RAM
0xA000 0000
Cortex M4 System Address Map nRF52832 Address Map
FICR
0x4000 0000
APB peripherals
AHB peripherals 0x5000 0000
UICR
0x1000 1000
External device
External RAM
Peripheral
SRAM
Code
0x0080 0000
0xFFFF FFFF
Private Peripheral Bus - External
System
ROM Table
External PPB
ETM
TPIU
0xE004 0000
0xE004 1000
0xE004 2000
0xE0FF 0000
0xE010 0000
DWT
ITM
0xE000 0000
0xE000 1000
0xE000 2000
0xE000 F000
FPB
SCS
0xE000 3000
0xE000 E000 1.0GB
1.0GB
0.5GB
0.5GB
0.5GB
Reserved
Reserved
nRF52832 Address Map
Reserved
Reserved
0x6000 0000
Reserved
0x2001 0000
0x4000 0000
0xE004 0000
Reserved
Code RAM
0x0008 0000
Reserved
Reserved
Reserved
0x2000 0000
0x0081 0000
Figure 5: Memory map
8.4 Instantiation
Table 11: Instantiation table
ID Base Address Peripheral Instance Description
0 0x40000000 CLOCK CLOCK Clock control
0 0x40000000 POWER POWER Power control
0 0x40000000 BPROT BPROT Block Protect
1 0x40001000 RADIO RADIO 2.4 GHz radio
2 0x40002000 UARTE UARTE0 Universal Asynchronous Receiver/Transmitter with EasyDMA
2 0x40002000 UART UART0 Universal Asynchronous Receiver/Transmitter Deprecated
3 0x40003000 SPIM SPIM0 SPI master 0
3 0x40003000 SPIS SPIS0 SPI slave 0
3 0x40003000 TWIM TWIM0 Two-wire interface master 0
3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated
3 0x40003000 SPI SPI0 SPI master 0 Deprecated
8 Memory
Page 25
ID Base Address Peripheral Instance Description
3 0x40003000 TWIS TWIS0 Two-wire interface slave 0
4 0x40004000 SPIM SPIM1 SPI master 1
4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated
4 0x40004000 SPIS SPIS1 SPI slave 1
4 0x40004000 TWIS TWIS1 Two-wire interface slave 1
4 0x40004000 TWIM TWIM1 Two-wire interface master 1
4 0x40004000 SPI SPI1 SPI master 1 Deprecated
5 0x40005000 NFCT NFCT Near Field Communication Tag
6 0x40006000 GPIOTE GPIOTE GPIO Tasks and Events
7 0x40007000 SAADC SAADC Analog to digital converter
8 0x40008000 TIMER TIMER0 Timer 0
9 0x40009000 TIMER TIMER1 Timer 1
10 0x4000A000 TIMER TIMER2 Timer 2
11 0x4000B000 RTC RTC0 Real-time counter 0
12 0x4000C000 TEMP TEMP Temperature sensor
13 0x4000D000 RNG RNG Random number generator
14 0x4000E000 ECB ECB AES Electronic Code Book (ECB) mode block encryption
15 0x4000F000 CCM CCM AES CCM Mode Encryption
15 0x4000F000 AAR AAR Acelerated Address Resolver
16 0x40010000 WDT WDT Watchdog timer
17 0x40011000 RTC RTC1 Real-time counter 1
18 0x40012000 QDEC QDEC Quadrature decoder
19 0x40013000 LPCOMP LPCOMP Low power comparator
19 0x40013000 COMP COMP General purpose comparator
20 0x40014000 SWI SWI0 Software interrupt 0
20 0x40014000 EGU EGU0 Event Generator Unit 0
21 0x40015000 EGU EGU1 Event Generator Unit 1
21 0x40015000 SWI SWI1 Software interrupt 1
22 0x40016000 SWI SWI2 Software interrupt 2
22 0x40016000 EGU EGU2 Event Generator Unit 2
23 0x40017000 SWI SWI3 Software interrupt 3
23 0x40017000 EGU EGU3 Event Generator Unit 3
24 0x40018000 EGU EGU4 Event Generator Unit 4
24 0x40018000 SWI SWI4 Software interrupt 4
25 0x40019000 SWI SWI5 Software interrupt 5
25 0x40019000 EGU EGU5 Event Generator Unit 5
26 0x4001A000 TIMER TIMER3 Timer 3
27 0x4001B000 TIMER TIMER4 Timer 4
28 0x4001C000 PWM PWM0 Pulse Width Modulation Unit 0
29 0x4001D000 PDM PDM Pulse Density Modulation (Digital Microphone Interface)
30 0x4001E000 NVMC NVMC Non-Volatile Memory Controller
31 0x4001F000 PPI PPI Programmable Peripheral Interconnect
32 0x40020000 MWU MWU Memory Watch Unit
33 0x40021000 PWM PWM1 Pulse Width Modulation Unit 1
34 0x40022000 PWM PWM2 Pulse Width Modulation Unit 2
35 0x40023000 SPI SPI2 SPI master 2 Deprecated
35 0x40023000 SPIS SPIS2 SPI slave 2
35 0x40023000 SPIM SPIM2 SPI master 2
36 0x40024000 RTC RTC2 Real-time counter 2
37 0x40025000 I2S I2S Inter-IC Sound Interface
38 0x40026000 FPU FPU FPU interrupt
0 0x50000000 GPIO GPIO General purpose input and output Deprecated
0 0x50000000 GPIO P0 General purpose input and output
N/A 0x10000000 FICR FICR Factory Information Configuration
N/A 0x10001000 UICR UICR User Information Configuration
9 AHB multilayer
Page 26
9 AHB multilayer
The CPU and all of the EasyDMAs are AHB bus masters on the AHB multilayer, while the RAM and various
other modules are AHB slaves.
See Block diagram on page 12 for an overview of which peripherals implement EasyDMA.
The CPU has exclusive access to all AHB slaves except for the RAM that can also be accessed by the
EasyDMA.
Access rights to each of the RAM AHB slaves are resolved using the priority of the different bus masters in
the system
See AHB multilayer priorities on page 26 for information about the priority of the different AHB bus
masters in the system. It is possible for two or more bus masters to have the same priority in cases where
it is guaranteed by design that the related masters will never be able to access the same slave at the same
time.
9.1 AHB multilayer priorities
Each master connected to the AHB multilayer is assigned a priority.
Table 12: AHB bus masters
Bus master name Priority Description
CPU Highest priority
SPIS1 Applies to SPIM1, SPIS1, TWIM1, TWIS1
RADIO
CCM/ECB/AAR
SAADC
UARTE
SERIAL0 Applies to SPIM0, SPIS0, TWIM0, TWIS0
SERIAL2 Applies to SPIM2, SPIS2
NFCT
I2S I2S
PDM PDM
PWM Lowest priority Applies to PWM0, PWM1, PWM2
10 EasyDMA
Page 27
10 EasyDMA
EasyDMA is an easy-to-use direct memory access module that some peripherals implement to gain direct
access to Data RAM.
The EasyDMA is an AHB bus master similar to the CPU and it is connected to the AHB multilayer
interconnect for direct access to the Data RAM. The EasyDMA is not able to access the Flash.
A peripheral can implement multiple EasyDMA instances, for example to provide a dedicated channel for
reading data from RAM into the peripheral at the same time as a second channel is dedicated for writing data
to the RAM from the peripheral. This concept is illustrated in Figure 6: EasyDMA example on page 27
Peripheral
READER
Peripheral
Core
AHB Multilayer
AHB
WRITER
AHB
RAM
RAM
RAM
EasyDMA
EasyDMA
Figure 6: EasyDMA example
An EasyDMA channel is usually exposed to the user in the form illustrated below, but some variations may
occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels, one
for reading, called READER, and one for writing, called WRITER. When the peripheral is started, it is here
assumed that the peripheral will read 5 bytes from the readerBuffer located in RAM at address 0x20000000,
process the data and then write no more than 6 bytes back to the writerBuffer located in RAM at address
0x20000005. The memory layout of these buffers is illustrated in Figure 7: EasyDMA memory layout on page
28.
10 EasyDMA
Page 28
readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3]
readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2]
writerBuffer[3] writerBuffer[4] writerBuffer[5]
0x20000000
0x20000004
0x20000008
Figure 7: EasyDMA memory layout
The EasyDMA channel's MAXCNT register cannot be specified larger than the actual size of the buffer. If,
for example, the WRITER.MAXCNT register is specified larger than the size of the writerBuffer, the WRITER
EasyDMA channel may overflow the writerBuffer.
After the peripheral has completed the EasyDMA transfer, the CPU can read the EasyDMA channel's
AMOUNT register to see how many bytes that were transferred, e.g. it is possible for the CPU to read the
MYPERIPHERAL->WRITER.AMOUNT register to see how many bytes the WRITER wrote to RAM.
10.1 EasyDMA array list
The EasyDMA is able to operate in a mode called array list.
The EasyDMA array list can be represented by the data structure ArrayList_type illustrated in the code
example below.
This data structure includes only a buffer with size equal to READER.MAXCNT. EasyDMA will use the
READER.MAXCNT register to determine when the buffer is full.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
#define BUFFER_SIZE 4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3];
READER.MAXCNT = BUFFER_SIZE;
READER.PTR = &ReaderList;
buffer[0] buffer[1]0x20000000 : ReaderList[0]
0x20000004 : ReaderList[1]
0x20000008 : ReaderList[2]
buffer[2] buffer[3]
READER.PTR = &ReaderList
buffer[0] buffer[1] buffer[2] buffer[3]
buffer[0] buffer[1] buffer[2] buffer[3]
Figure 8: EasyDMA array list
11 NVMC — Non-volatile memory controller
Page 29
11 NVMC — Non-volatile memory controller
The Non-volatile memory controller (NVMC) is used for writing and erasing the internal Flash memory and
the UICR.
Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before
an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page
31. The user must make sure that writing and erasing are not enabled at the same time. Failing to do so
may result in unpredictable behavior.
11.1 Writing to Flash
When writing is enabled, the Flash is written by writing a full 32-bit word to a word-aligned address in the
Flash.
The NVMC is only able to write '0' to bits in the Flash that are erased, that is, set to '1'. It cannot write back a
bit to '1'.
As illustrated in Memory on page 23, the Flash is divided into multiple pages that are further divided into
multiple blocks. The same block in the Flash can only be written nWRITE number of times before an erase
must be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory on
page 23 for block size.
Only full 32-bit words can be written to Flash using the NVMC interface. To write less than 32 bits to Flash,
write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that the
restriction about the number of writes (see above) still applies in this case.
The time it takes to write a word to the Flash is specified by tWRITE. The CPU is halted while the NVMC is
writing to the Flash.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
11.2 Erasing a page in Flash
When erase is enabled, the Flash can be erased page by page using the ERASEPAGE register.
After erasing a Flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by
tERASEPAGE. The CPU is halted while the NVMC performs the erase operation.
11.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as Flash. After UICR has been
written, the new UICR configuration will only take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or
ERASEALL.
The time it takes to write a word to the UICR is specified by tWRITE. The CPU is halted while the NVMC is
writing to the UICR.
11.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR register.
After erasing UICR all bits in UICR are set to '1'. The time it takes to erase UICR is specified by tERASEPAGE.
The CPU is halted while the NVMC performs the erase operation.
11 NVMC — Non-volatile memory controller
Page 30
11.5 Erase all
When erase is enabled, the whole Flash and UICR can be erased in one operation by using the ERASEALL
register. ERASEALL will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted while the
NVMC performs the erase operation.
11.6 Cache
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See the Memory map in Memory map on page 24 for the location of Flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states
for a cache miss, where the instruction is not available in the cache and needs to be fetched from Flash,
depends on the processor frequency and is shown in CPU on page 21
Enabling the cache can increase CPU performance and reduce power consumption by reducing the number
of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some
current when enabled. If the reduction in average current due to reduced flash accesses is larger than the
cache power requirement, the average current to execute the program code will reduce.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the
ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every
instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after
reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get
correct numbers.
11.7 Registers
Table 13: Instances
Base address Peripheral Instance Description Configuration
0x4001E000 NVMC NVMC Non-Volatile Memory Controller
Table 14: Register Overview
Register Offset Description
READY 0x400 Ready flag
CONFIG 0x504 Configuration register
ERASEPAGE 0x508 Register for erasing a page in Code area
ERASEPCR1 0x508 Register for erasing a page in Code area. Equivalent to ERASEPAGE. Deprecated
ERASEALL 0x50C Register for erasing all non-volatile user memory
ERASEPCR0 0x510 Register for erasing a page in Code area. Equivalent to ERASEPAGE. Deprecated
ERASEUICR 0x514 Register for erasing User Information Configuration Registers
ICACHECNF 0x540 I-Code cache configuration register.
IHIT 0x548 I-Code cache hit counter.
IMISS 0x54C I-Code cache miss counter.
11.7.1 READY
Address offset: 0x400
Ready flag
11 NVMC — Non-volatile memory controller
Page 31
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A R READY NVMC is ready or busy
Busy 0 NVMC is busy (on-going write or erase operation)
Ready 1 NVMC is ready
11.7.2 CONFIG
Address offset: 0x504
Configuration register
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW WEN Program memory access mode. It is strongly recommended
to only activate erase and write modes when they are actively
used. Enabling write or erase will invalidate the cache and keep
it invalidated.
Ren 0 Read only access
Wen 1 Write Enabled
Een 2 Erase enabled
11.7.3 ERASEPAGE
Address offset: 0x508
Register for erasing a page in Code area
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEPAGE Register for starting erase of a page in Code area
The value is the address to the page to be erased. (Addresses of
first word in page). Note that code erase has to be enabled by
CONFIG.EEN before the page can be erased. Attempts to erase
pages that are outside the code area may result in undesirable
behaviour, e.g. the wrong page may be erased.
11.7.4 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEPCR1 Register for erasing a page in Code area. Equivalent to
ERASEPAGE.
11.7.5 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
11 NVMC — Non-volatile memory controller
Page 32
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEALL Erase all non-volatile memory including UICR registers. Note
that code erase has to be enabled by CONFIG.EEN before the
UICR can be erased.
NoOperation 0 No operation
Erase 1 Start chip erase
11.7.6 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEPCR0 Register for starting erase of a page in Code area. Equivalent to
ERASEPAGE.
11.7.7 ERASEUICR
Address offset: 0x514
Register for erasing User Information Configuration Registers
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEUICR Register starting erase of all User Information Configuration
Registers. Note that code erase has to be enabled by
CONFIG.EEN before the UICR can be erased.
NoOperation 0 No operation
Erase 1 Start erase of UICR
11.7.8 ICACHECNF
Address offset: 0x540
I-Code cache configuration register.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW CACHEEN Cache enable
Disabled 0 Disable cache. Invalidates all cache entries.
Enabled 1 Enable cache
B RW CACHEPROFEN Cache profiling enable
Disabled 0 Disable cache profiling
Enabled 1 Enable cache profiling
11.7.9 IHIT
Address offset: 0x548
I-Code cache hit counter.
11 NVMC — Non-volatile memory controller
Page 33
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW HITS Number of cache hits
11.7.10 IMISS
Address offset: 0x54C
I-Code cache miss counter.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW MISSES Number of cache misses
11.8 Electrical specification
11.8.1 Flash programming
Symbol Description Min. Typ. Max. Units
nWRITE,BLOCK Amount of writes allowed in a block between erase 181
tWRITE Time to write one word 67.5 338 µs
tERASEPAGE Time to erase one page 2.05 89.7 ms
tERASEALL Time to erase all flash 6.72 295.3 ms
11.8.2 Cache size
Symbol Description Min. Typ. Max. Units
SizeICODE I-Code cache size 2048 Bytes
12 BPROT — Block protection
Page 34
12 BPROT — Block protection
The mechanism for protecting non-volatile memory can be used to prevent application code from erasing or
writing to protected blocks.
Non-volatile memory can be protected from erases and writes depending on the settings in the CONFIG
registers. One bit in a CONFIG register represents one protected block of 4 kB. There are four CONFIG
registers of 32 bits, which means there are 128 protectable blocks in total.
Important: If an erase or write to a protected block is detected, the CPU will hard fault. If an
ERASEALL operation is attempted from the CPU while any block is protected, it will be blocked and
the CPU will hard fault.
On reset, all the protection bits are cleared. To ensure safe operation, the first task after reset must be to set
the protection bits. The only way of clearing protection bits is by resetting the device from any reset source.
The protection mechanism is turned off when in debug interface mode (a debugger is connected) and the
DISABLEINDEBUG register is set to disable. For more information, see Debug and trace on page 72.
...
0
1
2
127
126
125
Program Memory
0x00000000
0CONFIG[0]
l
31
0CONFIG[3]
l
31
Figure 9: Protected regions of program memory
12.1 Registers
Table 15: Instances
Base address Peripheral Instance Description Configuration
0x40000000 BPROT BPROT Block Protect
Table 16: Register Overview
Register Offset Description
CONFIG0 0x600 Block protect configuration register 0
CONFIG1 0x604 Block protect configuration register 1
DISABLEINDEBUG 0x608 Disable protection mechanism in debug interface mode
0x60C Reserved
CONFIG2 0x610 Block protect configuration register 2
CONFIG3 0x614 Block protect configuration register 3
12 BPROT — Block protection
Page 35
12.1.1 CONFIG0
Address offset: 0x600
Block protect configuration register 0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW REGION0 Enable protection for region 0. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
B RW REGION1 Enable protection for region 1. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
C RW REGION2 Enable protection for region 2. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
D RW REGION3 Enable protection for region 3. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
E RW REGION4 Enable protection for region 4. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
F RW REGION5 Enable protection for region 5. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
G RW REGION6 Enable protection for region 6. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
H RW REGION7 Enable protection for region 7. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
I RW REGION8 Enable protection for region 8. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
J RW REGION9 Enable protection for region 9. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
K RW REGION10 Enable protection for region 10. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
L RW REGION11 Enable protection for region 11. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
M RW REGION12 Enable protection for region 12. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
N RW REGION13 Enable protection for region 13. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
O RW REGION14 Enable protection for region 14. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
P RW REGION15 Enable protection for region 15. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
Q RW REGION16 Enable protection for region 16. Write '0' has no effect.
Disabled 0 Protection disabled
12 BPROT — Block protection
Page 36
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
Enabled 1 Protection enable
R RW REGION17 Enable protection for region 17. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
S RW REGION18 Enable protection for region 18. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
T RW REGION19 Enable protection for region 19. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
U RW REGION20 Enable protection for region 20. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
V RW REGION21 Enable protection for region 21. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
W RW REGION22 Enable protection for region 22. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
X RW REGION23 Enable protection for region 23. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
Y RW REGION24 Enable protection for region 24. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
Z RW REGION25 Enable protection for region 25. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
a RW REGION26 Enable protection for region 26. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
b RW REGION27 Enable protection for region 27. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
c RW REGION28 Enable protection for region 28. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
d RW REGION29 Enable protection for region 29. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
e RW REGION30 Enable protection for region 30. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
f RW REGION31 Enable protection for region 31. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enable
12.1.2 CONFIG1
Address offset: 0x604
Block protect configuration register 1
12 BPROT — Block protection
Page 37
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW REGION32 Enable protection for region 32. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
B RW REGION33 Enable protection for region 33. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
C RW REGION34 Enable protection for region 34. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
D RW REGION35 Enable protection for region 35. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
E RW REGION36 Enable protection for region 36. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
F RW REGION37 Enable protection for region 37. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
G RW REGION38 Enable protection for region 38. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
H RW REGION39 Enable protection for region 39. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
I RW REGION40 Enable protection for region 40. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
J RW REGION41 Enable protection for region 41. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
K RW REGION42 Enable protection for region 42. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
L RW REGION43 Enable protection for region 43. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
M RW REGION44 Enable protection for region 44. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
N RW REGION45 Enable protection for region 45. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
O RW REGION46 Enable protection for region 46. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
P RW REGION47 Enable protection for region 47. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Q RW REGION48 Enable protection for region 48. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
R RW REGION49 Enable protection for region 49. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
S RW REGION50 Enable protection for region 50. Write '0' has no effect.
12 BPROT — Block protection
Page 38
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
Disabled 0 Protection disabled
Enabled 1 Protection enabled
T RW REGION51 Enable protection for region 51. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
U RW REGION52 Enable protection for region 52. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
V RW REGION53 Enable protection for region 53. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
W RW REGION54 Enable protection for region 54. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
X RW REGION55 Enable protection for region 55. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Y RW REGION56 Enable protection for region 56. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Z RW REGION57 Enable protection for region 57. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
a RW REGION58 Enable protection for region 58. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
b RW REGION59 Enable protection for region 59. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
c RW REGION60 Enable protection for region 60. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
d RW REGION61 Enable protection for region 61. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
e RW REGION62 Enable protection for region 62. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
f RW REGION63 Enable protection for region 63. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
12.1.3 DISABLEINDEBUG
Address offset: 0x608
Disable protection mechanism in debug interface mode
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000001 0 0000000000000000000000000000001
Id RW Field Value Id Value Description
A RW DISABLEINDEBUG Disable the protection mechanism for NVM regions while
in debug interface mode. This register will only disable the
protection mechanism if the device is in debug interface mode.
Disabled 1 Disable in debug
12 BPROT — Block protection
Page 39
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000001 0 0000000000000000000000000000001
Id RW Field Value Id Value Description
Enabled 0 Enable in debug
12.1.4 CONFIG2
Address offset: 0x610
Block protect configuration register 2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW REGION64 Enable protection for region 64. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
B RW REGION65 Enable protection for region 65. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
C RW REGION66 Enable protection for region 66. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
D RW REGION67 Enable protection for region 67. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
E RW REGION68 Enable protection for region 68. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
F RW REGION69 Enable protection for region 69. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
G RW REGION70 Enable protection for region 70. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
H RW REGION71 Enable protection for region 71. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
I RW REGION72 Enable protection for region 72. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
J RW REGION73 Enable protection for region 73. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
K RW REGION74 Enable protection for region 74. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
L RW REGION75 Enable protection for region 75. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
M RW REGION76 Enable protection for region 76. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
N RW REGION77 Enable protection for region 77. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
O RW REGION78 Enable protection for region 78. Write '0' has no effect.
Disabled 0 Protection disabled
12 BPROT — Block protection
Page 40
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
Enabled 1 Protection enabled
P RW REGION79 Enable protection for region 79. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Q RW REGION80 Enable protection for region 80. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
R RW REGION81 Enable protection for region 81. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
S RW REGION82 Enable protection for region 82. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
T RW REGION83 Enable protection for region 83. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
U RW REGION84 Enable protection for region 84. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
V RW REGION85 Enable protection for region 85. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
W RW REGION86 Enable protection for region 86. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
X RW REGION87 Enable protection for region 87. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Y RW REGION88 Enable protection for region 88. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Z RW REGION89 Enable protection for region 89. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
a RW REGION90 Enable protection for region 90. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
b RW REGION91 Enable protection for region 91. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
c RW REGION92 Enable protection for region 92. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
d RW REGION93 Enable protection for region 93. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
e RW REGION94 Enable protection for region 94. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
f RW REGION95 Enable protection for region 95. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
12 BPROT — Block protection
Page 41
12.1.5 CONFIG3
Address offset: 0x614
Block protect configuration register 3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW REGION96 Enable protection for region 96. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
B RW REGION97 Enable protection for region 97. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
C RW REGION98 Enable protection for region 98. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
D RW REGION99 Enable protection for region 99. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
E RW REGION100 Enable protection for region 100. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
F RW REGION101 Enable protection for region 101. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
G RW REGION102 Enable protection for region 102. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
H RW REGION103 Enable protection for region 103. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
I RW REGION104 Enable protection for region 104. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
J RW REGION105 Enable protection for region 105. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
K RW REGION106 Enable protection for region 106. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
L RW REGION107 Enable protection for region 107. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
M RW REGION108 Enable protection for region 108. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
N RW REGION109 Enable protection for region 109. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
O RW REGION110 Enable protection for region 110. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
P RW REGION111 Enable protection for region 111. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Q RW REGION112 Enable protection for region 112. Write '0' has no effect.
Disabled 0 Protection disabled
12 BPROT — Block protection
Page 42
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
Enabled 1 Protection enabled
R RW REGION113 Enable protection for region 113. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
S RW REGION114 Enable protection for region 114. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
T RW REGION115 Enable protection for region 115. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
U RW REGION116 Enable protection for region 116. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
V RW REGION117 Enable protection for region 117. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
W RW REGION118 Enable protection for region 118. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
X RW REGION119 Enable protection for region 119. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Y RW REGION120 Enable protection for region 120. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
Z RW REGION121 Enable protection for region 121. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
a RW REGION122 Enable protection for region 122. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
b RW REGION123 Enable protection for region 123. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
c RW REGION124 Enable protection for region 124. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
d RW REGION125 Enable protection for region 125. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
e RW REGION126 Enable protection for region 126. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
f RW REGION127 Enable protection for region 127. Write '0' has no effect.
Disabled 0 Protection disabled
Enabled 1 Protection enabled
13 FICR — Factory information configuration
registers
Page 43
13 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
13.1 Registers
Table 17: Instances
Base address Peripheral Instance Description Configuration
0x10000000 FICR FICR Factory Information Configuration
Table 18: Register Overview
Register Offset Description
CODEPAGESIZE 0x010 Code memory page size
CODESIZE 0x014 Code memory size
DEVICEID[0] 0x060 Device identifier
DEVICEID[1] 0x064 Device identifier
ER[0] 0x080 Encryption Root, word 0
ER[1] 0x084 Encryption Root, word 1
ER[2] 0x088 Encryption Root, word 2
ER[3] 0x08C Encryption Root, word 3
IR[0] 0x090 Identity Root, word 0
IR[1] 0x094 Identity Root, word 1
IR[2] 0x098 Identity Root, word 2
IR[3] 0x09C Identity Root, word 3
DEVICEADDRTYPE 0x0A0 Device address type
DEVICEADDR[0] 0x0A4 Device address 0
DEVICEADDR[1] 0x0A8 Device address 1
INFO.PART 0x100 Part code
INFO.VARIANT 0x104 Part Variant, Hardware version and Production configuration
INFO.PACKAGE 0x108 Package option
INFO.RAM 0x10C RAM variant
INFO.FLASH 0x110 Flash variant
0x114 Reserved
0x118 Reserved
0x11C Reserved
TEMP.A0 0x404 Slope definition A0.
TEMP.A1 0x408 Slope definition A1.
TEMP.A2 0x40C Slope definition A2.
TEMP.A3 0x410 Slope definition A3.
TEMP.A4 0x414 Slope definition A4.
TEMP.A5 0x418 Slope definition A5.
TEMP.B0 0x41C y-intercept B0.
TEMP.B1 0x420 y-intercept B1.
TEMP.B2 0x424 y-intercept B2.
TEMP.B3 0x428 y-intercept B3.
TEMP.B4 0x42C y-intercept B4.
TEMP.B5 0x430 y-intercept B5.
TEMP.T0 0x434 Segment end T0.
TEMP.T1 0x438 Segment end T1.
TEMP.T2 0x43C Segment end T2.
TEMP.T3 0x440 Segment end T3.
TEMP.T4 0x444 Segment end T4.
13 FICR — Factory information configuration
registers
Page 44
Register Offset Description
NFC.TAGHEADER0 0x450 Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
NFC.TAGHEADER1 0x454 Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
NFC.TAGHEADER2 0x458 Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
NFC.TAGHEADER3 0x45C Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
13.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R CODEPAGESIZE Code memory page size
13.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R CODESIZE Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
13.1.3 DEVICEID[0]
Address offset: 0x060
Device identifier
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEID 64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
13.1.4 DEVICEID[1]
Address offset: 0x064
Device identifier
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEID 64 bit unique device identifier
13 FICR — Factory information configuration
registers
Page 45
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
13.1.5 ER[0]
Address offset: 0x080
Encryption Root, word 0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption Root, word n
13.1.6 ER[1]
Address offset: 0x084
Encryption Root, word 1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption Root, word n
13.1.7 ER[2]
Address offset: 0x088
Encryption Root, word 2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption Root, word n
13.1.8 ER[3]
Address offset: 0x08C
Encryption Root, word 3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption Root, word n
13.1.9 IR[0]
Address offset: 0x090
Identity Root, word 0
13 FICR — Factory information configuration
registers
Page 46
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word n
13.1.10 IR[1]
Address offset: 0x094
Identity Root, word 1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word n
13.1.11 IR[2]
Address offset: 0x098
Identity Root, word 2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word n
13.1.12 IR[3]
Address offset: 0x09C
Identity Root, word 3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word n
13.1.13 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEADDRTYPE Device address type
Public 0 Public address
Random 1 Random address
13.1.14 DEVICEADDR[0]
Address offset: 0x0A4
Device address 0
13 FICR — Factory information configuration
registers
Page 47
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEADDR 48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
13.1.15 DEVICEADDR[1]
Address offset: 0x0A8
Device address 1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEADDR 48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
13.1.16 INFO.PART
Address offset: 0x100
Part code
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00052832 0 0000000000001010010100000110010
Id RW Field Value Id Value Description
A R PART Part code
N52832 0x52832 nRF52832
Unspecified 0xFFFFFFFF Unspecified
13.1.17 INFO.VARIANT
Address offset: 0x104
Part Variant, Hardware version and Production configuration
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x41414142 0 1000001010000010100000101000010
Id RW Field Value Id Value Description
A R VARIANT Part Variant, Hardware version and Production configuration,
encoded as ASCII
AAAA 0x41414141 AAAA
AAAB 0x41414142 AAAB
AABA 0x41414241 AABA
AABB 0x41414242 AABB
AAB0 0x41414230 AAB0
AAE0 0x41414530 AAE0
Unspecified 0xFFFFFFFF Unspecified
13.1.18 INFO.PACKAGE
Address offset: 0x108
Package option
13 FICR — Factory information configuration
registers
Page 48
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00002000 0 0000000000000000010000000000000
Id RW Field Value Id Value Description
A R PACKAGE Package option
QF 0x2000 QFxx - 48-pin QFN
CH 0x2001 CHxx - 7x8 WLCSP 56 balls
CI 0x2002 CIxx - 7x8 WLCSP 56 balls
CK 0x2005 CKxx - 7x8 WLCSP 56 balls with backside coating for light
protection
Unspecified 0xFFFFFFFF Unspecified
13.1.19 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000040 0 0000000000000000000000001000000
Id RW Field Value Id Value Description
A R RAM RAM variant
K16 0x10 16 kByte RAM
K32 0x20 32 kByte RAM
K64 0x40 64 kByte RAM
Unspecified 0xFFFFFFFF Unspecified
13.1.20 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000200 0 0000000000000000000001000000000
Id RW Field Value Id Value Description
A R FLASH Flash variant
K128 0x80 128 kByte FLASH
K256 0x100 256 kByte FLASH
K512 0x200 512 kByte FLASH
Unspecified 0xFFFFFFFF Unspecified
13.1.21 TEMP.A0
Address offset: 0x404
Slope definition A0.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0x00000320 0 0000000000000000000001100100000
Id RW Field Value Id Value Description
A R A A (slope definition) register.
13.1.22 TEMP.A1
Address offset: 0x408
Slope definition A1.
13 FICR — Factory information configuration
registers
Page 49
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0x00000343 0 0000000000000000000001101000011
Id RW Field Value Id Value Description
A R A A (slope definition) register.
13.1.23 TEMP.A2
Address offset: 0x40C
Slope definition A2.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0x0000035D 0 0000000000000000000001101011101
Id RW Field Value Id Value Description
A R A A (slope definition) register.
13.1.24 TEMP.A3
Address offset: 0x410
Slope definition A3.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0x00000400 0 0000000000000000000010000000000
Id RW Field Value Id Value Description
A R A A (slope definition) register.
13.1.25 TEMP.A4
Address offset: 0x414
Slope definition A4.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0x00000452 0 0000000000000000000010001010010
Id RW Field Value Id Value Description
A R A A (slope definition) register.
13.1.26 TEMP.A5
Address offset: 0x418
Slope definition A5.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0x0000037B 0 0000000000000000000001101111011
Id RW Field Value Id Value Description
A R A A (slope definition) register.
13.1.27 TEMP.B0
Address offset: 0x41C
y-intercept B0.
13 FICR — Factory information configuration
registers
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Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0x00003FCC 0 0000000000000000011111111001100
Id RW Field Value Id Value Description
A R B B (y-intercept)
13.1.28 TEMP.B1
Address offset: 0x420
y-intercept B1.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0x00003F98 0 0000000000000000011111110011000
Id RW Field Value Id Value Description
A R B B (y-intercept)
13.1.29 TEMP.B2
Address offset: 0x424
y-intercept B2.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0x00003F98 0 0000000000000000011111110011000
Id RW Field Value Id Value Description
A R B B (y-intercept)
13.1.30 TEMP.B3
Address offset: 0x428
y-intercept B3.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0x00000012 0 0000000000000000000000000010010
Id RW Field Value Id Value Description
A R B B (y-intercept)
13.1.31 TEMP.B4
Address offset: 0x42C
y-intercept B4.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0x0000004D 0 0000000000000000000000001001101
Id RW Field Value Id Value Description
A R B B (y-intercept)
13.1.32 TEMP.B5
Address offset: 0x430
y-intercept B5.
13 FICR — Factory information configuration
registers
Page 51
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0x00003E10 0 0000000000000000011111000010000
Id RW Field Value Id Value Description
A R B B (y-intercept)
13.1.33 TEMP.T0
Address offset: 0x434
Segment end T0.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0x000000E2 0 0000000000000000000000011100010
Id RW Field Value Id Value Description
A R T T (segment end)register.
13.1.34 TEMP.T1
Address offset: 0x438
Segment end T1.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A R T T (segment end)register.
13.1.35 TEMP.T2
Address offset: 0x43C
Segment end T2.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0x00000014 0 0000000000000000000000000010100
Id RW Field Value Id Value Description
A R T T (segment end)register.
13.1.36 TEMP.T3
Address offset: 0x440
Segment end T3.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0x00000019 0 0000000000000000000000000011001
Id RW Field Value Id Value Description
A R T T (segment end)register.
13.1.37 TEMP.T4
Address offset: 0x444
Segment end T4.
13 FICR — Factory information configuration
registers
Page 52
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0x00000050 0 0000000000000000000000001010000
Id RW Field Value Id Value Description
A R T T (segment end)register.
13.1.38 NFC.TAGHEADER0
Address offset: 0x450
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFF5F 1 1111111111111111111111101011111
Id RW Field Value Id Value Description
A R MFGID Default Manufacturer ID: Nordic Semiconductor ASA has ICM
0x5F
B R UD1 Unique identifier byte 1
C R UD2 Unique identifier byte 2
D R UD3 Unique identifier byte 3
13.1.39 NFC.TAGHEADER1
Address offset: 0x454
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R UD4 Unique identifier byte 4
B R UD5 Unique identifier byte 5
C R UD6 Unique identifier byte 6
D R UD7 Unique identifier byte 7
13.1.40 NFC.TAGHEADER2
Address offset: 0x458
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R UD8 Unique identifier byte 8
B R UD9 Unique identifier byte 9
C R UD10 Unique identifier byte 10
D R UD11 Unique identifier byte 11
13.1.41 NFC.TAGHEADER3
Address offset: 0x45C
Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
13 FICR — Factory information configuration
registers
Page 53
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R UD12 Unique identifier byte 12
B R UD13 Unique identifier byte 13
C R UD14 Unique identifier byte 14
D R UD15 Unique identifier byte 15
14 UICR — User information configuration
registers
Page 54
14 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring
user specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 29 and
Memory on page 23 chapters.
14.1 Registers
Table 19: Instances
Base address Peripheral Instance Description Configuration
0x10001000 UICR UICR User Information Configuration
Table 20: Register Overview
Register Offset Description
0x000 Reserved
0x004 Reserved
0x008 Reserved
0x010 Reserved
NRFFW[0] 0x014 Reserved for Nordic firmware design
NRFFW[1] 0x018 Reserved for Nordic firmware design
NRFFW[2] 0x01C Reserved for Nordic firmware design
NRFFW[3] 0x020 Reserved for Nordic firmware design
NRFFW[4] 0x024 Reserved for Nordic firmware design
NRFFW[5] 0x028 Reserved for Nordic firmware design
NRFFW[6] 0x02C Reserved for Nordic firmware design
NRFFW[7] 0x030 Reserved for Nordic firmware design
NRFFW[8] 0x034 Reserved for Nordic firmware design
NRFFW[9] 0x038 Reserved for Nordic firmware design
NRFFW[10] 0x03C Reserved for Nordic firmware design
NRFFW[11] 0x040 Reserved for Nordic firmware design
NRFFW[12] 0x044 Reserved for Nordic firmware design
NRFFW[13] 0x048 Reserved for Nordic firmware design
NRFFW[14] 0x04C Reserved for Nordic firmware design
NRFHW[0] 0x050 Reserved for Nordic hardware design
NRFHW[1] 0x054 Reserved for Nordic hardware design
NRFHW[2] 0x058 Reserved for Nordic hardware design
NRFHW[3] 0x05C Reserved for Nordic hardware design
NRFHW[4] 0x060 Reserved for Nordic hardware design
NRFHW[5] 0x064 Reserved for Nordic hardware design
NRFHW[6] 0x068 Reserved for Nordic hardware design
NRFHW[7] 0x06C Reserved for Nordic hardware design
NRFHW[8] 0x070 Reserved for Nordic hardware design
NRFHW[9] 0x074 Reserved for Nordic hardware design
NRFHW[10] 0x078 Reserved for Nordic hardware design
NRFHW[11] 0x07C Reserved for Nordic hardware design
CUSTOMER[0] 0x080 Reserved for customer
CUSTOMER[1] 0x084 Reserved for customer
CUSTOMER[2] 0x088 Reserved for customer
CUSTOMER[3] 0x08C Reserved for customer
CUSTOMER[4] 0x090 Reserved for customer
CUSTOMER[5] 0x094 Reserved for customer
CUSTOMER[6] 0x098 Reserved for customer
14 UICR — User information configuration
registers
Page 55
Register Offset Description
CUSTOMER[7] 0x09C Reserved for customer
CUSTOMER[8] 0x0A0 Reserved for customer
CUSTOMER[9] 0x0A4 Reserved for customer
CUSTOMER[10] 0x0A8 Reserved for customer
CUSTOMER[11] 0x0AC Reserved for customer
CUSTOMER[12] 0x0B0 Reserved for customer
CUSTOMER[13] 0x0B4 Reserved for customer
CUSTOMER[14] 0x0B8 Reserved for customer
CUSTOMER[15] 0x0BC Reserved for customer
CUSTOMER[16] 0x0C0 Reserved for customer
CUSTOMER[17] 0x0C4 Reserved for customer
CUSTOMER[18] 0x0C8 Reserved for customer
CUSTOMER[19] 0x0CC Reserved for customer
CUSTOMER[20] 0x0D0 Reserved for customer
CUSTOMER[21] 0x0D4 Reserved for customer
CUSTOMER[22] 0x0D8 Reserved for customer
CUSTOMER[23] 0x0DC Reserved for customer
CUSTOMER[24] 0x0E0 Reserved for customer
CUSTOMER[25] 0x0E4 Reserved for customer
CUSTOMER[26] 0x0E8 Reserved for customer
CUSTOMER[27] 0x0EC Reserved for customer
CUSTOMER[28] 0x0F0 Reserved for customer
CUSTOMER[29] 0x0F4 Reserved for customer
CUSTOMER[30] 0x0F8 Reserved for customer
CUSTOMER[31] 0x0FC Reserved for customer
PSELRESET[0] 0x200 Mapping of the nRESET function (see POWER chapter for details)
PSELRESET[1] 0x204 Mapping of the nRESET function (see POWER chapter for details)
APPROTECT 0x208 Access Port protection
NFCPINS 0x20C Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
14.1.1 NRFFW[0]
Address offset: 0x014
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.2 NRFFW[1]
Address offset: 0x018
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.3 NRFFW[2]
Address offset: 0x01C
Reserved for Nordic firmware design
14 UICR — User information configuration
registers
Page 56
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.4 NRFFW[3]
Address offset: 0x020
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.5 NRFFW[4]
Address offset: 0x024
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.6 NRFFW[5]
Address offset: 0x028
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.7 NRFFW[6]
Address offset: 0x02C
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.8 NRFFW[7]
Address offset: 0x030
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14 UICR — User information configuration
registers
Page 57
14.1.9 NRFFW[8]
Address offset: 0x034
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.10 NRFFW[9]
Address offset: 0x038
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.11 NRFFW[10]
Address offset: 0x03C
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.12 NRFFW[11]
Address offset: 0x040
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.13 NRFFW[12]
Address offset: 0x044
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.14 NRFFW[13]
Address offset: 0x048
Reserved for Nordic firmware design
14 UICR — User information configuration
registers
Page 58
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.15 NRFFW[14]
Address offset: 0x04C
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
14.1.16 NRFHW[0]
Address offset: 0x050
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.17 NRFHW[1]
Address offset: 0x054
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.18 NRFHW[2]
Address offset: 0x058
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.19 NRFHW[3]
Address offset: 0x05C
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14 UICR — User information configuration
registers
Page 59
14.1.20 NRFHW[4]
Address offset: 0x060
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.21 NRFHW[5]
Address offset: 0x064
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.22 NRFHW[6]
Address offset: 0x068
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.23 NRFHW[7]
Address offset: 0x06C
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.24 NRFHW[8]
Address offset: 0x070
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.25 NRFHW[9]
Address offset: 0x074
Reserved for Nordic hardware design
14 UICR — User information configuration
registers
Page 60
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.26 NRFHW[10]
Address offset: 0x078
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.27 NRFHW[11]
Address offset: 0x07C
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
14.1.28 CUSTOMER[0]
Address offset: 0x080
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.29 CUSTOMER[1]
Address offset: 0x084
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.30 CUSTOMER[2]
Address offset: 0x088
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14 UICR — User information configuration
registers
Page 61
14.1.31 CUSTOMER[3]
Address offset: 0x08C
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.32 CUSTOMER[4]
Address offset: 0x090
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.33 CUSTOMER[5]
Address offset: 0x094
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.34 CUSTOMER[6]
Address offset: 0x098
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.35 CUSTOMER[7]
Address offset: 0x09C
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.36 CUSTOMER[8]
Address offset: 0x0A0
Reserved for customer
14 UICR — User information configuration
registers
Page 62
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.37 CUSTOMER[9]
Address offset: 0x0A4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.38 CUSTOMER[10]
Address offset: 0x0A8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.39 CUSTOMER[11]
Address offset: 0x0AC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.40 CUSTOMER[12]
Address offset: 0x0B0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.41 CUSTOMER[13]
Address offset: 0x0B4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14 UICR — User information configuration
registers
Page 63
14.1.42 CUSTOMER[14]
Address offset: 0x0B8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.43 CUSTOMER[15]
Address offset: 0x0BC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.44 CUSTOMER[16]
Address offset: 0x0C0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.45 CUSTOMER[17]
Address offset: 0x0C4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.46 CUSTOMER[18]
Address offset: 0x0C8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.47 CUSTOMER[19]
Address offset: 0x0CC
Reserved for customer
14 UICR — User information configuration
registers
Page 64
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.48 CUSTOMER[20]
Address offset: 0x0D0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.49 CUSTOMER[21]
Address offset: 0x0D4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.50 CUSTOMER[22]
Address offset: 0x0D8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.51 CUSTOMER[23]
Address offset: 0x0DC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.52 CUSTOMER[24]
Address offset: 0x0E0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14 UICR — User information configuration
registers
Page 65
14.1.53 CUSTOMER[25]
Address offset: 0x0E4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.54 CUSTOMER[26]
Address offset: 0x0E8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.55 CUSTOMER[27]
Address offset: 0x0EC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.56 CUSTOMER[28]
Address offset: 0x0F0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.57 CUSTOMER[29]
Address offset: 0x0F4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.58 CUSTOMER[30]
Address offset: 0x0F8
Reserved for customer
14 UICR — User information configuration
registers
Page 66
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.59 CUSTOMER[31]
Address offset: 0x0FC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
14.1.60 PSELRESET[0]
Address offset: 0x200
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If they don't, there
will be no nRESET function exposed on a GPIO, and the device will always start independently of the levels
present on any of the GPIOs.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id B AAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PIN 21 GPIO number P0.n onto which Reset is exposed
B RW CONNECT Connection
Disconnected 1 Disconnect
Connected 0 Connect
14.1.61 PSELRESET[1]
Address offset: 0x204
Mapping of the nRESET function (see POWER chapter for details)
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If they don't, there
will be no nRESET function exposed on a GPIO, and the device will always start independently of the levels
present on any of the GPIOs.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id B AAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PIN 21 GPIO number P0.n onto which Reset is exposed
B RW CONNECT Connection
Disconnected 1 Disconnect
Connected 0 Connect
14.1.62 APPROTECT
Address offset: 0x208
Access Port protection
14 UICR — User information configuration
registers
Page 67
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PALL Enable or disable Access Port protection. Any other value than
0xFF being written to this field will enable protection.
See Debug and trace on page 72 for more information.
Disabled 0xFF Disable
Enabled 0x00 Enable
14.1.63 NFCPINS
Address offset: 0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PROTECT Setting of pins dedicated to NFC functionality
Disabled 0 Operation as GPIO pins. Same protection as normal GPIO pins
NFC 1 Operation as NFC antenna pins. Configures the protection for
NFC operation
15 Peripheral interface
Page 68
15 Peripheral interface
Peripherals are controlled by the CPU by writing