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IS25LP128, 064, 032 Datasheet

ISSI, Integrated Silicon Solution Inc

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Datasheet

IS25LP128
IS25LP064
IS25LP032
32/64/128M-BIT
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
DATA SHEET
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. D
10/03/2014
FEATURES
Industry Standard Serial Interface
- IS25LP128: 128M-bit/16M-byte
- IS25LP064: 64M-bit/8M-byte
- IS25LP032: 32M-bit/4M-byte
- 256 bytes per Programmable Page
- Supports standard SPI, Fast, Dual, Dual
I/O, QPI, SPI DTR, Dual SPI DTR I/O,
and QPI
- Double Transfer Rate (DTR) option
- Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
- 50MHz Normal and 133Mhz Fast Read
- 532 MHz equivalent QPI
- DTR (Dual Transfer Rate) up to 66MHz
- Selectable dummy cycles
- Configurable drive strength
- Supports SPI Modes 0 and 3
- More than 100,000 erase/program cycles
- More than 20-year data retention
Flexible & Efficient Memory Architecture
- Chip Erase with Uniform: Sector/Block
Erase (4K/32K/64K-Byte)
- Program 1 to 256 bytes per page
- Program/Erase Suspend & Resume
Efficient Read and Program modes
- Low Instruction Overhead Operations
- Continuous Read 8/16/32/64-Byte burst
- Selectable burst length
- QPI for reduced instruction overhead
Low Power with Wide Temp.
Ranges
- Single 2.3V to 3.6V Voltage Supply
- 10 mA Active Read Current
- 10 µA Standby Current
- 5 µA Deep Power Down
- Temp Grades:
Extended: -40°C to +105°C
V Grade: -40°C to +125°C
Auto Grade: up to +125°C
Advanced Security Protection
- Software and Hardware Write Protection
- Power Supply lock protect
- 4x256-Byte dedicated security area
with user-lockable bits, (OTP) One
Time Programmable Memory
- 128 bit Unique ID for each device
Industry Standard Pin-out & Packages
- JM =16-pin SOIC 300mil
- JB = 8-pin SOIC 208mil
- JF = 8-pin VSOP 208mil
- JK = 8-contact WSON 6x5mm
- JL = 8-contact WSON 8x6mm
- JG= 24-ball TFBGA 6x8mm
- KGD (call factory)
32/64/128M-BIT
3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 3
Rev. D
10/03/2014
GENERAL DESCRIPTION
The IS25LP032/064/128 Serial Flash memory offers a versatile storage solution with high flexibility and
performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems
that require limited space, a low pin count, and low power consumption. The IS25LP032/064/128 is accessed
through a 4-wire SPI Interface consisting of a Serial Data Input (Sl), Serial Data Output (SO), Serial Clock
(SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock
frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) allowing more than
66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate)
commands that transfer addresses and read data on both edges of the clock. These transfer rates can
outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in
place) operation.
The memory array is organized into programmable pages of 256-bytes. This family supports page program
mode where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface)
supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4K-byte
sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform sector and block architecture
allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications
requiring solid data retention.
GLOSSARY
Standard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (Sl), Serial Data Output (SO),
Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,
addresses, or input data to the device on the rising edge of SCK. The DO pin is used to read data or to check the
status of the device on the falling edge of SCK. This device supports SPI bus operation modes (0,0) and (1,1).
Mutil I/O SPI
Multi-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, and Quad Input and Output capability. Executing these instructions through SPI mode will achieve
double or quadruple the transfer bandwidth for READ and PROGRAM operations.
Quad I/O QPI
The IS25LP032/064/128 enables QPI protocol by issuing an “Enter QPI mode (35h)” command. The QPI mode
uses four IO pins for input and output to decrease SPI instruction overhead and increase output bandwidth. SI
and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode. Issuing an “Exit QPI (F5h) command will cause the device to exit QPI mode. Power Reset or
Hardware/Software Reset can also return the device into the standard SPI mode.
DTR
In addition to SPI and QPI features, IS25LP032/064/128 also supports SPI DTR READ. SPI DTR allows high
data throughput while running at lower clock frequencies. SPI DTR READ mode uses both rising and falling
edges of the clock to drive output, resulting in reducing the dummy cycles by half.
Programmable drive strength and Selectable burst setting.
The IS25LP032/064/128 offers programmable output drive strength and selectable burst (wrap) length features
to increase the efficiency and performance of READ operations. The driver strength and burst setting features
are controlled by setting the READ registers. A total of six different drive strengths and four different burst sizes
(8/16/32/64 Bytes) are available for selection.
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 4
Rev. D
10/03/2014
TABLE OF CONTENTS
1. PIN CONFIGURATION ................................................................................................................................. 6
2. PIN DESCRIPTIONS .................................................................................................................................... 7
3. BLOCK DIAGRAM ........................................................................................................................................ 8
4. SPI MODES DESCRIPTION ........................................................................................................................ 9
5. SYSTEM CONFIGURATION ...................................................................................................................... 11
5.1 BLOCK/SECTOR ADDRESSES .......................................................................................................... 11
6. REGISTERS ............................................................................................................................................... 12
6.1 STATUS REGISTER ............................................................................................................................ 12
6.2 FUNCTION REGISTER ........................................................................................................................ 15
6.3 READ REGISTERS .............................................................................................................................. 16
7. PROTECTION MODE ................................................................................................................................. 18
7.1 HARDWARE WRITE PROTECTION .................................................................................................... 18
7.2 SOFTWARE WRITE PROTECTION .................................................................................................... 18
8. DEVICE OPERATION ................................................................................................................................ 19
8.1 NORMAL READ OPERATION (NORD, 03h) ....................................................................................... 21
8.2 FAST READ OPERATION (FRD, 0Bh) ................................................................................................ 23
8.3 HOLD OPERATION .............................................................................................................................. 25
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ........................................................................... 25
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ................................................................... 28
8.6 FAST READ QUAD I/O OPERATION (FRQIO, EBh) .......................................................................... 30
8.7 PAGE PROGRAM OPERATION (PP, 02h) .......................................................................................... 33
8.8 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) ........................................................ 35
8.9 ERASE OPERATION ........................................................................................................................... 36
8.10 SECTOR ERASE OPERATION (SER, D7h/20h) ............................................................................... 37
8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) ............................................................ 38
8.12 CHIP ERASE OPERATION (CER, C7h/60h) ..................................................................................... 40
8.13 WRITE ENABLE OPERATION (WREN, 06h) .................................................................................... 41
8.14 WRITE DISABLE OPERATION (WRDI, 04h) ..................................................................................... 42
8.15 READ STATUS REGISTER OPERATION (RDSR, 05h) ................................................................... 43
8.16 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................. 44
8.17 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ............................................................... 45
8.18 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................. 46
8.19 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QIOEN,35h; QIODI,F5h) . 47
8.20 PROGRAM/ERASE SUSPEND & RESUME ...................................................................................... 48
8.21 DEEP POWER DOWN (DP, B9h) ...................................................................................................... 49
8.22 RELEASE DEEP POWER DOWN (RDPD, ABh) ............................................................................... 50
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 5
Rev. D
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8.23 SET READ PARAMETERS OPERATION (SRP, C0h) ...................................................................... 51
8.24 READ PRODUCT IDENTIFICATION (RDID, ABh) ............................................................................ 53
8.25 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) 55
8.26 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ........................ 56
8.27 READ UNIQUE ID NUMBER (RDUID, 4Bh) ...................................................................................... 57
8.28 READ SFDP OPERATION (RDSFDP, 5Ah) ...................................................................................... 58
8.29 NO OPERATION (NOP, 00h) ............................................................................................................. 58
8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ........................................................................................................................................................ 59
8.31 SECURITY INFORMATION ROW ...................................................................................................... 60
8.32 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................. 61
8.33 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................. 62
8.34 INFORMATION ROW READ OPERATION (IRRD, 68h) ................................................................... 63
8.35 FAST READ DTR MODE OPERATION (FRDTR, 0Dh) ..................................................................... 64
8.36 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh) .................................................. 66
8.37 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh) ................................................. 69
8.38 SECTOR LOCK/UNLOCK FUNCTIONS ............................................................................................ 72
9. ELECTRICAL CHARACTERISTICS ........................................................................................................... 74
9.1 ABSOLUTE MAXIMUM RATINGS (1) ................................................................................................... 74
9.2 OPERATING RANGE ........................................................................................................................... 74
9.3 DC CHARACTERISTICS ...................................................................................................................... 74
9.4 AC MEASUREMENT CONDITIONS .................................................................................................... 75
9.5 AC CHARACTERISTICS ...................................................................................................................... 76
9.6 SERIAL INPUT/OUTPUT TIMING ........................................................................................................ 78
9.7 POWER-UP AND POWER-DOWN ...................................................................................................... 80
9.8 PROGRAM/ERASE PERFORMANCE ................................................................................................. 81
9.9 RELIABILITY CHARACTERISTICS ..................................................................................................... 81
10. PACKAGE TYPE INFORMATION ......................................................................................................... 82
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (JB) ........................ 82
10.2 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (JK) .................................. 83
10.3 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 8x6mm (JL) .................................. 84
10.4 8-Pin 208mil VSOP Package (JF) .................................................................................................... 85
10.5 16-lead Plastic Small Outline package (300 mils body width) (JM) .................................................. 86
10.6 24-Ball Thin Profile Fine Pitch BGA 6x8mm (JG) ............................................................................. 87
11. ORDERING INFORMATION- Valid Part Numbers ................................................................................ 88
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 6
Rev. D
10/03/2014
1. PIN CONFIGURATION
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
D1 D2 D3 D4
E1 E2 E3 E4
F1 F2 F3 F4
NC NC NC NC
NC SCK GND VCC
NC CE# NC WP#(IO2)
NC SO(IO1) SI(IO0) HOLD#(IO3)
NC NC NC NC
NC NC NC NC
Top View, Balls Facing Down
Note1: For RESET# pin option instead of HOLD# pin, call Factory.
HOLD# (IO3) (1)
Vcc
GND
SCK
1
2
3
4
7
6
5
SO (IO1)
SI (IO0)
8
WP# (IO2)
6
3
CE#
Vcc
SCK
SI (IO0)
7
8
5
4
1
2
GND
WP# (IO2)
SO (IO1)
HOLD# (IO3) (1)
8-pin SOIC 208mil
8-pin VSOP 208mil
8-pin WSON 6x5mm
8-pin WSON 8x6mm
16-pin SOIC 300mil
24-ball TFBGA 6x8mm
12
10
11
9
13
15
14
5
7
6
8
4
2
3
16
1
Vcc
(1) HOLD# (IO3)
SCK
CE#
WP# (IO2)
GND
NC
NC
NC
NC
NC
SI (IO0)
SO (IO1)
NC
NC
NC
(1)
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 7
Rev. D
10/03/2014
2. PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a high
impedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.
When CE# is pulled low the device will be selected and brought out of standby
mode. The device is considered active and instructions can be written to, data read,
and written to the device. After power-up, CE# must transition from high to low
before a new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,
addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or status
from the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written. When the WP# is low the status registers are write-protected and vice-
versa for high. When the QE bit is set to “1”, the WP# pin (Write Protect) function is
not available since this pin is used for IO2.
HOLD# or
RESET# (IO3)
INPUT/OUTPUT
HOLD# or RESET#/Serial Data IO (IO3): When the QE bit of Status Register is set
to “1”, HOLD# pin or RESET# is not available since it becomes IO3. When QE=0 the
pin acts as HOLD# or RESET#.
RESET# pin can be selected with dedicated parts (Call Factory).
The HOLD# pin allows the device to be paused while it is selected. It pauses serial
communication by the master device without resetting the serial sequence. The
HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin
will be at high impedance. Device operation can resume when HOLD# pin is brought
to a high state.
RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the
memory is in the normal operating mode. When RESET# is driven LOW, the memory
enters reset mode and output is High-Z. If RESET# is driven LOW while an internal
WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.
SCK
INPUT
Serial Data Clock: Synchronized Clock for input and output timing operations.
Vcc
POWER
Power: Device Core Power Supply
GND
GROUND
Ground: Connect to ground when referenced to Vcc
NC
Unused
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 8
Rev. D
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3. BLOCK DIAGRAM
Note1: For RESET# pin option instead of HOLD# pin, call Factory.
SI (IO0)
WP# (IO2)
Control Logic High Voltage Generator
I/O Buffers and
Data Latches
256 Bytes
Page Buffer
Y-Decoder
X-Decoder
Serial Peripheral Interface
Status
Register
Address Latch &
Counter
Memory Array
CE#
SCK
WP#
(IO2)
SI
(IO0)
SO
(IO1)
HOLD# or RESET#
(IO3)
(1)
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 9
Rev. D
10/03/2014
4. SPI MODES DESCRIPTION
Multiple IS25LP032/064/128 devices can be connected on the SPI serial bus and controlled by a SPI Master,
i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the
serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer
to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge
of Serial Clock (SCK), and the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
Notes:
1. For RESET# pin option instead of HOLD# pin, call Factory.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively
during QPI mode.
SPI interface with
(0,0) or (1,1)
SPI Master
(i.e. Microcontroller) SPI
Memory
Device
SPI
Memory
Device
SPI
Memory
Device
SCK SO SI
SCK
SDI
SDO
CE#
WP#HOLD# or
RESET
SCK SO SI
CE#
WP#HOLD# or
RESET#
SCK SO SI
CE#
WP#
CS3CS2CS1
HOLD# or
RESET#
(1)
(1)
(1)
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 10
Rev. D
10/03/2014
Figure 4.2 SPI Mode Support
SCK
SO
SI
Mode 0 (0,0)
Mode 3 (1,1)
MSB
MSB
SCK
Figure 4.3 QPI Mode Support
20
CE#
SCK
40 4 0
3-byte Address
16 12 8
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
IO0
IO121 51 5 1
17 13 9
22 62 6 2
18 14 10
23 73 7 3
19 15 11
Mode Bits
IO2
IO3
C4 C0
C1C5
C2C6
C3C7
40 4 0
51 5 1
62 6 2
73 7 3
4
5
6
7
0
1
2
3
...
...
...
...
Data 1 Data 2 Data 3
IS25LP032/064/128
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Rev. D
10/03/2014
5. SYSTEM CONFIGURATION
The memory array of IS25LP032/064/128 is divided into uniform 4 Kbyte sectors or uniform 32K/64 Kbyte
blocks (a block consists of eight/sixteen adjacent sectors respectively).
Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is mapped.
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25LP032/064/128
Memory Density
Block No.
(64Kbyte)
Block No.
(32Kbyte)
Sector No.
Sector
Size
(KBytes)
Address Range
32Mb
64Mb
128Mb
Block 0
Block 0
Sector 0
4
000000h 000FFFh
:
:
:
Block 1
:
:
:
Sector 15
4
00F000h - 00FFFFh
Block 1
Block 2
Sector 16
4
010000h 010FFFh
:
:
:
Block 3
:
:
:
Sector 31
4
01F000h - 01FFFFh
Block 2
Block 4
Sector 32
4
020000h - 0200FFh
:
:
:
Block 5
:
:
:
Sector 47
4
02F000h 02FFFFh
:
:
:
:
:
Block 63
Block 126
:
:
:
Block 127
Sector 1023
4
3FF000h 3FFFFFh
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Block 127
:
:
:
:
:
:
:
Block 255
:
:
:
Sector 2047
4
7FF000h 7FFFFFh
:
:
:
:
:
:
:
:
:
:
Block 254
Block 508
Sector 4064
4
FE0000h FE0FFFh
:
:
:
Block 509
:
:
:
Sector 4079
4
FEF000h FEFFFFh
Block 255
Block 510
Sector 4080
4
FF0000h FF0FFFh
:
:
:
Block 511
:
:
:
Sector 4095
4
FFF000h FFFFFFh
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 12
Rev. D
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6. REGISTERS
The IS25LP032/064/128 has three sets of Registers: Status, Function and Read.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.
Table 6.1 Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
QE
BP3
BP2
BP1
BP0
WEL
WIP
Default (Flash bit)
0
0
0
0
0
0
0
0
Table 6.2 Status Register Bit Definition
Bit
Name
Definition
Read-
/Write
Non-Volatile
bit
Bit 0
WIP
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
R
No
Bit 1
WEL
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
R/W
No
Bit 2
BP0
Block Protection Bit: (See Tables 6.3 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
R/W
Yes
Bit 3
BP1
Bit 4
BP2
Bit 5
BP3
Bit 6
QE
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
R/W
Yes
Bit 7
SRWD
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W
Yes
The BP0, BP1, BP2, BP3, SRWD, and QE are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP2, BP1, BP0, and SRWD bits were set to “0” at factory.
The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for write status register, program or
erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the
WEL is “0”, the write enable latch is disabled and all write operations, including write status register, write
configuration register, page program, sector erase, block and chip erase operations are inhibited. When the
WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each
write register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be
reset by a Write Disable (WRDI) instruction. It will automatically reset after the completion of any write operation.
IS25LP032/064/128
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BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Tables 6.3 for the Block Write Protection (BP) bit settings. When a
defined combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any
program or erase operation to that area will be inhibited.
Note: A Chip Erase (CER) instruction will be ignored unless all the Block Protection Bits are “0”s.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection
(WP#) signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not
write-protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register
(SRWD, BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to
“1” and WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) is a non-volatile bit in the status register that allows quad operation. When the
QE bit is set to 0, the pin WP# and HOLD# are enabled. When the QE bit is set to 1, the IO2 and IO3 pins
are enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply or ground.
IS25LP032/064/128
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Table 6.3 Block (64Kbyte) assignment by Block Write Protect (BP) Bits
Status Register Bits
Protected Memory Area (IS25LP128, 256Blocks)
BP3
BP2
BP1
BP0
TBS(T/B selection) = 0, TOP area
TBS(T/B selection) = 1, Bottom area
0
0
0
0
0( None)
0( None)
0
0
0
1
1(1 block : 255th)
1(1 block : 0th)
0
0
1
0
2(2 blocks : 254th and 255th)
2(2 blocks : 0th and 1st)
0
0
1
1
3(4 blocks : 252nd to 255th)
3(4 blocks : 0th to 3rd)
0
1
0
0
4(8 blocks : 248th to 255th)
4(8 blocks : 0th to 7th)
0
1
0
1
5(16 blocks :240th to 255th)
5(16 blocks : 0th to 15th)
0
1
1
0
6(32 blocks : 224th to 255th)
6(32 blocks : 0th to 31st)
0
1
1
1
7(64 blocks : 192nd to 255th)
7(64 blocks : 0th to 63rd)
1
0
0
0
8(128 blocks : 128th to 255th)
8(128 blocks : 0th to 127th)
1
0
0
1
9(256 blocks : 0th to 255th) All blocks
9(256 blocks : 0th to 255th) All blocks
1
0
1
x
10-11(256 blocks : 0th to 255th) All blocks
10-11(256 blocks : 0th to 255th) All blocks
1
1
x
x
12-15(256 blocks : 0th to 255th) All blocks
12-15(256 blocks : 0th to 255th) All blocks
Status Register Bits
Protected Memory Area(IS25LP064, 128Blocks)
BP3
BP2
BP1
BP0
TBS(T/B selection) = 0, TOP area
TBS(T/B selection) = 1, Bottom area
0
0
0
0
0( None)
0( None)
0
0
0
1
1(1 block : 127th)
1(1 block : 0th)
0
0
1
0
2(2 blocks : 126th and 127th)
2(2 blocks : 0th and 1st)
0
0
1
1
3(4 blocks : 124th to 127th)
3(4 blocks : 0th to 3rd)
0
1
0
0
4(8 blocks : 120th to 127th)
4(8 blocks : 0th to 7th)
0
1
0
1
5(16 blocks :112nd to 127th)
5(16 blocks : 0th to 15th)
0
1
1
0
6(32 blocks : 96th to 127th)
6(32 blocks : 0th to 31st)
0
1
1
1
7(64 blocks : 64th to 127th)
7(64 blocks : 0th to 63rd)
1
x
x
x
8~15(128 blocks : 0th to 127th) All blocks
8~15(128 blocks : 0th to 127th) All blocks
Status Register Bits
Protected Memory Area(IS25LP032, 64Blocks)
BP3
BP2
BP1
BP0
TBS(T/B selection) = 0, TOP area
TBS(T/B selection) = 1, Bottom area
0
0
0
0
0( None)
0( None)
0
0
0
1
1(1 block : 63rd)
1(1 block : 0th)
0
0
1
0
2(2 blocks : 62nd and 63rd)
2(2 blocks : 0th and 1st)
0
0
1
1
3(4 blocks : 60th to 63rd)
3(4 blocks : 0th to 3rd)
0
1
0
0
4(8 blocks : 56th to 63rd)
4(8 blocks : 0th to 7th)
0
1
0
1
5(16 blocks :48th to 63rd)
5(16 blocks : 0th to 15th)
0
1
1
0
6(32 blocks : 32nd to 63rd)
6(32 blocks : 0th to 31st)
0
1
1
1
7(64 blocks : 0th to 63rd) All blocks
7(64 blocks : 0th to 63rd) All blocks
1
x
x
x
8~15(64 blocks : 0th to 63rd) All blocks
8~15(64 blocks : 0th to 63rd) All blocks
Note: x is don’t care
IS25LP032/064/128
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Rev. D
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6.2 FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.4 and 6.5
Table 6.4 Function Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRL3
IRL2
IRL1
IRL0
ESUS
PSUS
TBS
Reserved
Default
0
0
0
0
0
0
0
0
Table 6.5 Function Register Bit Definition
Bit
Name
Definition
Read-
/Write
Non-Volatile
bit
Bit 0
Reserved
Reserved
Reserved
Reserved
Bit 1
Top/Bottom
Selection
Top/Bottom Selection. (See Tables 6.3 for details)
“0” indicates Top area.
“1” indicates Bottom area.
R/W
Yes
Bit 2
PSUS
Program suspend bit:
“0” indicates program is not suspend
“1” indicates program is suspend
R
No
Bit 3
ESUS
Erase suspend bit:
"0" indicates Erase is not suspend
"1" indicates Erase is suspend
R
No
Bit 4
IR Lock 0
Lock the information row 0:
“0” indicates the information row can be programmed
“1” indicates the information row cannot be programmed
R/W
Yes
Bit 5
IR Lock 1
Lock the information row 1:
“0” indicates the information row can be programmed
“1” indicates the information row cannot be programmed
R/W
Yes
Bit 6
IR Lock 2
Lock the information row 2:
“0” indicates the information row can be programmed
“1” indicates the information row cannot be programmed
R/W
Yes
Bit 7
IR Lock 3
Lock the information row 3:
“0” indicates the information row can be programmed
“1” indicates the information row cannot be programmed
R/W
Yes
Note: Table 6.5 Function Register bits are only one time programmable and cannot be modified
Top/Bottom Selection: BP0~3 area assignment changed from Top or Bottom. See Tables 6.5 for details
The Program Suspend Status bit indicates when a Program operation has been suspended. The
PSUS changes to ‘1’ after a suspend command is issued during the program operation. Once the suspended
Program resumes, the PSUS bit is reset to ‘0.’
ESUS bit: The Erase Suspend Status indicates when an Erase operation has been suspended. The ESUS bit is
‘1’ after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, the
ESUS bit is reset to ‘0.’
IR lock bit 0 ~ 3: The information row lock bits are programmable. If the bit set to 1, it cant be programmed.
IS25LP032/064/128
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Rev. D
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6.3 READ REGISTERS
Read Register format and Bit definitions pertaining to QPI mode are described below.
READ PARAMETER BITS
Table 6.6 defines all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0 (P7, P6, P5) bits
provide a method to set and control driver strength. The Dummy Cycle bits (P4, P3) define how many dummy
cycles are used during various READ modes. The wrap selection bits (P2, P1, P0) define burst length with wrap
around.
The SET READ PARAMETERS Operation (SRP, C0h) is used to set all the Read Register bits, and can thereby
define the output driver strength, number of dummy cycles used during READ modes, burst length with wrap
around.
Table 6.6 Read Parameter Table
P7
P6
P5
P4
P3
P2
P1
P0
ODS2
ODS1
ODS0
Dummy
Cycles
Dummy
Cycles
Wrap
Enable
Burst
Length
Burst
Length
Default (Flash bit)
1
1
1
0
0
0
0
0
Table 6.7 Burst Length Data
P1
P0
8 bytes
0
0
16 bytes
0
1
32 bytes
1
0
64 bytes
1
1
Table 6.8 Wrap Function
Wrap around boundary
P2
Whole cell regardless of P1 and P0 value
0
Burst Length set by P1 and P0
1
IS25LP032/064/128
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Rev. D
10/03/2014
Table 6.9 Read Dummy Cycles.
Read Modes
P4,P3 = 00
(Default)
P4,P3 = 01
P4,P3 = 10
P4,P3 = 11
Max Freq
Mode
Normal Read
03h
0
0
0
0
50MHz
SPI
Fast read
0Bh
8
8
8
8
133MHz
SPI
Fast read
0Bh
6
4
8
10
4cc : 84MHz
6cc : 104MHz
8cc/10cc : 133MHz
QPI
Dual IO Read (1)
BBh
4
4
8
4
4cc : 104MHz
8cc : 133MHz
SPI
Fast Read Dual Output
3Bh
8
8
8
8
133MHz
SPI
Quad IO Read (2)
EBh
6
4
8
10
4cc : 84MHz
6cc : 104MHz
8cc/10cc : 133MHz
SPI , QPI
Notes:
1. When 4 dummy cycles are used the max clock frequency is 104MHz; when 8 dummy cycles are used the max
clock frequency is 133MHz.
2. When 4 dummy cycles are used the max clock frequency is 84MHz; when 6 dummy cycles are used the max clock
frequency is 104MHz; when 8 or 10 dummy cycles are used the max clock frequency is 133MHz.
3. In SPI DTR mode the dummy cycles are reduced by half.
4. Dummy cycles in the table are including Mode bit cycles.
Table 6.10 Driver Strength Table
ODS2
ODS1
ODS0
Description
Remark
0
0
0
Reserved
0
0
1
12.50%
0
1
0
25%
0
1
1
37.50%
1
0
0
Reserved
1
0
1
75%
1
1
0
100%
1
1
1
50%
Default
IS25LP032/064/128
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Rev. D
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7. PROTECTION MODE
The IS25LP032/064/128 supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD,
and QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage is 2.1V. All write sequence will be ignored when Vcc drops to 2.1V or lower.
7.2 SOFTWARE WRITE PROTECTION
The IS25LP032/064/128 also provides a software write protection feature. The Block Protection (BP3, BP2,
BP1, BP0) bits allow part or the whole memory area to be write-protected.
Table 7.1 Hardware Write Protection on Status Register
SRWD
WP#
Status Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Note: Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL)
bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the
program, erase or write register instruction will be ignored.
IS25LP032/064/128
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Rev. D
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8. DEVICE OPERATION
The IS25LP032/064/128 utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on
instructions and instruction codes. All instructions, addresses, and data are shifted in with the most significant bit
(MSB) first on Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3). The input data on SI or IOs is
latched on the rising edge of Serial Clock (SCK) for normal mode and both of rising and falling edges for DTR
mode after Chip Enable (CE#) is driven low (VIL). Every instruction sequence starts with a one-byte instruction
code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type
of instruction. CE# must be driven high (VIH) after the last bit of the instruction sequence has been shifted in to
end the operation.
Table 8.1 Instruction Set
Instruction
Name
Operation
Total
Bytes
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
NORD
Normal Read
Mode
4
SPI
03h
A
<23:16>
A
<15:8>
A
<7:0>
Data out
FRD
Fast Read
Mode
5
SPI
QPI
0Bh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Data out
FRDIO
Fast Read
Dual I/O
3
SPI
BBh
A
<23:16>
Dual
A
<15:8>
Dual
A
<7:0>
Dual
AXh(1),(2)
Dual
Dual
Data out
FRDO
Fast Read
Dual Output
5
SPI
3Bh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Dual
Data out
FRQIO
Fast Read
Quad I/O
2
SPI
QPI
EBh
A
<23:16>
Quad
A
<15:8>
Quad
A
<7:0>
Quad
AXh(1), (2)
Quad
Quad
Data out
FRDTR
Fast Read
DTR Mode
5
SPI
QPI
0Dh
A
<23:16>
A
<15:8>
A
<7:0>
Dummy(1)
Byte
Dual
Data out
FRDDTR
Fast Read
Dual I/O DTR
3
SPI
BDh
A
<23:16>
Dual
A
<15:8>
Dual
A
<7:0>
Dual
AXh(1), (2)
Dual
Dual
Data out
FRQDTR
Fast Read
Quad I/O DTR
5
SPI
QPI
EDh
A
<23:16>
A
<15:8>
A
<7:0>
AXh(1), (2)
Quad
Quad
Data out
PP
Input Page
Program
4
+ 256
SPI
QPI
02h
A
<23:16>
A
<15:8>
A
<7:0>
PD
(256byte)
PPQ
Quad Input
Page Program
4
+ 256
SPI
32h
38h
A
<23:16>
A
<15:8>
A
<7:0>
Quad PD
(256byte)
SER
Sector Erase
4
SPI
QPI
D7h
20h
A
<23:16>
A
<15:8>
A
<7:0>
BER32
(32Kb)
Block Erase
32K
4
SPI
QPI
52h
A
<23:16>
A
<15:8>
A
<7:0>
BER64
(64Kb)
Block Erase
64K
4
SPI
QPI
D8h
A
<23:16>
A
<15:8>
A
<7:0>
CER
Chip Erase
1
SPI
QPI
C7h
60h
WREN
Write Enable
1
SPI
QPI
06h
WRDI
Write Disable
1
SPI
QPI
04h
RDSR(5)
Read Status
Register
2
SPI
QPI
05h
SR
WRSR
Write Status
Register
2
SPI
QPI
01h
WSR
Data
RDFR(5)
Read Function
Register
2
SPI
QPI
48h
Data
out
IS25LP032/064/128
Integrated Silicon Solution, Inc.- www.issi.com 20
Rev. D
10/03/2014
Instruction
Name
Operation
Total
Bytes
Mode
Byte0
Byte1
Byte2
Byte3
Byte4
Byte5
Byte6
WRFR
Write Function
Register
2
SPI
QPI
42h
WFR
Data
QIOEN
Enter
QPI mode
1
SPI
35h
QIODI
Exit
QPI mode
1
QPI
F5h
PERSUS
Suspend during
program/erase
1
SPI
QPI
75h
B0h
PERRSM
Resume
program/erase
1
SPI
QPI
7Ah
30h
DP
Deep Power
Down
1
SPI
QPI
B9h
RDID(5),
RDPD
Read ID /
Release
Power Down
4
SPI
QPI
ABh
XXh(3)
XXh(3)
XXh(3)
ID7-ID0
SRP
Set Read
Parameters
4
SPI
QPI
C0h
Data in
RDJDID(5)
Read JEDEC
ID Command
1
SPI
9Fh
MF7-MF0
ID15-ID8
ID7-ID0
RDMDID(5)
Read
Manufacturer
& Device ID
4
SPI
QPI
90h
XXh(3)
XXh(3)
00h
MF7-MF0
ID7-ID0
01h
ID7-ID0
MF7-MF0
RDJDIDQ(5)
Read JEDEC ID
QPI mode
4
QPI
AFh
MF7-MF0
ID15-ID8
ID7-ID0
RDUID
Read
Unique ID
4
SPI
QPI
4Bh
A(4)
<23:16>
A(4)
<15:8>
A(4)
<7:0>
Dummy
Byte
Data out
RDSFDP
SFDP Read
5
SPI
QPI
5Ah
A
<23:16>
A
<15:8>
A
<7:0>
Dummy
Byte
Data out
RSTEN
Software
Reset
Enable
1
SPI
QPI
66h
RST
Software Reset
1
SPI
QPI
99h
IRER
Erase
Information
Row
4
SPI
QPI
64h
A
<23:16>
A
<15:8>
A
<7:0>
IRP
Program
Information
Row
4
+ 256
SPI
QPI
62h
A
<23:16>
A
<15:8>
A
<7:0>
PD
(256byte)
IRRD
Read
Information
Row
4
SPI
QPI
68h
A
<23:16>
A
<15:8>
A
<7:0>
Dummy
Byte
Data out
SECUN-
LOCK
Sector Unlock
4
SPI
QPI
26h
A
<23:16>
A
<15:8>
A
<7:0>
SECLOCK
Sector Lock
1
SPI
QPI
24h
Notes:
1. The number of dummy cycles depends on the value setting in the Table 6.9 Read Dummy Cycles.
2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.
3. XX means “don’t care”.
4. A<23:9> are “don’t care” and A<8:4> are always “0”.
5. The maximum clock frequency is 104MHz for Vcc=2.3V~2.7V and 133MHz for Vcc=2.7V~3.6V.
IS25LP032/064/128
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Rev. D
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8.1 NORMAL READ OPERATION (NORD, 03h)
The NORMAL READ (NORD) instruction is used to read memory contents of the IS25LP032/064/128 at a
maximum frequency of 50MHz.
The NORD instruction code is transmitted via the Sl line, followed by three address bytes (A23 - A0) of the first
memory location to be read. A total of 24 address bits are shifted in. The first byte addressed can be at any
memory location. Upon completion, any data on the Sl will be ignored. Refer to Table 8.2 for the related
Address Key.
The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole
memory array, can be read out in one NORMAL READ instruction. The address is automatically incremented by
one after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high
(VIH) after the data comes out. When the highest address of the device is reached, the address counter will roll
over to the 000000h address, allowing the entire memory to be read in one continuous READ instruction.
If the NORMAL READ instruction is issued while an Erase, Program or Write operation is in process (WIP=1)
the instruction is ignored and will not have any effects on the current operation.
Table 8.2 Address Key
Address
IS25LP032
IS25LP064
IS25LP128
AN (AMSB A0)
A23 - A0 (A23,A22=X)
A23 - A0 (A23=X)
A23 - A0
X=Don’t Care
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Rev. D
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Figure 8.1 Normal Read Sequence
7 6
CE#
SCK
SI
532
SO 410
Data Out 1
Instruction = 03h 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
48
765324 10
tV
Data Out 2
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Rev. D
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8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte from
the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling
edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST
READ instruction is terminated by driving CE# high (VIH). If the FAST READ instruction is issued while an
Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
7 6
CE#
SCK
SI
532
SO 410
Data Out
Instruction = 0Bh 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
48
...
tV
Dummy Byte
IS25LP032/064/128
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Rev. D
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FAST READ QPI OPERATION (FRD QPI, 0Bh)
The FAST READ QPI (FRD QPI) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ QPI instruction code (2 clocks) is followed by three address bytes (A23-A06clocks) and
dummy cycles, transmitted via the QPI line, with each bit latched-in during the rising edge of SCK. Then the first
data byte addressed is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT, during
the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ QPI instruction. The FAST
READ QPI instruction is terminated by driving CE# high (VIH). If the FAST READ QPI instruction is issued while
an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored without affecting the current
cycle.
Figure 8.3 Fast Read Sequence, QPI Mode
0Bh
CE#
SCK
IO[3:0]
6 Dummy Cycles
Address
0 1 2 3 4 5 6 7 8 9
...
13 14 15 16 17
Mode 3
Mode 0
23:20 7:4 3:0 7:4 3:0
Data 1 Data 2
19:16 15:12 11:8 7:4 3:0
18
tV
Instruction
Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.9 Read Dummy
Cycles.
IS25LP032/064/128
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Rev. D
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8.3 HOLD OPERATION
HOLD# is used in conjunction with CE# to select the IS25LP032/064/128. When the device is selected and a
serial sequence is underway, HOLD# can be used to pause the serial communication with the master device
without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume
serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD).
Inputs to SlO will be ignored while SO is in the high impedance state.
Note: HOLD is not supported in DTR mode or with QE=1.
Timing graph can be referenced in AC Parameters Figure 9.3
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)
The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directly
from the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 A0) and dummy cycles, transmitted via
the IO0 and IO1 lines, with each pair of bits latched-in during the rising edge of SCK. The address MSB is input
on IO1, the next bit on IO0, and this shift pattern continues to alternate between the two lines. Depending on the
usage of AX read operation mode, a mode byte may be located after address input.
The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK. The MSB is output on IO1, while simultaneously the
second bit is output on IO0. Figure 8.4 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8
bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as
described in Figure 8.5. When the code is different from AXh (X: don’t care), the device exits the AX read
operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycle in Table 6.9 includes number of mode bit cycles. If dummy cycles is configured as 4 cycles, data output
will starts right after mode bit applied.
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.
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Figure 8.4 Fast Read Dual I/O Sequence (with command decode cycles)
7 5 3 751 31
Data Out 1
Instruction = 03h 22
CE#
SCK
206 4
3-byte Address
High Impedance
20 18 ...
0 1 2 3 4 5 6 7 8 9 10 ... 18 19 20 21
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Mode 3
Mode 0
38
tV
23 317 5
21 19 ...
IO0
IO1
3 1
2 0 6 4 2640 20
Mode Bits
7531
6420
... ... ...
... ... ...
CE#
SCK
IO0
IO1
Data Out 2 Data Out 3
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are
different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9. Read Dummy Cycles.
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Figure 8.5 Fast Read Dual I/O Sequence (without command decode cycles)
22
CE#
SCK
20
3-byte Address
20 18 ...
0 1 2 3 ... 11 12 13 14 15 16 17 18 19 20 21
Mode 3
Mode 0
23 31
21 19 ...
IO0
IO1
Mode Bits
...
...
64
75
20
31
Data Out
tV
64
75
20
31
...
...
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits are
different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
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8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)
The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.
The FRDO instruction code is followed by three address bytes (A23 A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit
latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO and SIO lines,
with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is
output on SO, while simultaneously the second bit is output on SIO.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction is
terminated by driving CE# high (VIH). If the FRDO instruction is issued while an Erase, Program or Write cycle is in
process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle.
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Rev. D
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Figure 8.6 Fast Read Dual-Output Sequence
CE#
SCK
75
Data Out 1
Instruction = 3Bh 23
CE#
SCK
321 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
48
tV
IO0
IO1
64
3175
2064
31...
20...
Data Out 2
IO0
IO1
8 Dummy Cycles
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8.6 FAST READ QUAD I/O OPERATION (FRQIO, EBh)
The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be
executed directly from the SPI in some applications.
The FRQIO instruction code is followed by three address bytes (A23 A0) and dummy cycles, transmitted via
the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of SCK. The
address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue to shift
in alternating on the four. Depending on the usage of AX read operation mode, a mode byte may be located
after address input.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits
shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3,
while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.7 illustrates the
timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented after each
byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consists of 8
bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to
M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it
enables the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as
described in Figure 8.8. When the code is different from AXh (X: don’t care), the device exits the AX read
operation. After finishing the read operation, device becomes ready to receive a new command. SPI or QPI
mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy
cycle in Table 6.9 includes number of mode bit cycles. If dummy cycles is configured as 6 cycles, data output
will starts right after mode bits and 4 additional dummy cycles are applied
If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
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Figure 8.7 Fast Read Quad I/O Sequence (with command decode cycles)
CE#
SCK
51
Data Out 1
Instruction = EBh 20
CE#
SCK
40 4 0
3-byte Address
High Impedance
16 12 8
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Mode 3
Mode 0
32
tV
IO0
IO1
40
5151
4040
51
40
IO0
IO1
21 51 5 1
17 13 9
22 62 6 2
18 14 10
23 73 7 3
19 15 11
Mode Bits
IO2
IO3
62626262
73737373
Data Out 2 Data Out 3 Data Out 4
IO2
IO3
1
0
51...
40...
262...
373...
5
4
6
7
6 Dummy Cycles Data Out 5 Data Out 6
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
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Figure 8.8 Fast Read Quad I/O Sequence (without command decode cycles)
20
CE#
SCK
404 0
3-byte Address
16 12 8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
IO0
IO1 21 515 1
17 13 9
22 626 2
18 14 10
23 737 3
19 15 11
Mode Bits
IO2
IO3
51
40
51
40
6262
7373
...
...
...
...
Data Out 1 Data Out 2
16
tV
Dummy Byte
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.10 Read Dummy Cycles.
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8.7 PAGE PROGRAM OPERATION (PP, 02h)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that is write-
protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line.
Program operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be
executed. The internal control logic automatically handles the programming voltages and timing. During a
program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of
the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has
completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
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Figure 8.9 Page Program Sequence
Instruction = 02h23
CE#
SCK
SI 76
SO
7
3-byte Address
High Impedance
22 ... 0
Data In 1 Data In 256
0 1 ... 7 8 9 ... 31 32 33 ... 39 ...
2079
...
2086
Mode 3
Mode 0
... 0... ... 0
2087
Figure 8.10 Page Program Sequence (QPI)
02h
CE#
SCK
IO[3:0]
Address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
23:20 7:4 3:0 7:4 3:0
Data In 1 Data In 2
19:16 15:12 11:8 7:4 3:0
16
7:4 3:0 7:4 3:0
Data In 3 Data In 4
...
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8.8 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a
single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must
be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input
Page Program instruction which attempts to program into a page that is write-protected will be ignored. Before
the execution of Quad Input Page Program instruction, the QE bit in the status register must be set to 1 and
the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are
input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought
high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic
automatically handles the programming voltages and timing. During a program operation, all instructions will be
ignored except the RDSR instruction. The progress or completion of the program operation can be determined
by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is
still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the
previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page.
The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the whole sector or block.
Figure 8.11 Quad Input Page Program operation
Instruction = 32h/38h 23
CE#
SCK
404 0
3-byte Address
High Impedance
22 ... 0
0 1 2 3 4 5 6 7 8 9 31 32 33 34 35
Mode 3
Mode 0
IO0
IO1 51 5 1
62 6 2
73 7 3
Data In 2
IO2
IO3
...
Data In 1
...
...
...
...
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8.9 ERASE OPERATION
The memory array of the IS25LP032/064/128 is organized into uniform 4 Kbyte sectors or 32K/64 Kbyte uniform
blocks (a block consists of sixteen adjacent sectors).
Before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to
“1”). In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase
(BER) and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without
affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation
erases the whole memory array of a device. A sector erase, block erase, or chip erase operation can be
executed prior to any programming operation.
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8.10 SECTOR ERASE OPERATION (SER, D7h/20h)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after
the completion of sector an erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire
instruction sequence The SER instruction code, and three address bytes are input via SI. Erase operation will
start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and
timing. Refer to Figure 8.12-8.13 for the Sector Erase Sequence.
During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction.
The progress or completion of the erase operation can be determined by reading the WIP bit in the Status
Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is
“0”, the erase operation has been completed.
Figure 8.12 Sector Erase Sequence
Instruction = D7h/20h 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
Mode 0
Figure 8.13 Sector Erase Sequence (QPI)
D7h/20h
CE#
SCK
IO[3:0]
Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
23:20 19:16 15:12 11:8 7:4 3:0
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8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64 Kbyte block of the IS25LP032/064/128. Before the execution of
a BER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL
is reset automatically after the completion of a block erase operation.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic
automatically handles the erase voltage and timing. Refer to Figure 8.14-8.17 for the Block Erase Sequence.
Figure 8.14 Block Erase (64k) Sequence
Instruction = D8h 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
Mode 0
Figure 8.15 Block Erase (64k) Sequence (QPI)
D8h
CE#
SCK
IO[3:0]
Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
23:20 19:16 15:12 11:8 7:4 3:0
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Figure 8.16 Block Erase Sequence (32K)
Instruction = 52h 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
Mode 0
Figure 8.17 Block Erase (32K) Sequence (QPI)
52h
CE#
SCK
IO[3:0]
Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
23:20 19:16 15:12 11:8 7:4 3:0
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8.12 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array of a IS25LP032/064/128. Before the execution
of CER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL
is automatically reset after completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,
otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing. Refer to Figure 8.18-8.19 for the Chip Erase Sequence.
Figure 8.18 Chip Erase Sequence
Instruction = C7h/60h
CE#
SCK
SIO
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.19 Chip Erase Sequence (QPI)
C7h/60h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
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8.13 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the
IS25LP032/064/128 is reset to the write protected state after power-up. The WEL bit must be write enabled
before any write operation, including sector, block erase, chip erase, page program, write status register, and
write configuration register operations. The WEL bit will be reset to the write-protect state automatically upon
completion of a write operation. The WREN instruction is required before any above operation is executed.
Figure 8.20 Write Enable Sequence
Instruction = 06h
CE#
SCK
SIO
Address
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.21 WRITE ENABLE OPERATION (QPI)
06h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
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8.14 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI
instruction is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.22 Write Disable Sequence
Instruction = 04h
CE#
SCK
SIO
0 1 2 3 4 5 6 7
Mode 3
Mode 0
SO High Impedance
Figure 8.23 WRITE DISABLE OPERATION (QPI)
04h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
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8.15 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of a
program, erase or write status register operation, all other instructions will be ignored except the RDSR
instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of
Status Register.
Figure 8.24 Read Status Register Sequence
Instruction = 05h
7
CE#
SCK
SI
32
SO 1 0
Data Out
6 5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
4
tV
Figure 8.25 RDSR COMMAND (READ STATUS REGISTER) OPERATION (QPI)
05h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
tV
Data Out
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8.16 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and
status register write protection features by writing “0”s or “1”s into the non-volatile BP3, BP2, BP1, BP0, QE and
SRWD bits.
Figure 8.26 Write Status Register Sequence
Instruction = 01h
CE#
SCK
SI
SO
Data In
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
7321 0
6 5 4
High Impedence
Figure 8.27 WRSR COMMAND (WRITE STATUS REGISTER) OPERATION (QPI)
01h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
Data In
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8.17 READ FUNCTION REGISTER OPERATION (RDFR, 48h)
The Read Function Register (RDFR) instruction provides access to the Erase/Program suspend register. During
the execution of a program, erase or write status register suspend, which can be used to check the suspend
status.
Figure 8.28 Read Function Register Sequence
Instruction = 48h
7
CE#
SCK
SI
32
SO 1 0
Data Out
6 5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
4
tV
Figure 8.29 READ FUNCTION REGISTER OPERATION (QPI) RDFR
48h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
tV
Data Out
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8.18 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)
The Write Function Register (WRFR) instruction allows the user to select top or bottom block area by writing into
TBS bit and lock or unlock the information row by writing “0”s (IR lock) or “1”s (IR unlock) into IRL3, IRL2, IRL1,
IRL0.
Figure 8.30 Write Function Register Sequence
Instruction = 42h
CE#
SCK
SI
SO
Data In
0 1 2 3 4 5 6 78 9 10 11 12 13 14 15
Mode 3
Mode 0
732 1 0
6 5 4
High Impedence
Figure 8.31 WRFR COMMAND (WRITE Function REGISTER) OPERATION (QPI)
42h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
Data In
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8.19 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QIOEN,35h; QIODI,F5h)
The Enter Quad I/O (QIOEN) instruction, 35h, enables the Flash device for QPI bus operation. Upon completion
of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power cycle or an Exit
Quad I/O instruction is sent to device.
Figure 8.32 Enter Quad Peripheral Interface OPERATION (QPI)
Instruction = 35h
CE#
SCK
SI
SO High Impedence
0 1 2 3 4 5 6 7
Mode 3
Mode 0
Figure 8.33 Exit Quad Peripheral Interface (QPI) mode OPERATION
The Exit Quad I/O instruction, F5h, resets the device to 1-bit SPI protocol operation. To execute an Exit Quad
I/O operation, the host drives CE# low, sends the Exit Quad I/O command cycle, then drives CE# high. The
device just accepts SQI (2 clocks) command cycles.
F5h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
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8.20 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector-Erase, Block-Erase or Page-Program operations to conduct other
operations. B0h command for suspend and 30h for resume will be used. (SPI/QPI all acceptable) Function
register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing: 10s.
Resume to another suspend timing: 400µs (recommendation).
PROGRAM/ERASE SUSPEND DURING SECTOR-ERASE OR BLOCK-Erase (PERSUS 75h/B0h)
After erase suspend, WEL bit will be disabled, therefore only read related, resume and reset commands will be
accepted (03h, 0Bh, BBh, 3Bh, EBh, 0Dh, BDh, EDh, 05h, 48h, 7Ah/30h, ABh, 9Fh, 90h, AFh, 4Bh, 5Ah, 00h,
66h and 99h, 68h).
To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (B0H), then drives CE# high. The Function register indicates that the erase has been
suspended by changing the ESUS bit from ‘0’ to ‘1,’ but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait
the specified time tSUS. When ESUS bit is issued, the Write Enable Latch (WEL) bit will be reset.
PROGRAM/ERASE SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
Program suspend allows the interruption of all program operations.
After a program suspend command, WEL bit will be disabled, only read related, resume and reset command
can be accepted (03h, 0Bh, BBh, 3Bh, EBh, 0Dh, BDh, EDh, 05h, 48h, 7Ah/30h, ABh, 9Fh, 90h, AFh, 4Bh, 5Ah,
00h, 66h and 99h, 68h).
To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend
command cycle (B0H), then drives CE# high. The Function register indicates that the programming has been
suspended by changing the PSUS bit from ‘0’ to ‘1,’ but the device will not accept another command until it is
ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait
the specified time tSUS.
PROGRAM/ERASE RESUME (PERRSM 7A/30h)
Program/Erase Resume restarts a Program/Erase command that was suspended, and changes the suspend
status bit in the (ESUS or PSUS bits) back to ‘0’. To execute a Program/Erase Resume operation, the host
drives CE# low, sends the Program/Erase Resume command cycle (30H), then drives CE# high. A cycle is two
nibbles long, most significant nibble first. To determine if the internal, self-timed Write operation completed, poll
the WIP bit in the Status register, or wait the specified time tSE, tBE or tPP for Sector- Erase, Block-Erase, or
Page-Programming, respectively. The total write time before suspend and after resume will not exceed the
uninterrupted write times tSE, tBE or tPP.
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8.21 DEEP POWER DOWN (DP, B9h)
8.22 The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption
(enter into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the
Power-down mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction
is initiated by driving the CE# pin low and shifting the instruction code “B9h” as shown in the figure 8.34. The
CE# pin must be driven high after the instruction has been latched, or Power-down mode will not engage. Once
CE# pin driven high, the Power-down mode will be entered within the time duration of tDP. While in the Power-
down mode only the Release from Power-down / RDID instruction, which restores the device to normal
operation, will be recognized. All other instructions are ignored, including the Read Status Register instruction
which is always available during normal operation. Ignoring all but one instruction makes the Power Down state
a useful condition for securing maximum write protection. It is available in both SPI and QPI mode.
Figure 8.34 Enter Deep Power Down Mode Operation. (SPI)
Instruction = B9h
CE#
SCK
SI ...
0 1 2 3 4 5 6 7
Mode 3
Mode 0
tDP
Figure 8.35 Deep Power Down Sequence (QPI)
B9h
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
tDP
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8.22 RELEASE DEEP POWER DOWN (RDPD, ABh)
The Release Deep Power-down/Read Device ID instruction is a multi-purpose command. To release the device
from the Power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code
“ABh” and driving CE# high as shown in Figure 8.36, 8.37.
Releasing the device from Power-down mode will take the time duration of tRES1 before normal operation is
restored and other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If
the Release Deep Power-down / RDID instruction is issued while an Erase, Program or Write cycle is in
progress (WIP=1) the instruction is ignored and will not have any effects on the current cycle.
Figure 8.36 Release Power Down Sequence (SPI)
Instruction = ABh
CE#
SCK
SI ...
0 1 2 3 4 5 6 7
Mode 3
Mode 0
tRES1
Figure 8.37 Release Power Down Sequence (QPI)
ABh
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
tRES1
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8.23 SET READ PARAMETERS OPERATION (SRP, C0h)
Set Read Operational Driver Strength
This device supports configurable Operational Driver Strengths in both SPI and QPI modes by setting three bits
within the READ Register (ODS0, ODS1, ODS3). To set the ODS bits the SRP operation (C0h) instruction is
required. The device’s driver strength can be reduced as low as 12.50% of full drive strength. Details regarding
the driver strength can be found in table 6.10.
Note: The default driver strength is set to 50%
Figure 8.38 Set Read Parameters Operation.
Instruction = C0h 7
CE#
SCK
SI 32
SO
1 0
Data In
6 5
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
4
High Impedance
Figure 8.39 Set Read Parameters Operation. (QPI)
C0h
0 1
Mode 3
Mode 0
2 3
7:4 3:0
CE#
SCK
IO[3:0]
Data In
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Read with “8/16/32/64-Byte Wrap Around”
The device is capable of burst read with wrap around in both SPI and QPI mode. The size of burst length is
configurable by using P0, P1, and P2 bits in READ register. P2 bit (Wrap enable) enables the burst mode
feature. P0 and P1 define the size of burst. Burst lengths of 8, 16, 32, and 64 bytes are supported. By default,
address increases by one up through the entire array. By setting the burst length, the data being accessed can
be limited to the length of burst boundary within a 256 byte page. The first output will be the data at the initial
address which is specified in the instruction. Following data will come out from the next address within the burst
boundary. Once the address reaches the end of boundary, it will automatically move to the first address of the
boundary. CS# high will terminate the command.
For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from
address 00h and continue to 01h,..,07h, 00h, 01h… until CS# terminates the operation. If burst length of 8 and
initial address being applied is FEh(254d), following byte output will be from address FEh and continue to FFh,
F8h, F9h, FAh, FBh, FCh, FDh, and repeat from FEh until CS# terminates the operation.
The command, “SET READ PARAMETERS OPERATION (C0h)”, is used to configure the burst length. If the
following data input is one of “00h”,”01h”,”02h”, and ”03h”, the device will be in default operation mode. It will be
continuous burst read of the whole array. If the following data input is one of “04h”,”05h”,”06h”, and ”07h”, the
device will set the burst length as 8,16,32 and 64 respectively.
To exit the burst mode, another “C0hcommand is necessary to set P2 to 0. Otherwise, the burst mode will be
retained until either power down or reset operation. To change burst length, another “C0hcommand should be
executed to set P0 and P1 (Detailed information in Table 6.7 Burst Length Data). All read commands operate in
burst mode once the READ register is set to enable burst mode.
Refer to Figures 8.38 and 8.39 for instruction sequence.
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8.24 READ PRODUCT IDENTIFICATION (RDID, ABh)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI
and QPI modes. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit
Electronic Signature, whose values are shown as table of ID Definitions.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising
SCK edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDID instruction is ended by driving CE# high. The Device ID (ID7-ID0) outputs
repeatedly if additional clock cycles are continuously sent to SCK while CE# is at low.
Table 8.3 Product Identification
Manufacturer ID
(MF7-MF0)
ISSI Serial Flash
9Dh
Instruction
ABh
90h
9Fh
Device Density
Device ID (ID7-ID0)
Memory Type + Capacity
(ID15-ID0)
32Mb
15h
6016h
64Mb
16h
6017h
128Mb
17h
6018h
Figure 8.40 Read Product Identification Sequence
Instruction = ABh
Device ID
(ID7-ID0)
CE#
SCK
SI
Device ID
(ID7-ID0)
SO
Data Out
0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47
Mode 3
Mode 0
3 Dummy Cyles
tV
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Figure 8.41 Read Product Identification Sequence (QPI)
ABh
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
2 3
7:4 3:0
4 5 ... 9 10 11 12 13
6 Dummy Cyles Device ID
(ID7-ID0) Device ID
(ID7-ID0)
tV
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8.25 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to
Table 8.3 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh in
SPI mode, AFh in QPI mode) is input, the Manufacturer ID is shifted out MSB first followed by the 2-byte
electronic ID (ID15-ID0) that indicates memory type and density, one bit at a time. Each bit is shifted out during
the falling edge of SCK. If CE# stays low after the last bit of the 2-byte electronic ID, the Manufacturer ID and 2-
byte electronic ID will loop until CE# is pulled high.
Figure 8.42 Read Product Identification by JEDEC ID READ Sequence in SPI mode
Instruction = 9Fh
Memory Type
(ID15-ID8)
CE#
SCK
SI
Capacity
(ID7-ID0)
SO
Data Out
0 1 ... 7 8 9 ... 15 16 17 ... 23 24 25 ... 31
Mode 3
Mode 0
Manufacturer ID
(MF7-MF0)
tV
Figure 8.43 RDJDIDQ COMMAND (Read JEDEC ID in QPI Mode) OPERATION
AFh
CE#
SCK
IO[3:0]
0 1
Mode 3
Mode 0
2 3
7:4 3:0
4 5
7:4 3:0
6 7
7:4 3:0
MF7-MF0 ID15-ID8 ID7-ID0
tV
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8.26 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)
The Read Product Identification (RDID) instruction allows the user to read the manufacturer and product ID of
devices. Refer to Table 8.3 Product Identification for manufacturer ID and device ID. The RDID instruction code
is followed by two dummy bytes and one byte address (A7~A0), each bit being latched-in on SI during the rising
edge of SCK. If one byte address is initially set as A0 = 0, then the manufacturer ID (9Dh) is shifted out on SO
with the MSB first followed by the device ID7- ID0. Each bit shifted out during the falling edge of SCK. If one
byte address is initially set as A0 = 1, then Device ID7-ID0 will be read first followed by the Manufacture ID
(9Dh). The manufacture and device ID can be read continuously alternating between the two until CE# is driven
high.
Figure 8.44 Read Product Identification by RDMDID READ Sequence
Instruction = 90h
Manufacturer ID
(MF7-MF0)
CE#
SCK
SI
Device ID
(ID7-ID0)
SO
Data Out
0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47
Mode 3
Mode 0
3 Byte Address
tV
Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacture ID (MF7-MF0) 1-byte device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte device ID (ID7-ID0) 1-byte Manufacture ID (MF7-MF0)
2. The Manufacture and Device ID can be read continuously and will alternate from one to the other until CE# pin is pulled high.
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8.27 READ UNIQUE ID NUMBER (RDUID, 4Bh)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is
unique to the device. The Id number can be used in conjunction with user software methods to help prevent
copying or cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the
instruction code (4Bh) followed by 3 address bytes and a dummy byte. After which, the 16-byte ID is shifted out
on the falling edge of SCK as shown below.
Note: 16 bytes of data will repeat as long as CE# is low and SCK is toggling.
Figure 8.45 RDUID COMMAND OPERATION
Instruction = 4Bh Dummy Byte
CE#
SCK
SI
SO
0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47
Mode 3
Mode 0
3 Byte Address
Data Out
tV
Table 8.4 Unique ID Addressing
A[23:16]
A[15:9]
A[8:4]
A[3:0]
XXh
XXh
00h
0h Byte address
XXh
XXh
00h
1h Byte address
XXh
XXh
00h
2h Byte address
XXh
XXh
00h
XXh
XXh
00h
Fh Byte address
Note: XX means “don’t care”.
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8.28 READ SFDP OPERATION (RDSFDP, 5Ah)
The Serial Flash Discoverable Parameters (SFDP) standard provides a consistent method of describing the
functions and features of serial Flash devices in a standard set of internal parameter tables. These parameters
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. For more details please refer to the JEDEC Standard JESD216A (Serial Flash
Discoverable Parameters).
The sequence of issuing RDSFDP instruction is same as FAST_READ: CE# goes low Send RDSFDP
instruction (5Ah) Send 3 address bytes on SI pin Send 1 dummy byte on SI pin Read SFDP code on
SO End RDSFDP operation by driving CE# high at any time during data out. Refer to ISSI’s Application note
for SFDP table. The data at the addresses that are not specified in SFDP table are undefined.
Figure 8.46 RDSFDP COMMAND (Read SFDP) OPERATION
Instruction = 5Ah Dummy Byte
CE#
SCK
SI
SO
0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47
Mode 3
Mode 0
3 Byte Address
Data Out
tV
8.29 NO OPERATION (NOP, 00h)
The No Operation command solely cancels a Reset Enable command and has no impact on any other
commands. It is available in both SPI and QPI modes. To execute a NOP, the host drives CE# low, sends the
NOP command cycle (00H), then drives CE# high.
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8.30 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE RESET
The Software Reset operation is used as a system reset that puts the device in normal operating mode. During
the Reset operation, the value of volatile registers will default back to the value in the corresponding non-volatile
register. This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The operation
requires the Reset-Enable command followed by the Reset command. Any command other than the Reset
command after the Reset-Enable command will disable the Reset-Enable.
Execute the CE# pin low sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives
CE# low again, sends the Reset command (99h), and pulls CE# high.
Only for the dedicated parts that have the RESET# pin, Hardware Reset function is available. The RESET# pin
will be solely applicable in SPI mode and when the QE bit is disabled. The RESET# pin has the highest priority
among all the input signals and will reset the device to its initial power-on state regardless of the state of all
other pins (CS, IOs, SCK and WP#).
In order to activate Hardware Reset, the RESET# pin must be driven low for a minimum period of tRESET (1µs).
Drive RESET# low for a minimum period of tRESET will interrupt any on-going internal and external operations,
release the device from deep power down mode1, disable all input signals, force the output pin enter a state of
high impedance, and reset all the read parameters. If the RESET# pulse is driven for a period shorter than 1µs,
it may still reset the device, however the 1µs minimum period is recommended to ensure the reliable operation.
The required wait time after activating a HW Reset before the device will accept another instruction (tHWRST) is
the same as the maximum value of tSUS (100µs).
The Software/Hardware Reset during an active Program or Erase operation aborts the operation, which can
result in corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset
timing may vary. Recovery from a Write operation will require more latency than recovery from other operations.
Note 1: The Status and Function Registers remain unaffected.
Figure 8.47 SOFTWARE RESET ENABLE, SOFTWARE RESET OPERATIONS (RSTEN, 66h + RST, 99h)
Instruction = 66h
CE#
SCK
SIO
0 1
Mode 3
Mode 0
2 3 4 5 6 7
Instruction = 99h
8 9 10 11 12 13 14 15
SO High Impedance
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8.31 SECURITY INFORMATION ROW
The security information row is comprised of an additional 4 x 256 bytes of programmable information. The
security bits can be reprogrammed by the user. Any program security instruction issued while an erase, program
or write cycle is in progress is rejected without having any effect on the cycle that is in progress.
Table 8.5 Information Row Address
Address Assignment
A[23:16]
A[15:8]
A[7:0]
IRL0(Information row lock0)
00h
00h
Byte address
IRL1
00h
10h
Byte address
IRL2
00h
20h
Byte address
IRL3
00h
30h
Byte address
Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.
When Function Register bit IRLx = ’0’, the 256 bytes of the programmable memory array can be programmed.
When Function Register bit IRLx = ‘1’, the 256 bytes of the programmable memory array function as read only.
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8.32 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to the
operation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is
automatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device Send IRER instruction code Send
three address bytes Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE#
is pulled high, Erase operation will begin immediately. The internal control logic automatically handles the erase
voltage and timing. Refer to Figure 8.48 for IRER Sequence.
Figure 8.48 IRER COMMAND (Information Row Erase) OPERATION
Instruction = 64h 23
CE#
SCK
SI 32
SO
1 0
3-byte Address
High Impedance
22 21 ...
0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31
Mode 3
Mode 0
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8.33 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)
The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory
in a single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input.
Three address bytes has to be input as specified in the section 8.31 SECURITY INFORMAION ROW. Program
operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The internal
control logic automatically handles the programming voltages and timing. During a program operation, all
instructions will be ignored except the RDSR instruction. The progress or completion of the program operation
can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the
program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The
previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap
around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all
other bytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s.
A byte cannot be reprogrammed without first erasing the corresponding Information Row array which is one
of IR0~3.
Figure 8.49 IRP COMMAND (Information Row Program) OPERATION
Instruction = 62h 23
CE#
SCK
SI 76
SO
7
3-byte Address
High Impedance
22 ... 0
Data In 1 Data In 256
0 1 ... 7 8 9 ... 31 32 33 ... 39 ...
2079
...
2086
Mode 3
Mode 0
... 0... ... 0
2087
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8.34 INFORMATION ROW READ OPERATION (IRRD, 68h)
The IRRD instruction is used to read memory data at up to a 133MHz clock in the voltage range, 2.7V to 3.6V.
The IRRD instruction code is followed by three address bytes (A23 - A0) and a dummy byte, transmitted via the
SI line, with each bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out
on the SO line, with each bit shifted out at a maximum frequency fCT, during the falling edge of SCK.
The address is automatically incremented after each byte of data is shifted out. When the highest address is
reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a
single IRRD instruction. The IRRD instruction is terminated by driving CE# high (VIH). If a IRRD instruction is
issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored and will not have
any effects on the current cycle
Figure 8.50 IRRD COMMAND (Information Row Read) OPERATION
Instruction = 68h Dummy Byte
CE#
SCK
SI
SO
0 1 ... 7 8 9 ... 31 32 33 ... 39 40 41 ... 47
Mode 3
Mode 0
3 Byte Address
Data Out
tV
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8.35 FAST READ DTR MODE OPERATION (FRDTR, 0Dh)
The FRDTR instruction is for doubling the data in and out. Signals are triggered on both rising and falling edge
of clock. The address is latched on both rising and falling edge of SCK, and data of each bit shifts out on both
rising and falling edge of SCK at a maximum frequency fC2. The 2-bit address can be latched-in at one clock,
and 2-bit data can be read out at one clock, which means one bit at the rising edge of clock, the other bit at the
falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out in a single FRDTR instruction. The
address counter rolls over to 0 when the highest address is reached.
The sequence of issuing FRDTR instruction is: CE# goes low Sending FRDTR instruction code (1bit per
clock) 3-byte address on SI (2-bit per clock) 4 dummy clocks on SI Data out on SO (2-bit per clock)
End FRDTR operation via driving CE# high at any time during data out. (Please refer to Figure 8.51)
While a Program/Erase/Write Status Register cycle is in progress, FRDTR instruction will be rejected without
any effect on the current cycle.
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Figure 8.51 FRDTR COMMAND (Fast Read DTR Mode) OPERATION
CE#
SCK
SI
SO
Data Out 1
Instruction = 0Dh
CE#
SCK
SI
SO
3-byte Address
High Impedance
0 1 2 3 4 5 6 78 9 10 ... 19 20 21
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Mode 3
Mode 0
...
tV
23 22 21 0
76 5 43 2 1 0
Data Out 2
76 5 43 2 1 0
Data Out 3
76 5 43 2 1 0
4 Dummy
Cycles
20 19 18 17 ...
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8.36 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh)
The FRDDTR instruction enables Double Transfer Rate throughput on dual I/O of the device in read mode. The
address (interleave on dual I/O pins) is latched on both rising and falling edge of SCK, and the data (interleave
on dual I/O pins) shift out on both rising and falling edge of SCK at a maximum frequency fT2. The 4-bit address
can be latched-in at one clock, and 4-bit data can be read out at one clock, which means two bits at the rising
edge of clock, the other two bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte of data is shifted out, so the whole memory can be read out with a single FRDDTR instruction.
The address counter rolls over to 0 when the highest address is reached. Once writing FRDDTR instruction, the
following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing FRDDTR instruction is: CE# goes low Sending FRDDTR instruction (1-bit per clock)
24-bit address interleave on SIO1 & SIO0 (4-bit per clock) 2 dummy clocks (configurable) on SIO1 & SIO0
Data out interleave on SIO1 & SIO0 (4-bit per clock) End FRDDTR operation via pulling CE# high at any
time during data out (Please refer to Figure 8.52 for 2 x I/O Double Transfer Rate Read Mode Timing
Waveform).
If AXh (X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation
mode which enables subsequent FRDIO execution skips command code. It saves cycles as described in Figure
8.53. When the code is different from AXh (X is don’t care), the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command. Since the number of dummy
cycles and AX bits cycles are same in this case, X should be Hi-Z to avoid I/O contention
If the FRDDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),
the instruction will be rejected without any effect on the current cycle.
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Figure 8.52 FRDDTR (Fast Read Dual IO DTR Mode) OPERATION (with command decode cycles)
CE#
SCK
SI
SO
Instruction = BDh
CE#
SCK
SI
SO
3-byte Address
High Impedance
0 1 2 3 4 5 6 78 9 10 ... 13 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ...
Mode 3
Mode 0
...
tV
22 20 18 0
75 3 17 5 3 1 75 3 17 5 3 1 75 3 17 5 3 1
2 Dummy Cycles
23 21 19 1
Data Out
...
64 2 06 4 2 0 64 2 06 4 2 0 64 2 06 4 2 0
Data Out Data Out Data Out Data Out Data Out
...
...
16 14 12
17 15 13
10
11 75
64
31
20
Mode Bits
Mode Bits
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bits cycles are same in the above Figure, X should be Hi-Z to avoid
I/O contention.
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Figure 8.53 FRDDTR (Fast Read Dual IO DTR Mode) OPERATION (without command decode cycles)
SI
SO
3-byte Address
...
...
tV
22 20 18
75 3 17 5 3 1 75 3 1
2 Dummy Cycles
23 21 19
...
64 2 06 4 2 0 64 2 0
Data Out Data Out Data Out
...
...
16 14 12
17 15 13
10
11
SCK
0 1 2 ... 6 7 8910 11 12 13 14 15 16
Mode 3
Mode 0
CE#
7 5 3 1
6 4 2 00
1
Mode Bits
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bits cycles are same in the above Figure, X should be Hi-Z to avoid
I/O contention
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8.37 FAST READ QUAD IO DTR MODE OPERATION (FRQDTR, EDh)
The FRQDTR instruction enables Double Transfer Rate throughput on quad I/O of the device in read mode. A
Quad Enable (QE) bit of status Register must be set to "1" before sending the FRQDTR instruction. The address
(interleave on 4 I/O pins) is latched on both rising and falling edge of SCK, and data (interleave on 4 I/O pins)
shift out on both rising and falling edge of SCK at a maximum frequency fQ2. The 8-bit address can be latched-in
at one clock, and 8-bit data can be read out at one clock, which means four bits at the rising edge of clock, the
other four bits at the falling edge of clock.
The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out with a single FRQDTR instruction. The
address counter rolls over to 0 when the highest address is reached. Once writing FRQDTR instruction, the
following address/dummy/data out will perform as 8-bit instead of previous 1-bit.
The sequence of issuing FRQDTR instruction is: CE# goes low Sending FRQDTR instruction (1-bit per clock)
24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) 3 dummy clocks (configurable)
Data out interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) End FRQDTR operation by driving CE#
high at any time during data out.
If AXh (X is don’t care) is input for the mode bits during dummy cycles, the device will enter AX read operation
mode which enables subsequent FRDIO execution skips command code. It saves cycles as described in Figure
8.55. When the code is different from AXh (X is don’t care), the device exits the AX read operation. After
finishing the read operation, device becomes ready to receive a new command.
If the FRQDTR instruction is issued while a Program/Erase/Write Status Register cycle is in progress (WIP=1),
the instruction will be rejected without any effect on the current cycle.
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Figure 8.54 FRQDTR (Fast Read Quad IO DTR Mode) OPERATION (with command decode cycles)
CE#
SCK
Instruction = EDh
CE#
SCK
3-byte Address
High Impedance
0 1 2 3 4 5 6 7 8 9 10 11 12
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Mode 3
Mode 0
...
tV
20 16 12
51
21 17 13
Data
Out
...
40
IO0
IO1
IO0
22 18 14
23 19 15
8 4 0
9 5 1
10 6 2
11 7 3
3 Dummy Cycles
IO2
IO3
IO1
IO2
IO3
...
62
...
73
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
Data
Out Data
Out Data
Out
Data
Out Data
Out Data
Out
Data
Out Data
Out Data
Out
Data
Out Data
Out
13
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
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Figure 8.55 FRQDTR (Fast Read Quad IO DTR Mode) OPERATION (without command decode cycles)
CE#
SCK
3-byte Address
0 1 2 3 4 5 6 78 9 10 11
Mode 3
Mode 0
...
tV
20 16 12
51
21 17 13
Data
Out
...
40
IO0
IO1
22 18 14
23 19 15
84 0
95 1
10 6 2
11 7 3
3 Dummy Cycles
IO2
IO3
...
62
...
73
51
40
62
73
51
40
62
73
51
40
62
73
51
40
62
73
51
40
62
73
51
40
62
73
Data
Out Data
Out Data
Out
Data
Out Data
Out Data
Out
51
40
62
73
Mode Bits
12 13
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
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8.38 SECTOR LOCK/UNLOCK FUNCTIONS
SECTOR UNLOCK OPERATION (SECUNLOCK, 26h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, and
BP3 bits in the Status register. Only one sector can be enabled at any time. To enable a different sector, a
previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is
followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining
sectors within the same block remain as read-only.
In the Sector Unlock procedure, [A11:A0] must be “0” for the unlock procedure to execute properly. The chip will
regard anything else as an illegal command.
Figure 8.56 Sector Unlock Sequence
Instruction = 26h
CE#
SCK
3-byte Address
High Impedance
0 1 2 3 4 5 6 7 8 9 10 11
Mode 3
Mode 0
20 16 12
21 17 13
IO0
IO1
22 18 14
23 19 15
8 4 0
9 5 1
10 6 2
11 7 3
IO2
IO3
Notes:
1. If the number of clock cycles do not match 8 cycles (command) + 24 clocks (address), the command will be
ignored.
2. WREN (06h) must be executed before sector unlock instructions.
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SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.57 Sector Lock Sequence
Instruction = 24h
CE#
SCK
SI
SO High Impedance
0 1 2 3 4 5 6 7
Mode 3
Mode 0
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9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65oC to +150oC
Surface Mount Lead Soldering Temperature
Standard Package
240oC 3 Seconds
Lead-free Package
260oC 3 Seconds
Input Voltage with Respect to Ground on All Pins
-0.5V to VCC + 0.5V
All Output Voltage with Respect to Ground
-0.5V to VCC + 0.5V
VCC
-0.5V to +6.0V
Note:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
9.2 OPERATING RANGE
Part Number
IS25LP032/064/128
Operating Temperature (Extended Grade)
-40°C to 105°C
Operating Temperature (V Grade: Hybrid Flow)
-40°C to 125°C
Operating Temperature (Automotive Grade A1)
-40°C to 85°C
Operating Temperature (Automotive Grade A2)
-40°C to 105°C
Operating Temperature (Automotive Grade A3)
-40°C to 125°C
VCC Power Supply
2.3V (VMIN) 3.6V (VMAX) ; 3.3V (Typ)
9.3 DC CHARACTERISTICS
(Under operating range)
Symbol
Parameter
Condition
Min
Typ(2)
Max
Units
ICC1
VCC Active Read Current
VCC = VMAX at 50MHz, SO = Open
10
15
mA
ICC2
VCC Program/Erase Current
VCC = VMAX at 50MHz, SO = Open
25
40
mA
ISB1
VCC Standby Current CMOS
VCC = VMAX, CE# = VCC
10
50
µA
ISB2
Deep power down current
VCC = VMAX, CE# = VCC
5
20
µA
ILI
Input Leakage Current
VIN = 0V to VCC
1
µA
ILO
Output Leakage Current
VIN = 0V to VCC
1
µA
VIL (1)
Input Low Voltage
-0.5
0.3VCC
V
VIH (1)
Input High Voltage
0.7VCC
VCC + 0.3
V
VOL
Output Low Voltage
2.3V < VCC < 3.6V
IOL = 100 µA
0.2
V
VOH
Output High Voltage
IOH = -100 µA
VCC - 0.2
V
Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may
overshoot VCC by + 2.0 V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is -
0.5V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to
exceed 20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C
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9.4 AC MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Max
Units
CL
Load Capacitance up to 104MHz
30
pF
CL
Load Capacitance up to 133MHz
15
pF
TR,TF
Input Rise and Fall Times
5
ns
VIN
Input Pulse Voltages
0.2VCC to 0.8VCC
V
VREFI
Input Timing Reference Voltages
0.3VCC to 0.7VCC
V
VREFO
Output Timing Reference Voltages
0.5VCC
V
Figure9.1 Output test load & AC measurement I/O Waveform
OUTPUT PIN
1.8k
1.2k 15/30pf
0.8VCC
0.2VCC
Input VCC/2 AC
Measurement
Level
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9.5 AC CHARACTERISTICS
(Under operating range, refer to section 9.4 for AC measurement conditions)
Symbol
Parameter
Min
Typ(3)
Max
Units
fCT
Clock Frequency for fast read mode:
SPI, Dual, Dual I/O, Quad I/O, and QPI.
0
133
MHz
fC2, fT2, fQ2
Clock Frequency for fast read DTR:
SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and
QPI DTR.
0
66
MHz
fC
Clock Frequency for read mode SPI
0
50
MHz
tCLCH(1)
SCK Rise Time (peak to peak)
0.1
V/ns
tCHCL(1)
SCK Fall Time ( peak to peak)
0.1
V/ns
tCKH
SCK High Time
For read mode
45% fC
ns
For others
45% fCT/C2/T2/Q2
tCKL
SCK Low Time
For read mode
45% fC
ns
For others
45% fCT/C2/T2/Q2
tCEH
CE# High Time
7
ns
tCS
CE# Setup Time
6
ns
tCH
CE# Hold Time
6
ns
tDS
Data In Setup Time
Normal Mode
2
ns
DTR Mode
1.5
ns
tDH
Data in Hold Time
Normal Mode
2
ns
DTR Mode
1.5
ns
tV
Output Valid @ 133MHz (CL = 15pF)
7
ns
Output Valid @ 104MHz (CL = 30pF)
8
ns
tOH
Output Hold Time Normal Mode
2
ns
tDIS(1)
Output Disable Time
8
ns
tHD
Output Hold Time
2
ns
tHLCH
HOLD Active Setup Time relative to SCK
5
ns
tCHHH
HOLD Active Hold Time relative to SCK
5
ns
tHHCH
HOLD Not Active Setup Time relative to SCK
5
ns
tCHHL
HOLD Not Active Hold Time relative to SCK
5
ns
tLZ(1)
HOLD to Output Low Z
12
ns
tHZ(1)
HOLD to Output High Z
12
ns
tEC
Sector Erase Time (4Kbyte)
45
300
ms
Block Erase Time (32Kbyte)
0.15
0.75
s
Block Erase time (64Kbyte)
0.3
1.5
s
Chip Erase Time (32Mb)
8
23
s
Chip Erase Time (64Mb)
16
45
s
Chip Erase Time (128Mb)
30
90
s
tPP
Page Program Time
0.2
1.0
ms
tVCE
Vcc(min) to CE# Low
1
ms
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Rev. D
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Symbol
Parameter
Min
Typ(3)
Max
Units
tRES1(1)
Release deep power down
3
µs
tDP(1)
Deep power down
3
µs
tW
Write Status Register time
2
15
ms
tSUS(1)
Suspend to read ready
100
µs
tSRST(1)
Software Reset recovery time
100
µs
tRESET(1),(4)
RESET# pin low pulse width
1(2)
µs
tHWRST(1),(4)
Hardware Reset recovery time
100
µs
Notes:
1. These parameters are characterized and not 100% tested.
2. If the RESET# pulse is driven for a period shorter than 1µs (tRESET minimum), it may still reset the device, however
the 1µs minimum period is recommended to ensure reliable operation.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at
VCC = VCC (Typ), TA=25°C
4. Only applicable to the parts that have the RESET# pin option
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9.6 SERIAL INPUT/OUTPUT TIMING
Figure 9.2 SERIAL INPUT/OUTPUT TIMING (Normal Mode) (1)
HI-Z
SO
SI
SCK
CE#
VALID IN
tCS
tCKH tCKL
tDS tDH
tCH
tCEH
tVtDIS
HI-Z
tOH
VALID IN
VALID OUTPUT
Note1. For SPI Mode 0 (0,0)
Figure 9.3 SERIAL INPUT/OUTPUT TIMING (DTR Mode) (1)
HI-Z
SO
SI
SCK
CE#
VALID IN
tCS
tCKH tCKL
tDS tDH
tCH
tCEH
tVtDIS
HI-Z
tOH
VALID INVALID IN
OutputOutput
tV
Note1. For SPI Mode 0 (0,0)
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Rev. D
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Figure 9.4 HOLD TIMING
SI
SO
SCK
CE#
HOLD#
tCHHL
tHLCH
tCHHH
tHHCH
tHZ tLZ
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9.7 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding
a simple pull-up resistor on CE# is recommended.)
Power up timing
VCC
VCC(max)
VCC(min)
V(write inhibit)
Reset State
tVCE
tPUW
Read Access Allowed Device fully
accessible
Chip Selection Not Allowed
All Write Commands are Rejected
Symbol
Parameter
Min.
Max
Unit
tVCE(1)
Vcc(min) to CE# Low
1
ms