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CY62256N Datasheet

Cypress Semiconductor Corp

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Datasheet

CY62256N
256-Kbit (32 K × 8) Static RAM
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-06511 Rev. *J Revised April 28, 2017
256-Kbit (32 K × 8) Static RA
Features
Temperature ranges
Commercial: 0 °C to +70 °C
Industrial: –40 °C to +85 °C
Automotive-A: –40 °C to +85 °C
Automotive-E: –40 °C to +125 °C
High speed: 55 ns
Voltage range: 4.5 V to 5.5 V operation
Low active power
275 mW (max)
Low standby power (LL version)
82.5 W (max)
Easy memory expansion with CE and OE Features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed and power
Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP,
28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin
reverse TSOP I packages
Functional Description
The CY62256N is a high performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power-down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
For a complete list of related documentation, click here.
A9
A8
A7
A6
A5
A4
A3
A2
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
32K x 8
ARRA
Y
I/O7
I/O6
I/O5
I/O4
A10
A13
A11
A12
A
A14
A1
0
Logic Block Diagram
CY62256N
Document Number: 001-06511 Rev. *J Page 2 of 17
Contents
Product Portfolio .............................................................. 3
Pin Configurations ........................................................... 3
Pin Definitions ..................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Typical DC and AC Characteristics .............................. 10
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community .................................17
Technical Support ..................................................... 17
CY62256N
Document Number: 001-06511 Rev. *J Page 3 of 17
Product Portfolio
Product VCC Range (V) Speed (ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (A)
Min Typ[1] Max Typ[1] Max Typ[1] Max
CY62256NLL Commercial 4.5 5.0 5.5 70 25 50 0.1 5
CY62256NLL Industrial 55/70 25 50 0.1 10
CY62256NLL Automotive-A 55/70 25 50 0.1 10
CY62256NLL Automotive-E 55 25 50 0.1 15
Pin Configurations
Figure 1. 28-pin DIP and Narrow SOIC pinout Figure 2. 28-pin TSOP I and Reverse TSOP I pinout
Pin Definitions
Pin Number Type Description
1–10, 21, 23–26 Input A0–A14. Address Inputs
11–13, 15–19, Input/Output I/O0–I/O7. Data lines. Used as input or output lines depending on operation
27 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted
20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins
14 Ground GND. Ground for the device
28 Power Supply VCC. Power supply for the device
Note
1. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA= 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
CY62256N
Document Number: 001-06511 Rev. *J Page 4 of 17
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage to ground potential
(pin 28 to pin 14) [2] .....................................–0.5 V to +7.0 V
DC voltage applied to outputs
in high Z State [2] ................................–0.5 V to VCC + 0.5 V
DC input voltage [2] .............................–0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Range Ambient Temperature (TA) [3] VCC
Commercial 0 C to +70 C5 V 10%
Industrial –40 C to +85 C 5 V 10%
Automotive-A –40 C to +85 C 5 V 10%
Automotive-E –40 C to +125 C 5 V 10%
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -55 -70 Unit
Min Typ [4] Max Min Typ [4] Max
VOH Output HIGH
voltage
VCC = Min, IOH = 1.0 mA 2.4 2.4 V
VOL Output LOW
voltage
VCC = Min, IOL = 2.1 mA 0.4 0.4 V
VIH Input HIGH
voltage 2.2 – VCC + 0.5 2.2 VCC + 0.5 V
VIL Input LOW
voltage
–0.5 – 0.8 –0.5 – 0.8 V
IIX Input leakage
current
GND VI VCC –0.5 – +0.5 –0.5 – +0.5 A
IOZ Output leakage
current GND VO VCC, output disabled –0.5 +0.5 –0.5 +0.5 A
ICC VCC operating
supply current
VCC = Max,
IOUT = 0 mA,
f = fMAX = 1/tRC
LL - Commercial 25 50 mA
LL - Industrial 25 50 25 50 mA
LL - Automotive-A 25 50 25 50 mA
LL - Automotive-E 25 50 mA
ISB1 Automatic CE
power-down
current – TTL
inputs
Max. VCC, CE VIH,
VIN VIH or VIN VIL,
f = fMAX
LL - Commercial 0.3 0.5 mA
LL - Industrial 0.3 0.5 0.3 0.5 mA
LL - Automotive-A 0.3 0.5 0.3 0.5 mA
LL - Automotive-E 0.3 0.5 mA
ISB2 Automatic CE
power-down
current – CMOS
inputs
Max. VCC,
CE VCC 0.3 V,
VIN VCC 0.3 V, or
VIN 0.3 V, f = 0
LL - Commercial 0.1 5 A
LL - Industrial 0.1 10 0.1 10 A
LL - Automotive-A 0.1 10 0.1 10 A
LL - Automotive-E 0.1 15 A
Notes
2. VIL (min) = 2.0 V for pulse durations of less than 20 ns.
3. TA is the “Instant-On” case temperature.
4. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA=25 °C, V
CC). Parameters are guaranteed by design and characterization, and not 100% tested.
CY62256N
Document Number: 001-06511 Rev. *J Page 5 of 17
Capacitance
Parameter [5] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 5.0 V 6 pF
COUT Output capacitance 8pF
Thermal Resistance
Parameter [5] Description Test Conditions DIP SOIC TSOP RTSOP Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on
a 4.25 × 1.125 inch,
4-layer printed
circuit board
75.61 76.56 93.89 93.89 C/W
JC Thermal resistance
(junction to case) 43.12 36.07 24.64 24.64 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.0 V
5 V
OUTPUT
R1 1800
R2
990
100 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
5ns <5ns
5 V
OUTPUT
R1 1800
R2
990
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.77 V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
639
Note
5. Tested initially and after any design or process changes that may affect these parameters.
CY62256N
Document Number: 001-06511 Rev. *J Page 6 of 17
Data Retention Characteristics
Parameter Description Conditions [6] Min Typ [7] Max Unit
VDR VCC for data retention 2.0 V
ICCDR Data
retention
current
LL – Commercial VCC = 2.0 V, CE VCC 0.3 V,
VIN VCC 0.3 V, or VIN 0.3 V
–0.15A
LL – Industrial/
Automotive-A –0.110A
LLAutomotive-E 0.1 10 A
tCDR[7] Chip deselect to data retention
time
0––ns
tR[7] Operation recovery time CY62256NLL-55 55 ns
CY62256NLL-70 70 –
Data Retention Waveform
Figure 4. Data Retention Waveform
3.0 V3.0 V
tCDR
VDR 2 V
DATA RETENTION MODE
tR
CE
VCC
Notes
6. No input may exceed VCC + 0.5 V.
7. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA=25 °C, V
CC). Parameters are guaranteed by design and characterization, and not 100% tested.
CY62256N
Document Number: 001-06511 Rev. *J Page 7 of 17
Switching Characteristics
Over the Operating Range
Parameter [8] Description CY62256N-55 CY62256N-70 Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 55 70 ns
tAA Address to data valid 55 70 ns
tOHA Data hold from address change 5 5 ns
tACE CE LOW to data valid 55 70 ns
tDOE OE LOW to data valid 25 35 ns
tLZOE OE LOW to low Z [9] 5–5 ns
tHZOE OE HIGH to high Z [9, 10] –2025 ns
tLZCE CE LOW to low Z [9] 5–5 ns
tHZCE CE HIGH to high Z [9, 10] –2025 ns
tPU CE LOW to power-up 0 0 ns
tPD CE HIGH to power-down 55 70 ns
Write Cycle [11, 12]
tWC Write cycle time 55 70 ns
tSCE CE LOW to write end 45 60 ns
tAW Address setup to write end 45 60 ns
tHA Address hold from write end 0 0 ns
tSA Address setup to write start 0 0 ns
tPWE WE pulse width 40 50 ns
tSD Data setup to write end 25 30 ns
tHD Data hold from write end 0 0 ns
tHZWE WE LOW to high Z [9, 10] –2025 ns
tLZWE WE HIGH to low Z [9] 5–5 ns
Notes
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 100-pF load capacitance.
9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
10. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
11. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.
12. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
CY62256N
Document Number: 001-06511 Rev. *J Page 8 of 17
Switching Waveforms
Figure 5. Read Cycle No. 1 [13, 14]
Figure 6. Read Cycle No. 2 [14, 15]
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
CY62256N
Document Number: 001-06511 Rev. *J Page 9 of 17
Figure 7. Write Cycle No. 1 (WE Controlled) [16, 17, 18]
Figure 8. Write Cycle No. 2 (CE Controlled) [16, 17, 18]
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [18, 20]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATA
IN VALID
NOTE 19
tWC
tAW
tSA
tHA
tHD
tSD
tSCE
WE
DATA I/O
ADDRESS
CE
DATA
IN VALID
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
CE
WE
tHZWE
DATA
IN VALID
NOTE 19
CY62256N
Document Number: 001-06511 Rev. *J Page 10 of 17
Typical DC and AC Characteristics
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
55 25 125
55 25 125
1.2
1.0
0.8
NORMALIZED tAA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
AMBIENT TEMPERATURE (C)
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
0.0
0.8
1.4
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED tAA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED ICC
NORMALIZED ICC, ISB
ICC
ICC
ISB
0.6
0.8
0
1.3
1.2
VIN = 5.0V
TA = 25C
1.4
55 25 105
2.5
2.0
1.5
AMBIENT TEMPERATURE (C)
1.0
0.5
0.0
–0.5
ISB
3.0
STANDBY CURRENT
ISB2 A
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
VIN = 5.0V
VCC = 5.0V
VCC = 5.0V
VIN = 5.0V
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
TA = 25C
VCC = 5.0V TA = 25C
VCC = 5.0V
vs. OUTPUT VOLTAGE
VCC = 5.0V
TA = 25C
CY62256N
Document Number: 001-06511 Rev. *J Page 11 of 17
Typical DC and AC Characteristics (continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED IPO
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1.25
1.00
0.75
10 20 30 40
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
0.0 5.0 0.0 1000 0.50
NORMALIZED ICC vs. CYCLE TIME
TA = 25 C
VCC = 5.0 V
VIN = 5.0 V
TA = 25 C
VCC = 4.5 V
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/power-down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High Z Output Disabled Active (ICC)
CY62256N
Document Number: 001-06511 Rev. *J Page 12 of 17
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
55 CY62256NLL55SNXI 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) Industrial
CY62256NLL55ZXI 51-85071 28-pin TSOP I (Pb-free)
CY62256NLL55ZXA 51-85071 28-pin TSOP I (Pb-free) Automotive-A
CY62256NLL55SNXE 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) Automotive-E
CY62256NLL55ZXE 51-85071 28-pin TSOP I (Pb-free)
70 CY62256NLL70PXC 51-85017 28-pin (600 Mil) Molded DIP (Pb-free) Commercial
CY62256NLL70SNXC 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free)
CY62256NLL70ZRXI 51-85074 28-pin Reverse TSOP I (Pb-free) Industrial
CY62256NLL70SNXA 51-85092 28-pin SNC (300 Mils) Narrow Body (Pb-free) Automotive-A
Temperature Grade: X = C or I or A or E
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C;
A = Automotive-A = –40 °C to +85 °C; E = Automotive-E = –40 °C to +125 °C
Package Type: XXX = SNX or ZX or PX or ZRX
SNX = 28-pin SNC (Pb-free)
ZX= 28-pin TSOP I (Pb-free)
PX = 28-pin Molded DIP (Pb-free)
ZRX = 28-pin Reverse TSOP I (Pb-free)
Speed Grade: XX = 55 ns or 70 ns
Low Power
Nitride Seal Mask fix
Density: 256 kbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
256 N - XX XXXXLLCY 62
CY62256N
Document Number: 001-06511 Rev. *J Page 13 of 17
Package Diagrams
Figure 10. 28-pin PDIP (1.480 × 0.550 × 0.195 Inches) P28.6/PZ28.6 Package Outline, 51-85017
Figure 11. 28-pin SNC (300 Mils) SN28.3 (Narrow Body) Package Outline, 51-85092
51-85017 *F
51-85092 *E
CY62256N
Document Number: 001-06511 Rev. *J Page 14 of 17
Figure 12. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28 (Standard) Package Outline, 51-85071
Figure 13. 28-pin TSOP I (8 × 13.4 mm) Package Outline - Reverse, 51-85074
Package Diagrams (continued)
51-85071 *J
51-85074 *H
CY62256N
Document Number: 001-06511 Rev. *J Page 15 of 17
Acronyms Document Conventions
Units of Measure
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
VFBGA Very Fine-Pitch Ball Grid Array
Symbol Unit of Measure
°C degree Celsius
Amicroampere
mA milliampere
MHz megahertz
ns nanosecond
ohm
pF picofarad
Vvolt
Wwatt
CY62256N
Document Number: 001-06511 Rev. *J Page 16 of 17
Document History Page
Document Title: CY62256N, 256-Kbit (32 K × 8) Static RAM
Document Number: 001-06511
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 426504 NXR See ECN New data sheet.
*A 488954 NXR See ECN Added Automotive product
Updated ordering Information table
*B 2715270 VKN / AESA 06/05/2009 Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017)
*C 2891344 VKN 03/12/2010 Added Table of Contents
Removed “L” product information
Updated Ordering Information table
Updated Package Diagrams (Figure 10, Figure 11, and Figure 12)
Updated Sales, Solutions, and Legal Information
*D 3119519 AJU 01/04/2011 Updated Ordering Information.
Added Ordering Code Definitions.
*E 3329873 RAME 07/27/11 Updated template and styles according to current Cypress standards.
Added acronyms and units.
Removed reference to AN1064 SRAM system guidelines.
Updated operation recovery time parameter under Data Retention
Characteristics on page 6.
*F 3433878 TAVA 11/09/11 Updated Package Diagrams.
*G 4122787 VINI 09/13/2013 Updated Package Diagrams:
spec 51-85092 – Changed revision from *D to *E.
Updated in new template.
Completing Sunset Review.
*H 4525875 VINI 10/06/2014 Updated Maximum Ratings:
Referred Note 2 in “Supply voltage to ground potential (pin 28 to pin 14)”.
Updated Package Diagrams:
spec 51-85071 – Changed revision from *I to *J.
spec 51-85074 – Changed revision from *G to *H.
Completing Sunset Review.
*I 4576406 VINI 01/16/2015 Added related documentation hyperlink in page 1.
Added Note 12 in Switching Characteristics.
Added note reference 12 in the Switching Characteristics table.
Added Note 20 in Switching Waveforms.
Added note reference 20 in Figure 9.
Updated Figure 10 in Package Diagrams (spec 51-85017 *E to *F).
*J 5718683 AESATMP7 04/28/2017 Updated Cypress Logo and Copyright.
Document Number: 001-06511 Rev. *J Revised April 28, 2017 Page 17 of 17
CY62256N
© Cypress Semiconductor Corporation, 2006-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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IC SRAM 256K PARALLEL 28TSOP I
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IC SRAM 256K PARALLEL 28TSOP I
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IC SRAM 256K PARALLEL 28DIP
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IC SRAM 256K PARALLEL 28SOIC
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IC SRAM 256K PARALLEL 28SOIC
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IC SRAM 256K PARALLEL 28TSOP I
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IC SRAM 256K PARALLEL 28SOIC
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IC SRAM 256K PARALLEL 28SOIC
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IC SRAM 256K PARALLEL 28SOIC
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