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ADUM140(0-2) Datasheet

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Datasheet

Quad-Channel Digital Isolators
Data Sheet
ADuM1400/ADuM1401/ADuM1402
Rev. L Document Feedback
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FEATURES
Qualified for automotive applications
Low power operation
5 V operation
1.0 mA per channel maximum at 0 Mbps to 2 Mbps
3.5 mA per channel maximum at 10 Mbps
31 mA per channel maximum at 90 Mbps
3 V operation
0.7 mA per channel maximum at 0 Mbps to 2 Mbps
2.1 mA per channel maximum at 10 Mbps
20 mA per channel maximum at 90 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 125°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak
TÜV approval: IEC/EN/UL/CSA 61010-1
APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Automotive systems
GENERAL DESCRIPTION
The ADuM1400/ADuM1401/ADuM14021 are quad-channel
digital isolators based on Analog Devices, Inc., iCoupler®
technology. Combining high speed CMOS and monolithic air
core transformer technology, these isolation components provide
outstanding performance characteristics superior to alternatives,
such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and
temperature and lifetime effects are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
The need for external drivers and other discrete components is
eliminated with these iCoupler products. Furthermore, iCoupler
devices consume one tenth to one sixth of the power of
optocouplers at comparable signal data rates.
The ADuM1400/ADuM1401/ADuM1402 isolators provide four
independent isolation channels in a variety of channel configu-
rations and data rates (see the Ordering Guide). All models
operate with the supply voltage on either side ranging from
2.7 V to 5.5 V, providing compatibility with lower voltage
systems as well as enabling a voltage translation functionality
across the isolation barrier. In addition, the ADuM1400/
ADuM1401/ADuM1402 provide low pulse width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives, the
ADuM1400/ADuM1401/ADuM1402 isolators have a patented
refresh feature that ensures dc correctness in the absence of input
logic transitions and when power is not applied to one of the
supplies.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
VID
NC
GND1
VDD2
GND2
VOA
VOB
VOC
VOD
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03786-001
Figure 1. ADuM1400
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
VOD
VE1
GND1
VDD2
GND2
VOA
VOB
VOC
VID
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03786-002
Figure 2. ADuM1401
DECODE ENCODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VOC
VOD
VE1
GND1
VDD2
GND2
VOA
VOB
VIC
VID
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03786-003
Figure 3. ADuM1402
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 2 of 31
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics5 V, 105°C Operation ................... 4
Electrical Characteristics3 V, 105°C Operation ................... 6
Electrical CharacteristicsMixed 5 V/3 V or 3 V/5 V, 105°C
Operation ....................................................................................... 8
Electrical Characteristics5 V, 125°C Operation ................. 11
Electrical Characteristics3 V, 125°C Operation ................. 13
Electrical CharacteristicsMixed 5 V/3 V, 125°C Operation
....................................................................................................... 15
Electrical CharacteristicsMixed 3 V/5 V, 125°C Operation
....................................................................................................... 17
Package Characteristics ............................................................. 19
Regulatory Information ............................................................. 19
Insulation and Safety Related Specifications .......................... 19
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions ......................... 22
Typical Performance Characteristics ........................................... 25
Applications Information .............................................................. 27
PC Board Layout ........................................................................ 27
Propagation Delay-Related Parameters ................................... 27
DC Correctness and Magnetic Field Immunity ..................... 27
Power Consumption .................................................................. 28
Insulation Lifetime ..................................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Automotive Products ................................................................. 31
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 3 of 31
REVISION HISTORY
12/2016Rev. K to Rev. L
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 9
Changes to Table 4 .......................................................................... 11
Changes to Table 5 .......................................................................... 13
Changes to Table 6 .......................................................................... 15
Changes to Table 7 .......................................................................... 17
Changes to Table 9 and Table 10 ................................................... 19
Changes to Ordering Guide ........................................................... 30
7/2015Rev. J to Rev. K
Changes to Table 9 and Table 10 ................................................... 19
4/2015Rev. I to Rev. J
Changed ADuM140x to ADuM1400/ADuM1401/
ADuM1402..................................................................... Throughout
Changes to Table 10 ........................................................................ 19
4/2014Rev. H to Rev. I
Change to Table 9 ............................................................................ 19
3/2012Rev. G to Rev. H
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section ................................................................. 1
Change to PC Board Layout Section ............................................ 27
Updated Outline Dimensions ........................................................ 30
Moved Automotive Products Section ........................................... 31
5/2008Rev. F to Rev. G
Added ADuM1400W, ADuM1401W, and ADuM1402W
Parts ...................................................................................... Universal
Added Table 4 .................................................................................. 11
Added Table 5 .................................................................................. 13
Added Table 6 .................................................................................. 15
Added Table 7 .................................................................................. 17
Changes to Table 12 ........................................................................ 20
Changes to Table 13 ........................................................................ 21
Added Automotive Products Section ........................................... 29
Changes to Ordering Guide ........................................................... 30
11/2007Rev. E to Rev. F
Changes to Note 1 ............................................................................. 1
Added ADuM140xARW Change vs. Temperature Parameter ... 4
Added ADuM140xARW Change vs. Temperature Parameter ... 5
Added ADuM140xARW Change vs. Temperature Parameter ... 8
Changes to Figure 17 ...................................................................... 18
6/2007Rev. D to Rev. E
Updated VDE Certification Throughout ....................................... 1
Changes to Features and Note 1 ...................................................... 1
Changes to Figure 1, Figure 2, and Figure 3 .................................. 1
Changes to Regulatory Information Section ............................... 10
Changes to Table 7 .......................................................................... 11
Added Table 10 ................................................................................ 12
Added Insulation Lifetime Section ............................................... 20
Updated Outline Dimensions........................................................ 21
Changes to Ordering Guide ........................................................... 21
2/2006Rev. C to Rev. D
Updated Format ................................................................. Universal
Added TÜV Approval ....................................................... Universal
5/2005Rev. B to Rev. C
Changes to Format ............................................................. Universal
Changes to Figure 2 .......................................................................... 1
Changes to Table 3 ............................................................................ 8
Changes to Table 6 .......................................................................... 12
Changes to Ordering Guide ........................................................... 21
6/2004Rev. A to Rev. B
Changes to Format ............................................................. Universal
Changes to Features .......................................................................... 1
Changes to Electrical Characteristics5 V Operation ................ 3
Changes to Electrical Characteristics3 V Operation ................ 5
Changes to Electrical CharacteristicsMixed 5 V/3 V or
3 V/5 V Operation ............................................................................ 7
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics Title ........................................................................ 11
Changes to the Ordering Guide .................................................... 19
5/2004Rev. 0 to Rev. A
Updated Format ................................................................. Universal
Changes to the Features.................................................................... 1
Changes to Table 7 and Table 8 ..................................................... 14
Changes to Table 9 .......................................................................... 15
Changes to the DC Correctness and Magnetic Field Immunity
Section .............................................................................................. 20
Changes to the Power Consumption Section .............................. 21
Changes to the Ordering Guide .................................................... 22
9/2003Revision 0: Initial Version
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 4 of 31
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS5 V, 105°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD25.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.19 0.21 mA
ADuM1400 Total Supply Current, Four Channels
2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 70 100 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 18 25 mA 45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current
DD2 (Q)
1.2
1.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 7.1 9.0 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 57 82 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 31 43 mA 45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
DD1
or V
DD2
Supply Current
DD1 (90)
DD2 (90)
44
62
mA
45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold
IL
EL
0.8
V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1 5.0 V IOx = −20 µA, VIx = VIxH
(VDD1 or VDD2) − 0.4 4.8 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 5 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5
PHL
PLH
20
32
50
ns
C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 15 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 10 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output8
|CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output8
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 6 of 31
ELECTRICAL CHARACTERISTICS3 V, 105°C OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent
I
DDO (Q)
0.11
0.14
mA
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 37 65 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 11 15 mA 45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
V
DD1
Supply Current
I
DD1 (Q)
1.0
1.6
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90) 30 52 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90) 18 27 mA 45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 3.0 4.2 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current IDD1 (90), IDD2 (90) 24 39 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1 3.0 V IOx = −20 µA, VIx = VIxH
(VDD1 or VDD2) − 0.4 2.8 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 7 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 38 50 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
t
PSKCD
3
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3
PW
8.3
11.1
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 16 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to
High Impedance)
t
PHZ
, t
PLH
6
8
ns
C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output8
|CM
H
|
25
35
kV/µs
V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output8
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.10 mA/
Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.03 mA/
Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 8 of 31
ELECTRICAL CHARACTERISTICSMIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, V DD2 = 3 . 0 V. These specifications do not apply to ADuM1400W, ADuM1401W,
and ADuM1402W automotive grade versions.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation 0.50 0.53 mA
3 V/5 V Operation 0.26 0.31 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
5 V/3 V Operation 0.11 0.14 mA
3 V/5 V Operation 0.19 0.21 mA
ADuM1400 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.2
1.9
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation
0.5
0.9
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 70 100 mA 45 MHz logic signal freq.
3 V/5 V Operation 37 65 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 11 15 mA 45 MHz logic signal freq.
3 V/5 V Operation 18 25 mA 45 MHz logic signal freq.
ADuM1401 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.0
1.6
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation
0.7
1.2
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq.
3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 9 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 57 82 mA 45 MHz logic signal freq.
3 V/5 V Operation 30 52 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 18 27 mA 45 MHz logic signal freq.
3 V/5 V Operation 31 43 mA 45 MHz logic signal freq.
ADuM1402 Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current IDD1 (10)
5 V/3 V Operation
5.6
7.0
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.0
4.2
mA
5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq.
3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current IDD1 (90)
5 V/3 V Operation 44 62 mA 45 MHz logic signal freq.
3 V/5 V Operation 24 39 mA 45 MHz logic signal freq.
VDD2 Supply Current IDD2 (90)
5 V/3 V Operation 24 39 mA 45 MHz logic signal freq.
3 V/5 V Operation 44 62 mA 45 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID VDD1 or VDD2,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation 0.4 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1 (VDD1 or VDD2) V IOx = −20 µA, VIx = VIxH
(V
DD1
or V
DD2
) − 0.4
(V
DD1
or V
DD2
) − 0.2
V
I
Ox
= −3.2 mA, V
Ix
= V
IxH
Logic Low Output Voltages
V
OAL
, V
OBL
,
VOCL, VODL
0.0
0.1
V
I
Ox
= 20 µA, V
Ix
= V
IxL
0.04
0.1
V
I
Ox
= 400 µA, V
Ix
= V
IxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching
7
t
PSKCD
/t
PSKOD
50
ns
C
L
= 15 pF, CMOS signal levels
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 10 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW
Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 14 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 2 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels7
tPSKOD 5 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
t
PHZ
, t
PLH
6
8
ns
C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF CL = 15 pF, CMOS signal levels
5 V/3 V Operation 3.0 ns
3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity at Logic
High Output8
|CMH| 25 35 kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output8
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D)
5 V/3 V Operation 0.19 mA/Mbps
3 V/5 V Operation 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D)
5 V/3 V Operation
0.03
mA/Mbps
3 V/5 V Operation
0.05
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 11 of 31
ELECTRICAL CHARACTERISTICS5 V, 125°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD25.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent
I
DDO (Q)
0.19
0.21
mA
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.6 3.5 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
V
DD1
Supply Current
I
DD1 (10)
7.1
9.0
mA
5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq.
For All Models
Input Currents
I
IA
, I
IB
, I
IC
,
IID, IE1, IE2
−10
+0.01
+10
µA
0 V ≤ V
IA
, V
IB
, V
IC
, V
ID
≤ V
DD1
or V
DD2
,
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold VIH, VEH 2.0 V
Logic Low Input Threshold VIL, VEL 0.8 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1 5.0 V IOx = −20 µA, VIx = VIxH
(V
DD1
or V
DD2
) − 0.4
4.8
V
I
Ox
= −3.2 mA, V
Ix
= V
IxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5
t
PHL
, t
PLH
50
65
100
ns
C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 12 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 18 27 34 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
t
PSK
15
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels
7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
t
PZH
, t
PZL
6
8
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output8
|CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output8
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 13 of 31
ELECTRICAL CHARACTERISTICS3 V, 125°C OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel,
Quiescent
IDDO (Q) 0.11 0.14 mA
ADuM1400W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 or VDD2 Supply Current IDD1 (Q), IDD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 or VDD2 Supply Current IDD1 (10), IDD2 (10) 3.0 4.2 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 V VIA, VIB, VIC, VID VDD1 or VDD2,
0 V ≤ VE1, VE2VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1 3.0 V IOx = −20 µA, VIx = VIxH
(V
DD1
or V
DD2
) − 0.4
2.8
V
I
Ox
= −3.2 mA, V
Ix
= V
IxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 75 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 14 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 34 45 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
t
PSK
22
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
t
PZH
, t
PZL
6
8
ns
C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output8
|CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output8
|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per
Channel9
IDDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per
Channel9
IDDO (D) 0.03 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 15 of 31
ELECTRICAL CHARACTERISTICSMIXED 5 V/3 V, 125°C OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.50 0.53 mA
Output Supply Current per Channel, Quiescent
I
DDO (Q)
0.11
0.14
mA
ADuM1400W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 8.6 10.6 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 1.4 2.0 mA 5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
V
DD1
Supply Current
I
DD1 (10)
7.1
9.0
mA
5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 2.2 3.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
0.9
1.5
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 5.6 7.0 mA 5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
3.0
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1
or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1
or V
DD2
Logic High Input Threshold
V
IH
, V
EH
5 V/3 V Operation 2.0 V
3 V/5 V Operation 1.6 V
Logic Low Input Threshold VIL, VEL
5 V/3 V Operation 0.8 V
3 V/5 V Operation
0.4
V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 µA, VIx = VIxH
(VDD1 or VDD2) 0.4 VDD1, VDD2 − 0.2 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 16 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
t
PSK
22
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels
7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic
High Output8
|CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic
Low Output8
|CM
L
|
25
35
kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.19 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.03 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 17 of 31
ELECTRICAL CHARACTERISTICSMIXED 3 V/5 V, 12C OPERATION1
3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These specifications apply to ADuM1400W,
ADuM1401W, and ADuM1402W automotive grade versions.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.31 mA
Output Supply Current per Channel, Quiescent
I
DDO (Q)
0.19
0.21
mA
ADuM1400W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
0.9
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 4.5 6.5 mA 5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
2.6
3.5
mA
5 MHz logic signal freq.
ADuM1401W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (Q)
1.2
1.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.7 5.4 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 4.1 5.0 mA 5 MHz logic signal freq.
ADuM1402W, Total Supply Current, Four
Channels2
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq.
VDD2 Supply Current IDD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current IDD1 (10) 3.0 4.2 mA 5 MHz logic signal freq.
VDD2 Supply Current IDD2 (10) 5.6 7.0 mA 5 MHz logic signal freq.
For All Models
Input Currents IIA, IIB, IIC,
IID, IE1, IE2
−10 +0.01 +10 µA 0 V VIA, VIB, VIC, VID VDD1 or
VDD2, 0 V ≤ VE1, VE2 VDD1 or VDD2
Logic High Input Threshold VIH, VEH 1.6 V
Logic Low Input Threshold VIL, VEL 0.4 V
Logic High Output Voltages VOAH, VOBH,
VOCH, VODH
(VDD1 or VDD2) − 0.1
VDD1, VDD2 V IOx = −20 µA, VIx = VIxH
(VDD1 or VDD2) − 0.4
VDD1, VDD2 − 0.2 V IOx = −3.2 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL,
VOCL, VODL
0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.04 0.1 V IOx = 400 µA, VIx = VIxL
0.2 0.4 V IOx = 3.2 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM1400WSRWZ/ADuM1401WSRWZ/
ADuM1402WSRWZ
Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay
5
t
PHL
, t
PLH
50
70
100
ns
C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels
Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7 tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 18 of 31
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM1400WTRWZ/ADuM1401WTRWZ/
ADuM1402WTRWZ
Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels
Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels
Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
t
PSK
22
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD 3 ns CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels
7
tPSKOD 6 ns CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High
Impedance to High/Low)
tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic High Output8
|CMH| 25 35 kV/µs VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at
Logic Low Output8
|CM
L
|
25
35
kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.1 Mbps
Input Dynamic Supply Current per Channel9 IDDI (D) 0.10 mA/Mbps
Output Dynamic Supply Current per Channel9 IDDO (D) 0.05 mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 19 of 31
PACKAGE CHARACTERISTICS
Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output)
1
R
I-O
10
12
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Case Thermal Resistance, Side 1 θJCI 33 °C/W Thermocouple located at
center of package underside
IC Junction to Case Thermal Resistance, Side 2 θJCO 28 °C/W
1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,
Pin 15, and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1400/ADuM1401/ADuM1402 are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime
section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL CSA VDE CQC TÜV
Recognized Under
UL 1577 Component
Recognition
Program1
Approved under
CSA Component
Acceptance Notice 5A
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Approved under
CQC11-471543-2012
Approved according to
IEC 61010-1:2001 (2nd Edition),
EN 61010-1:2001 (2nd Edition),
UL 61010-1:2004, and
CSA C22.2.61010.1:2005
Single Protection,
2500 V rms Isolation
Voltage
Basic insulation per
CSA 60950-1-03 and
IEC 60950-1, 780 V rms
(1103 V peak) maximum
working voltage
Reinforced insulation,
560 V peak
Basic Insulation per
GB4943.1-2011, 415 V rms
(588 V peak) maximum
working voltage, tropical
climate, altitude 5000 m
Reinforced insulation, 400 V rms
maximum working voltage
Reinforced insulation
per CSA 60950-1-03 and
IEC 60950-1, 390 V rms
(551 V peak) maximum
working voltage
File E214100 File 205078 File 2471900-4880-0001 File CQC14001114900 Certificate U8V 05 06 56232 002
1 In accordance with UL 1577, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage
detection limit = 5 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM1400/ADuM1401/ADuM1402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial
discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 10.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.8 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.8 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L(PCB) 8.3 min mm Measured from input terminals to output terminals,
shortest distance through air, and line of sight, in the
PCB mounting plane
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 20 of 31
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1050 V peak
Input to Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 896 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature TS 150 °C
Side 1 Current IS1 265 mA
Side 2 Current IS2 335 mA
Insulation Resistance at TS VIO = 500 V RS >109
CASE TEMPERATURE (°C)
SAFETY-LIMITING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE #1
SIDE #2
03786-004
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter Rating
Operating Temperature (TA)1 −40°C to +105°C
Operating Temperature (T
A
)
2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3 2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2)2, 3 3.0 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1 Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive
grade versions.
2 Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
versions.
3 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to
external magnetic fields.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 21 of 31
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter Rating
Storage Temperature (TST) −65°C to +150°C
Ambient Operating Temperature (TA)1 −40°C to +105°C
Ambient Operating Temperature (TA)2 −40°C to +125°C
Supply Voltages (VDD1, VDD2)3 −0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)3, 4 −0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)3, 4 −0.5 V to VDDO + 0.5 V
Average Output Current per Pin
5
Side 1 (IO1) −18 mA to +18 mA
Side 2 (IO2) −22 mA to +22 mA
Common-Mode Transients6 −100 kV/µs to +100 kV/µs
1 Does not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive
grade versions.
2 Applies to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade
versions.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
5 See Figure 4 for maximum rated current values for various temperatures.
6 This refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the Absolute Maximum Ratings
may cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage, Bipolar Waveform 565 V peak 50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation 1131 V peak Maximum approved working voltage per IEC 60950-1
Reinforced Insulation 560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input1 VEx Input1, 2 VDDI State1 VDDO State1 VOx Output1 Notes
H H or NC Powered Powered H
L H or NC Powered Powered L
X L Powered Powered Z
X H or NC Unpowered Powered H Outputs return to the input state within 1 µs of VDDI power restoration.
X L Unpowered Powered Z
X X Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of VDDO power restoration
if the VEx state is H or NC. Outputs return to a high impedance state
within 8 ns of VDDO power restoration if the VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 22 of 31
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
ID 6
V
OD
11
NC
7
V
E2
10
*GND
18
GND
2
*
9
NC = NO CONNECT
ADuM1400
TOP VIEW
(Not to Scale)
03786-005
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND
1
IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND
2
IS RECOMMENDED.
Figure 5. ADuM1400 Pin Configuration
Table 16. ADuM1400 Pin Function Descriptions
Pin No. Mnemonic
Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5
V
IC
Logic Input C.
6 VID Logic Input D.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
11 VOD Logic Output D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14
V
OA
Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 23 of 31
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
OD 6
V
ID
11
V
E1 7
V
E2
10
*GND
18
GND
2
*
9
ADuM1401
TOP VIEW
(Not to Scale)
03786-006
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND
1
IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND
2
IS RECOMMENDED.
Figure 6. ADuM1401 Pin Configuration
Table 17. ADuM1401 Pin Function Descriptions
Pin No.
Mnemonic
Description
1 VDD1 Supply Voltage for Isolator Side 1.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 VE1 Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled
when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10 VE2 Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA,
VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11 VID Logic Input D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2.
ADuM1400/ADuM1401/ADuM1402 Data Sheet
Rev. L | Page 24 of 31
V
DD1 1
*GND
12
V
IA 3
V
IB 4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
V
E1 7
V
E2
10
*GND
18
GND
2
*
9
ADuM1402
TOP VIEW
(Not to Scale)
03786-007
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND
1
IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND
2
IS RECOMMENDED.
Figure 7. ADuM1402 Pin Configuration
Table 18. ADuM1402 Pin Function Descriptions
Pin No. Mnemonic Description
1
V
DD1
Supply Voltage for Isolator Side 1.
2 GND1 Ground 1. Ground reference for Isolator Side 1.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 VE1 Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and
VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is
recommended.
8 GND1 Ground 1. Ground reference for Isolator Side 1.
9 GND2 Ground 2. Ground reference for Isolator Side 2.
10
V
E2
Output Enable 2. Active high logic input. V
OA
and V
OB
outputs are enabled when V
E2
is high or disconnected. V
OA
and
VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is
recommended.
11 VID Logic Input D.
12 VIC Logic Input C.
13
V
OB
Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2.
16 VDD2 Supply Voltage for Isolator Side 2.
Data Sheet ADuM1400/ADuM1401/ADuM1402
Rev. L | Page 25 of 31
TYPICAL PERFORMANCE CHARACTERISTICS
DATA RATE (Mbps)
CURRENT/CHANNEL (mA)
0
0
10
5
15
20
20 60 8040 100
5V
3V
03786-008
Figure 8. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
DATA RATE (Mbps)
CURRENT/CHANNEL (mA)
0
0
3
2
1
4
5
6
20 60 8040 100
5V
3V
03786-009
Figure 9. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
DATA RATE (Mbps)
CURRENT/CHANNEL (mA)
0
0
6
4
2
8
10
20 60 8040 100
5V
3V
03786-010
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
DATA RATE (Mbps)
CURRENT (mA)
0
0